CN110767804B

CN110767804B - Carbon nanotube device and manufacturing method thereof

Info

Publication number: CN110767804B
Application number: CN201911131392.4A
Authority: CN
Inventors: 孟令款; 肖梦梦; 张志勇; 彭练矛
Original assignee: Beijing Huatan Yuanxin Electronic Technology Co ltd; Beijing Yuanxin Carbon Based Integrated Circuit Research Institute
Current assignee: Beijing Huatan Yuanxin Electronic Technology Co ltd; Beijing Yuanxin Carbon Based Integrated Circuit Research Institute
Priority date: 2019-11-19
Filing date: 2019-11-19
Publication date: 2020-11-06
Anticipated expiration: 2039-11-19
Also published as: WO2021098546A1; CN110767804A

Abstract

The invention discloses a carbon nano tube device and a manufacturing method thereof, wherein the structure of the carbon nano tube device is positioned at the bottom of a gate electrode between side walls and consists of a plurality of transverse rod-shaped ring gate arrays, two ends of each transverse rod-shaped ring gate array are respectively connected with the carbon nano tube layers, and the outer layer of each transverse rod-shaped ring gate is coated with a gate dielectric layer and a high-K metal gate material layer. The manufacturing method of the device is also provided, firstly a dummy gate electrode structure is formed through a pre-gate process, then the carbon nano tube layer is exposed by removing the dummy gate electrode, then the dielectric material below the layer is corroded, so that the carbon nano tube layer is completely released from the carbon nano tube layer to form an unsupported structure, a gate dielectric layer, a high-K metal gate material and the like are grown on the surface of the suspended rod-shaped ring gate array, a subsequent treatment process is carried out to obtain the ring gate nano wire device meeting the requirements, and therefore the method for preparing the ring gate carbon nano tube device by integrating a self-alignment process and the traditional CMOS device technology is realized.

Description

Carbon nanotube device and manufacturing method thereof

Technical Field

The present invention relates to a carbon nanotube CMOS integrated circuit process, and more particularly, to a carbon nanotube device and a method for manufacturing the same.

Background

Carbon Nanotubes (CNTs) have advantages in terms of high speed, low power consumption, etc., and are considered to be one of the best channel materials for constructing field effect transistors in the future. In the last 20 years, the research on the application of Carbon Nanotubes (CNTs) in integrated circuits has focused on exploring new devices, physical principles, manufacturing methods, and optimization of performance and structure.

Most research has focused on planar carbon nanotube devices, i.e., carbon nanotubes need to be grown on a substrate support layer, such as silicon oxide, for use as a subsequent channel material. In practical effect, the structure is similar to a tri-gate device with an omega structure. Research shows that the device has a relatively obvious hysteresis phenomenon in the working process. The hysteresis phenomenon refers to the non-periodic variation of the output when the input signal varies periodically, which is a non-single correspondence. For field effect transistors, one important factor in the operation of the device is the stable control of voltage to current, and the stability can be divided into two types: long term stability and repeatability. The current hysteresis phenomenon is the most direct manifestation of the unrepeatability of the voltage-current regulation relationship (Dian Ming, research on the current hysteresis phenomenon and its origin in organic thin film transistors, 2014, the Master thesis of the university of double-denier). Many studies have indicated that defects present in the silicon oxide material under the carbon nanotubes or the interaction of the two have some effect on the hysteresis. Eliminating the bottom silicon oxide significantly improves the device performance of the carbon nanotubes.

On the other hand, the gate control capability of the tri-gate device with the omega-like structure is limited to a certain extent, and if the capability of the whole carbon nanotube can be exerted, the performance of the carbon nanotube device is certainly and effectively enhanced.

Compared with an omega-structure carbon nanotube device depending on a substrate, the suspended carbon nanotube device is a more perfect ring gate device, because the contact between a carbon tube and a substrate material is avoided, the current fluctuation can be effectively inhibited, and meanwhile, the gate control capability is greatly enhanced, which is beneficial to improving the device performance from the improvement of the device structure.

In a CMOS process, a process for preparing an HKMG (metal gate + High-k insulating layer) gate structure is generally divided into a front gate process and a back gate process. The chip of the HKMG gate structure manufactured by adopting the gate-last process has the advantages of lower power consumption and less electric leakage, so that the high-frequency running state is more stable, and the phenomenon of frequency reduction after running for a period of time can not occur. Compared with the prior grid process, the prior grid process is undoubtedly more advanced, but the production and manufacturing technology is complex, the yield is difficult to improve, the large-scale mass production is difficult to achieve in the early stage of the production of the technology, and a customer manufacturer is required to modify the circuit design according to the requirement in a matching manner, so the prior grid process is more popular in the early stage. Later, as the process gradually matured, and after overcoming the problems of the gate-last process, the gate-last process gradually replaced the gate-last process in recent years to become the main process for manufacturing the HKMG gate structure.

At present, there are two main methods for preparing a suspended gate-all-around carbon nanotube device:

the first method is to use photoetching exposure and etching methods to suspend the carbon nanotube, and has the disadvantages that the photoresist and the hard mask material are difficult to remove on the surface of the carbon nanotube, and the material surface of the carbon nanotube may be damaged in the process, thereby affecting the performance of the device.

The second method is to process the source and drain electrodes on the substrate in advance, and then to use the chemical vapor deposition method of in-situ growth to make the carbon nano-tube grow between the electrodes to realize suspension. Although this method avoids the influence of the above method, the carbon nanotubes are only attached to the source and drain electrode surfaces. Meanwhile, the method of processing the source and the drain in advance cannot adopt a self-alignment process, and is very difficult to perform in the follow-up process of the gate electrode.

Although there are reports of releasing carbon nanotubes from substrate materials, and simple devices have been made and tested, there are no reports of fabricating gate-all-around carbon nanotube devices that can be effectively integrated with semiconductor mass production fabrication techniques. The invention provides a new manufacturing method, which can manufacture the gate-all-around carbon nanotube device by adopting a method compatible with the semiconductor industry, and can effectively promote the application of the new device in the semiconductor industry.

Disclosure of Invention

The invention aims to provide a carbon nanotube device, wherein carbon nanotubes are completely released in the device structure, so that an unsupported suspended channel is formed, and then the carbon nanotube device is integrated with a traditional CMOS (complementary metal oxide semiconductor) device gate-last process to form a gate-all-around carbon nanotube device.

The invention provides a carbon nanotube device, which comprises a substrate, a dielectric layer covering the substrate, a carbon nanotube layer and a gate dielectric layer, wherein the gate dielectric layer is provided with a gate structure comprising a side wall and a high-K metal gate material, and the carbon nanotube device comprises the following specific components:

the lateral walls are provided with source and drain metal electrode layers on the outer sides, a transverse rod-shaped ring grid array is arranged on the plane of the carbon nano tube layer between the grooves of the lateral walls, two ends of the array are respectively connected with the carbon nano tube layers below the source and drain metal electrodes, the rod-shaped ring grid central layer is a rod-shaped carbon nano tube, an outer-layer coated grid dielectric layer and a high-K metal grid material layer, and meanwhile various single metal or multiple metal combined materials consisting of a metal grid threshold value modulation layer, a metal grid blocking layer and a lead metal layer are respectively deposited in the grooves between the lateral walls.

Preferably, the substrate is selected from the group consisting of a silicon wafer, an SOI silicon wafer, a hard insulating material such as silicon oxide, silicon nitride, quartz, glass, alumina, and the like, and a high temperature resistant flexible insulating material such as PET, PEN, polyimide, and the like, and is preferably a silicon wafer.

Preferably, the carbon nanotube layer may be a carbon nanotube film having a semiconductor ratio of > 90%, a grown carbon nanotube array, a carbon nanotube Network (Network) film, a carbon nanotube self-assembled film, and a composite layer formed by any combination of the above two.

Preferably, the source-drain metal electrode layer is selected from a single metal or an alloy thereof such as palladium, scandium, nickel-platinum alloy, titanium, cobalt, yttrium, aluminum, molybdenum, or other metals.

Preferably, the dielectric layer is silicon oxide, silicon nitride, silicon oxynitride or a composite material composed of any two or three of the above materials, and may be other insulating layer materials that are easily removed.

In another aspect, the present invention provides a method for manufacturing the carbon nanotube device, comprising the following steps:

s1: providing a substrate covered with a dielectric layer, a carbon nano tube layer and a gate dielectric layer in sequence, forming a gate structure comprising a dummy gate electrode and a side wall on the substrate, and forming source and drain metal electrode layers on two sides of the side wall;

s2: depositing a first interlayer dielectric ILD0 on the structure formed in the step S1 to cover the whole dummy gate structure, and performing CMP planarization until the surface of the dummy gate electrode is covered;

s3: removing the dummy gate electrode and the gate dielectric layer in the groove structure until the carbon nano tube is exposed, and partially removing the dielectric layer below the carbon nano tube layer until the carbon nano tube can be completely suspended to form a suspended transverse rod-shaped carbon nano tube array with two ends respectively connected with the side surfaces of the carbon nano tube layer on two sides of the groove;

s4: sequentially depositing a gate dielectric layer and a high-K metal gate material layer in the groove structure to respectively coat the outer surfaces of the suspended transverse rod-shaped carbon nanotube arrays to form a transverse rod-shaped ring gate, and continuously sequentially depositing a metal gate modulation layer, a metal gate blocking layer and a lead metal layer in the groove until the whole groove is filled;

s5: and selecting a proper CMP technology to carry out planarization after high-K metal gate materials (HKMG) are filled in the film, and then adopting subsequent processes to manufacture contact holes, hole film filling and local and global metal interconnection layers.

Preferably, the first interlayer dielectric layer ILD0 is formed by PECVD, HDPCVD deposited silicon oxide, flowable cvd (fcvd) deposited silicon oxide, spin-on dielectric SOD method.

Preferably, in step S3, a dry or wet etching technique is used to remove the dummy gate electrode.

Preferably, in step S4, the dielectric layer under the carbon nanotube layer is removed by wet etching or vapor etching or other dry etching techniques.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent by describing a carbon nanotube device structure and a method of fabricating the same with reference to the accompanying drawings in which:

fig. 1 is a perspective view of a gate-all-around structure of a carbon nanotube device.

FIG. 2 is a flow chart of a method for fabricating a nanotube device.

FIG. 3 is a schematic diagram of a structure in which a dummy gate structure and a source-drain metal electrode layer are formed on a semiconductor layer.

Figure 4 deposits and planarizes an ILD0 layer.

FIG. 5 is a schematic view of the device structure with the dummy gate electrode removed to expose the carbon nanotube layer.

FIG. 6 is a schematic diagram of a device structure in which a silicon oxide layer on a carbon nanotube substrate is partially removed to completely suspend carbon nanotubes.

Fig. 7 is a schematic diagram of the device structure after deposition of HKMG gates in the trench structures.

Fig. 8 is a schematic diagram of the device structure after CMP planarization of the HKMG filled film.

FIG. 9 is a schematic diagram of a final device structure after subsequent processes such as contact hole lithography and filling.

Fig. 10 is a schematic perspective view of the final carbon nanotube device.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Like elements in the drawings are represented by like reference numerals, and parts of the drawings are not drawn to scale. In addition, certain well known components may not be shown. For simplicity, the semiconductor structure obtained after several steps can be described in one figure.

It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.

If for the purpose of describing the situation directly above another layer, another region, the expression "a directly above B" or "a above and adjacent to B" will be used herein. In the present application, "a is directly in B" means that a is in B and a and B are directly adjacent, rather than a being in a doped region formed in B.

The invention provides a carbon nanotube device structure, as shown in fig. 1, the carbon nanotube device includes a substrate 101, a dielectric layer 102 covering the substrate 101, a carbon nanotube layer 103, and a gate dielectric layer 104, and the gate dielectric layer 104 has a gate structure including sidewalls 108 and 108' and a dummy gate electrode 107. The dielectric layer 102 may be made of silicon oxide, silicon nitride, or a composite structure of the two, or may also be made of other insulating layer materials that are easy to remove, and the gate dielectric layer 104 may be made of silicon oxide or silicon oxynitride. After a series of process steps, source and drain metal electrode layers 105 and 106 located on both sides of the side walls 108 and 108' are deposited on the carbon nanotubes 103, and a transverse rod-shaped ring gate array is arranged on the plane of the carbon nanotube layer 103 between the source and drain metal electrode layers 105 and 106. The ring grid array comprises a plurality of transverse rod-shaped ring grids 113, the two ends of each transverse rod-shaped ring grid 113 are respectively connected with a carbon nano tube layer 103, the inner layer of each transverse rod-shaped ring grid 113 is a rod-shaped carbon nano tube 110, the outer layer of each transverse rod-shaped ring grid is coated with a grid dielectric layer 111 and a high-K metal grid material layer 112, and materials such as a metal grid modulation layer, a metal grid blocking layer, a lead metal layer and the like are respectively deposited in a groove between

side walls

107 and 108.

Fig. 2 shows a process flow of a method for manufacturing a carbon nanotube device, fig. 3 to 10 specifically show specific steps of the method for manufacturing a carbon nanotube device, and a detailed description of an embodiment of the invention is provided below according to the steps shown in fig. 3 to 9.

According to step S1, as shown in fig. 3, a substrate 101 is provided, a silicon oxide layer 102, a carbon nanotube layer 103, and a gate oxide layer 104 are formed on the substrate 101, a gate structure including a dummy gate electrode 107 and a sidewall 108 is formed thereon, and source and drain metal electrode layers 105 and 106 are formed on two sides of the sidewall 107 and located on the substrate 103. The substrate 101 may be selected from a hard insulating material such as a silicon wafer, silicon oxide, silicon nitride, quartz, glass, and alumina, and a high temperature resistant flexible insulating material such as PET, PEN, and polyimide, in which the substrate 101 is a silicon wafer in this embodiment.

The carbon nanotube layer 103 is a carbon nanotube film with a semiconductor ratio of 90% -99.9999%, which may be a grown carbon nanotube array and a carbon nanotube network, i.e., a film arranged in order, a carbon nanotube self-assembled film, or a composite film combining any two of them, in this embodiment, a carbon nanotube film.

The source-drain

electrode metal layers

105 and 106 are selected from a single metal such as palladium, scandium, nickel-platinum alloy, titanium-palladium, cobalt, yttrium, aluminum, or other metals not listed here, and may be an alloy or a stack of multiple metals composed of the above single metal, mainly depending on the specific application requirements. The dummy gate electrode 107 may be silicon oxide, silicon oxynitride, or other conventional gate oxide materials, or may also be hafnium oxide, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, or lanthanum aluminum oxide, or other high-K dielectric materials, and has a thickness of 1-10 nm, in which silicon oxide having a thickness of 5nm is used in this embodiment.

Next, in step S2, as shown in fig. 4, an interlayer dielectric layer (ILD0)109 is formed on the source/drain

electrode metal layers

105 and 106, the dummy gate structure 107, and the sidewall spacers 108, and Chemical Mechanical Planarization (CMP) is performed to stop on the surface of the dummy gate electrode 107. Wherein the interlevel dielectric layer (ILD0) may be formed by depositing a layer of doped or undoped silicon oxide using CVD methods such as SACVD, PECVD, HDPCVD, or Flow CVD (FCVD) techniques applied to high aspect ratio structures, or other more advanced CVD techniques that may be developed in the future, or by spin-on processes to obtain an insulating dielectric or by depositing a low-k material. Doped silicon oxides include materials such as borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and low-k materials including, but not limited to, organic low-k materials (e.g., organic polymers containing aryl or multiple ring members), inorganic low-k materials such as amorphous carbon nitride films, polycrystalline boron nitride films, fluorosilicone glass, and the like, and porous low-k materials (e.g., disiloxane (SSQ) -based porous low-k materials, porous silica, porous SiOCH, C-doped silica, F-doped porous amorphous carbon, porous diamond, porous organic polymers), and the like.

Further according to step S3, as shown in fig. 5, the dummy gate electrode 107 and the gate oxide layer 104 in the trench structure are removed by using a dry or wet etching technique until the carbon nanotube layer 103 is exposed. As shown in fig. 6, the dielectric layer 102 under the carbon nanotube layer 103 is partially removed by wet etching, vapor etching or other suitable dry etching techniques until the carbon nanotube layer 103 can be completely suspended to form an unsupported structure, thereby forming a suspended transverse rod array 110 with two ends respectively connected to the carbon nanotube layer 103. Here 102 may be silicon oxide, silicon nitride, silicon oxynitride or a composite material of any two or three of the above, such as a composite stack of silicon nitride and silicon oxide deposited thereon, or other easily removable insulating layer materials may be used. In this embodiment, a single silicon oxide is used, which can be effectively removed by wet etching with partially diluted HF. The specific removal precision can be realized by accurately controlling the dilution ratio, thereby reducing the lateral corrosion degree.

Further according to step S4, as shown in fig. 7, a gate dielectric layer 111 and a high-K metal material layer 112 are sequentially deposited on the surface of the suspended carbon nanotube layer 110 to respectively coat the surface of each suspended transverse rod array 110, so as to form a gate-all-around structure 113, and materials such as a metal gate modulation layer, a metal gate blocking layer, and a lead metal layer are continuously deposited in the trench. The structure of the dashed frame portion in fig. 7 is shown in an enlarged view in fig. 1. Wherein the floating lateral rod array comprises a lateral plurality of rod-shaped floating gate-all-around structures 113.

Further according to step S5, as shown in fig. 8, a CMP technique is selected to planarize the high-K metal material (HKMG) filling film filled in the trench between the sidewalls, and the subsequent contact hole lithography and film filling processes are continued, specifically, a second interlayer dielectric layer (ILD1)115 is deposited on the structure obtained in step S5, and silicon oxide or a layer of SOD as an insulating dielectric is deposited by PECVD, SACVD, LPCVD, HDPCVD, or the like, or spin coating is performed. The material selection for ILD1 may be the same as or different from ILD 0. Chemical Mechanical Polishing (CMP) is further employed to planarize the interlevel dielectric layer (ILD1)115, stopping exactly a certain thickness above the gate structure as required to meet the requirements for local interconnect lines. Next, as shown in fig. 9, after the contact hole lithography and etching, a filling metal tungsten (W plug)116 and a contact hole interconnection metal 117, such as a Ti/TiN/W stack layer material, are deposited, and then contact hole CMP planarization is performed to form the final device structure shown in fig. 10. The contact hole lithography may be one-step or two-step lithography, and in this embodiment, one-step lithography is adopted, that is, the source-drain contact hole and the gate lead metal contact hole are formed at one time. In another embodiment, after the steps are completed, two-step photoetching is adopted to form the contact holes, namely, photoetching patterns of a source-drain contact area are formed firstly, photoetching patterns of two areas of contact hole interconnection metal and grid electrode connection lead metal are formed secondly, and then, a subsequent process is carried out.

Although the invention has been described in detail hereinabove with respect to specific embodiments thereof, it will be apparent to those skilled in the art that modifications and improvements can be made thereto without departing from the scope of the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims

1. A method for fabricating a carbon nanotube device, comprising:

s1: providing a substrate (101) which is sequentially covered with a dielectric layer (102), a carbon nanotube layer (103) formed by a grown carbon nanotube array film and a first gate dielectric layer (104), forming a gate structure comprising a dummy gate electrode (107) and side walls (108, 108 ') on the substrate, removing the first gate dielectric layer (104) on the outer sides of the side walls (108, 108 ') by taking the gate structure as a pattern, exposing the grown carbon nanotube array film, and forming source drain metal electrode layers (105, 106) on two sides of the side walls (108, 108 ');

s2: depositing a first interlayer dielectric ILD0 (109) on the structure formed in the step S1 to cover the whole dummy gate structure, and performing CMP planarization until the surface of the dummy gate electrode (107);

s3: removing a dummy gate electrode (107) and a first gate dielectric layer (104) in the groove structure until the grown carbon nanotube array film is exposed, removing a part of dielectric layer (102) below the grown carbon nanotube array film through wet etching or gasification etching until the carbon nanotubes are completely suspended to form a suspended transverse rod-shaped carbon nanotube (110) array with two ends respectively connected with the side surfaces of the grown carbon nanotube array film at two sides of the groove;

s4: sequentially depositing a second gate dielectric layer (111) and a high-K/metal gate material layer (112) in the groove structure to respectively coat the outer surfaces of the suspended transverse rod-shaped carbon nanotubes (110) to form a transverse rod-shaped ring gate (113) array, and continuously sequentially depositing a metal gate modulation layer, a metal gate blocking layer and a lead metal layer in the groove until the whole groove is filled;

s5: the film filled in step S4 is planarized by CMP technique, and then the subsequent processes are performed to form contact holes, hole film filling, and local and global metal interconnection layers.

2. The method of claim 1, wherein in step S3, the dummy gate electrode (107) and the first gate dielectric layer (104) are removed by a dry or wet etching technique.

3. The method of claim 1, wherein the dielectric layer (102) is silicon oxide, silicon nitride, silicon oxynitride, or a composite material of any two or three of the foregoing.

4. A carbon nanotube device manufactured by a method for manufacturing a carbon nanotube device according to any one of claims 1 to 3, comprising a substrate (101), a dielectric layer (102) on the substrate (101), a carbon nanotube layer (103) formed by a grown carbon nanotube array film, a first gate dielectric layer (104), and a channel region, a source region and a drain region defined by side walls (108, 108'), wherein:

the first gate dielectric layer (104) is positioned between the grown carbon nanotube array film and the side walls (108, 108'), and is only positioned between the channel region and the source region and between the channel region and the drain region in the horizontal direction; the side walls (108, 108') are integrally positioned above the plane of the grown carbon nanotube array film;

the source region and the drain region of the carbon nanotube device are positioned on the surface of the grown carbon nanotube array film, the source region and the drain region are provided with source and drain metal electrode layers (105, 106) which are in direct contact with the grown carbon nanotube array, and the source and drain metal electrode layers (105, 106) are selected from one or more of palladium, scandium, nickel-platinum alloy, titanium, cobalt, yttrium, aluminum and molybdenum;

the plane of the grown carbon nanotube array film in the groove between the side walls (108, 108 ') is provided with a transverse rod-shaped ring grid (113) array, two ends of the array are respectively connected with the carbon nanotube array film, the central layer of the transverse rod-shaped ring grid (113) is a rod-shaped carbon nanotube (110), the outer layer of the transverse rod-shaped ring grid is coated with a second grid dielectric layer (111) and a high K/metal grid material layer (112), and meanwhile, the groove between the side walls (108, 108') is provided with a composite layer consisting of a metal grid threshold value modulation layer, a metal grid blocking layer and a lead metal layer.

5. The carbon nanotube device according to claim 4, wherein the substrate (101) is selected from a rigid insulating material or a high temperature resistant flexible insulating material.

6. The carbon nanotube device of claim 5, wherein said rigid insulating material is selected from the group consisting of SOI silicon wafer, silicon oxide, silicon nitride, quartz, glass, aluminum oxide, and said high temperature resistant flexible insulating material is selected from the group consisting of PET, PEN, polyimide.

7. The carbon nanotube device of claim 4, wherein the substrate (101) is a silicon wafer.

8. The carbon nanotube device according to claim 4, wherein the grown carbon nanotube array film is a carbon nanotube network film, a carbon nanotube self-assembled film, or a composite layer of the two.

9. The carbon nanotube device of claim 4, wherein the dielectric layer (102) is silicon oxide, silicon nitride, silicon oxynitride, or a composite material of any two or three of the foregoing.