CN111063731A - CNT-IGZO thin film heterojunction bipolar transistor and preparation method and application thereof - Google Patents
CNT-IGZO thin film heterojunction bipolar transistor and preparation method and application thereof Download PDFInfo
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- CN111063731A CN111063731A CN201911242907.8A CN201911242907A CN111063731A CN 111063731 A CN111063731 A CN 111063731A CN 201911242907 A CN201911242907 A CN 201911242907A CN 111063731 A CN111063731 A CN 111063731A
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- 238000002360 preparation method Methods 0.000 title abstract description 13
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- 239000002238 carbon nanotube film Substances 0.000 claims abstract description 8
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- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
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- 239000000377 silicon dioxide Substances 0.000 claims description 8
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 5
- 239000003292 glue Substances 0.000 claims description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229920003229 poly(methyl methacrylate) Polymers 0.000 claims description 4
- 239000004926 polymethyl methacrylate Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
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- 239000004065 semiconductor Substances 0.000 abstract description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 14
- 239000002041 carbon nanotube Substances 0.000 description 12
- 229910021393 carbon nanotube Inorganic materials 0.000 description 12
- 238000004528 spin coating Methods 0.000 description 5
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- 229910052737 gold Inorganic materials 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 239000002109 single walled nanotube Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical class O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
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Abstract
The invention discloses a CNT-IGZO thin film heterojunction bipolar transistor and a preparation method and application thereof, wherein the CNT-IGZO thin film heterojunction bipolar transistor comprises an IGZO layer and a CNT thin film covering the surface of the IGZO layer; the preparation method comprises the steps of preparing the IGZO layer as a channel material by adopting a radio frequency magnetron sputtering method, and depositing the CNT film on the surface of the IGZO layer by adopting a solution dripping method. According to the invention, the upper surface of the IGZO prepared by the radio frequency magnetron sputtering method is very flat, the roughness is less than 0.2nm, and the P-type CNT film is directly deposited on the surface of the IGZO, so that the electrical property of a P-type organic semiconductor can be close to that of an N-type oxide semiconductor, and compared with the prior art, the electrical property of the bipolar transistor is effectively improved, large-area array can be realized, and the application prospect is very wide.
Description
Technical Field
The invention belongs to the technical field of electronic devices, and particularly relates to a CNT-IGZO thin film heterojunction bipolar transistor and a preparation method and application thereof.
Background
With the development of the purification technology of the semiconducting carbon nano tube, the semiconducting carbon nano tube with high purity can be obtained at present, and the high-purity carbon nano tube shows p-type characteristics at room temperature and has high hole mobility; in addition, the semiconductor carbon nano tube has good application prospect in the aspect of flexible transparent logic circuits due to good flexibility and a simple large-area preparation method.
The complementary p-channel and n-channel inverter transistors in the logic circuit are the most effective and energy-saving design, however, for the semiconducting carbon nanotubes, because the band gap is narrow (about 1.5 eV), holes are mainly transported as main carriers at room temperature, so that n-type carbon nanotubes are less existed, and the existing small amount of n-type semiconducting carbon nanotubes are difficult to match due to the low performance, such as mobility, of the n-type semiconducting carbon nanotubes, which needs to undergo a series of processing and packaging treatments and lower testing temperature, so that the n-type semiconducting material with the matched performance needs to be searched again.
The oxide semiconductor has higher mobility, has the advantages of low-temperature preparation, low cost, good uniformity and the like, and completely meets the requirements of logic circuits. The carbon nano tube and oxide semiconductor combined heterojunction has the advantages of simple processing technology, diversified methods, low cost, easy packaging, compatibility with a flexible substrate, capability of processing at room temperature, large-area batch production and the like, can reduce the process flow and reduce the cost in the preparation of the transparent logic circuit, and can completely meet the increasing demands of people on novel electronic products.
In the prior art, large-area array preparation of the InGaZn and semiconductor carbon nanotube heterostructure bipolar transistor is realized at room temperature, and theoretical and experimental support is provided for subsequent application to a CMOS circuit. However, in the prior art, the SWCNT/IGZO heterojunction bipolar transistor is prepared by using a solution method, and since the purity of the selected CNT is low and the performance is relatively poor, and the mobility of the IGZO prepared by using the solution method is low, the performance of the bipolar transistor prepared by using the SWCNT/IGZO heterojunction bipolar transistor is poor, and Al is used as a source electrode and a drain electrode of the device, so that a large contact resistance is generated between the electrode and the IGZO, and the performance of the device is further influenced.
The present invention has been made in view of the above circumstances.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a CNT-IGZO thin film heterojunction bipolar transistor and a preparation method and application thereof.
In order to achieve the purpose, the invention adopts the following technical scheme:
a CNT-IGZO thin film heterojunction bipolar transistor comprises an IGZO layer and a CNT thin film covering the surface of the IGZO layer.
In the technical scheme, the IGZO layer is prepared by a radio frequency magnetron sputtering method, and the roughness of the surface of the IGZO layer, which is in contact with the CNT film, is less than 0.2 nm.
In the above technical solution, the thickness of the CNT thin film is less than 5nm, preferably 1-3 nm.
In the above technical solution, the thickness of the IGZO layer is 12 to 30nm, preferably 15 to 24nm, and more preferably 20 nm.
Further, in a preferred embodiment, the CNT-IGZO thin film heterojunction bipolar transistor comprises a heavily doped P-type silicon wafer, a silicon dioxide layer, an IGZO layer, a CNT thin film, a metal source electrode and a metal drain electrode, wherein the silicon dioxide layer and the IGZO layer are sequentially disposed on the heavily doped P-type silicon wafer from bottom to top, the metal source electrode and the metal drain electrode cover the surface of the IGZO layer, and the CNT thin film covers the surface of the IGZO layer between the metal source electrode and the metal drain electrode.
Specifically, in the above technical solution, the thickness of the silicon dioxide layer is 250-360nm, preferably 300 nm.
Specifically, in the above technical solution, the metal source electrode and the metal drain electrode are Ti/Au electrodes;
preferably, in the above technical solution, the size of the metal source electrode and the metal drain electrode is 250 μm × 250 μm.
The invention also provides a preparation method of the CNT-IGZO thin film heterojunction bipolar transistor, which comprises the following steps:
s1, preparing an IGZO layer as a channel material by adopting a radio frequency magnetron sputtering method;
and S2, depositing a CNT film on the surface of the IGZO layer by adopting a solution drop coating method.
Specifically, in a preferred embodiment, step S1 is to perform rf magnetron sputtering on the IGZO layer and perform annealing at 280-.
Specifically, in a preferred embodiment, in step S2, a patterned metal electrode array is prepared by uv lithography-evaporation, and then PMMA glue is spin-coated, where the parameters are spin-coating at 480-550rpm for 4-6S, then spin-coating at 2600-3250rpm for 50-75S, and developing to obtain a pattern at the channel, and then CNT solution is drop-coated, and the pattern is obtained after acetone photoresist removal.
The invention also provides application of the CNT-IGZO thin film heterojunction bipolar transistor or the preparation method in preparation of photoelectric devices.
The invention has the advantages that:
according to the invention, the upper surface of the IGZO prepared by the radio frequency magnetron sputtering method is very flat, the roughness is less than 0.2nm, and the P-type CNT film is directly deposited on the surface of the IGZO, so that the electrical property of a P-type organic semiconductor can be close to that of an N-type oxide semiconductor, and compared with the prior art, the electrical property of the bipolar transistor is effectively improved, large-area array can be realized, and the application prospect is very wide.
Drawings
FIG. 1 is a schematic structural diagram of a CNT-IGZO thin film heterojunction bipolar transistor according to an embodiment of the present invention;
FIG. 2 is a graph showing the transfer and output curves of a CNT-IGZO thin film heterojunction bipolar transistor according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples.
The following examples are intended to illustrate the present invention, but not to limit the scope of the invention, which is defined by the claims.
Unless otherwise specified, the test reagents and materials used in the examples of the present invention are commercially available.
Unless otherwise specified, the technical means used in the examples of the present invention are conventional means well known to those skilled in the art.
In the following examples, a high purity carbon nanotube solution (toluene as solvent) was provided by the mr group of zhao mon, zu nano-institute, having a purity of 99%; the IGZO target is a commercial product and purchased from new research in gold; the optical microscope was purchased from Leica corporation under model number DM 4000M; the electron beam evaporation coating system (O-50B) is purchased from Chongwen science and technology GmbH; vacuum probe station available from Lake Shore; the magnetron sputtering equipment is of the type ACS-4000-C4 and is purchased from ULVAC company; a scanning electron/focused ion beam dual beam system (SEM/FIB) was purchased from FEI, Inc., USA, the Netherlands.
Examples
The radio frequency magnetron sputtering power is 50-150W, the ratio of argon to oxygen is 12:1, the sputtering gas is 0.6-0.75Pa, an IGZO active layer with the thickness of 20nm is prepared, and annealing is carried out for 1 hour at the temperature of 300 ℃ in the oxygen atmosphere. The method comprises the following steps of (1) dripping a high-purity semiconductor type carbon nanotube solution on an IGZO semiconductor active layer, wherein the specific process comprises the steps of exposing an electrode pattern on an IGZO thin film by adopting an ultraviolet lithography technology, and finally obtaining patterning through a developing solution; performing electron beam evaporation on the patterned substrate, firstly evaporating 5nm titanium as an adhesion layer, then evaporating 30nm gold as a source electrode and a drain electrode, and removing glue after evaporation to obtain a patterned metal electrode array; spin-coating PMMA glue, spin-coating for 5s at 500rpm, then spin-coating for 60s at 3000rpm, developing to obtain a pattern at a channel, then dropwise coating a CNT solution, and performing acetone photoresist removal treatment to obtain the PMMA glue, wherein the size of an electrode is 250 micrometers by 250 micrometers, the length of the channel is 40 micrometers, and the width of the channel is 500 micrometers.
As shown in fig. 1, the structure of the solar cell comprises a heavily doped P-type silicon wafer, a silicon dioxide layer, an IGZO layer, a CNT film, a metal source electrode and a metal drain electrode, wherein the silicon dioxide layer and the IGZO layer are sequentially arranged on the heavily doped P-type silicon wafer from bottom to top, the metal source electrode and the metal drain electrode cover the surface of the IGZO layer, and the CNT film covers the surface of the IGZO layer between the metal source electrode and the metal drain electrode.
The devices were electrically characterized in a vacuum probe station, and the results are shown in fig. 2.
Fig. 2.a and 2.b are transfer curves of a bipolar transistor in hole and electron enhancement modes, respectively. The transfer curve shows a typical V-shaped bipolar field effect transfer characteristic relationship, and it can be seen that the gate voltage corresponding to the p-n turning point changes along with the change of bias voltage applied to two ends of the source drain, and the change can be interpreted as the transition between an actual source drain and a nominal source drain electrode. Fig. 2 c and 2 d are output characteristic curves of the bipolar transistor in electron and hole enhancement modes, respectively, from which it can be seen that at a lower positive gate voltage, the transistor shows a diode-like curve characteristic, and the source-drain current increases exponentially with the source-drain voltage, which is a typical characteristic of the bipolar transistor.
As can be seen from the results of comprehensively analyzing the transfer characteristic and output characteristic curves of the four groups of corresponding transistors in fig. 2, the CNT-IGZO thin film heterojunction bipolar transistor prepared according to the embodiment of the present invention finally exhibits bipolar characteristics, and the corresponding on-state current, i.e., carrier mobility, is much improved compared with the literature reports.
Finally, the above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The CNT-IGZO thin film heterojunction bipolar transistor is characterized by comprising an IGZO layer and a CNT thin film covering the surface of the IGZO layer.
2. The CNT-IGZO thin film heterojunction bipolar transistor according to claim 1, wherein the IGZO layer is prepared by a radio frequency magnetron sputtering method, and a surface of the IGZO layer in contact with the CNT thin film has a roughness of less than 0.2 nm.
3. The CNT-IGZO thin film heterojunction bipolar transistor of claim 1, wherein the CNT thin film has a thickness of less than 5nm, preferably 1-3 nm.
4. The CNT-IGZO thin film heterojunction bipolar transistor according to claim 1, wherein the thickness of the IGZO layer is 12-30nm, preferably 15-24nm, and more preferably 20 nm.
5. The CNT-IGZO thin film heterojunction bipolar transistor according to any one of claims 1 to 4, comprising a heavily doped P-type silicon wafer, a silicon dioxide layer, an IGZO layer, a CNT thin film, a metal source electrode and a metal drain electrode, wherein the silicon dioxide layer and the IGZO layer are sequentially disposed on the heavily doped P-type silicon wafer from bottom to top, the metal source electrode and the metal drain electrode cover the surface of the IGZO layer, and the CNT thin film covers the surface of the IGZO layer between the metal source electrode and the metal drain electrode.
6. The CNT-IGZO thin film heterojunction bipolar transistor of claim 5, wherein the thickness of the silicon dioxide layer is 250 nm and 360nm, preferably 300 nm.
7. The CNT-IGZO thin film heterojunction bipolar transistor of claim 5, wherein the metal source electrode and the metal drain electrode are Ti/Au electrodes;
preferably, the size of the metal source electrode and the metal drain electrode is 250 μm.
8. The method of fabricating the CNT-IGZO thin film heterojunction bipolar transistor of any of claims 1 to 7, comprising:
s1, preparing an IGZO layer as a channel material by adopting a radio frequency magnetron sputtering method;
and S2, depositing a CNT film on the surface of the IGZO layer by adopting a solution drop coating method.
9. The method according to claim 8,
step S1 is specifically to carry out radio frequency magnetron sputtering on the IGZO layer and anneal for 50-75min at the temperature of 280-325 ℃ in the oxygen atmosphere under the conditions that the power is 50-150W, the deposition pressure is 0.6-0.75Pa and the deposition atmosphere is the mixed gas of argon and oxygen with the volume ratio of 12: 1;
and/or step S2 is specifically to adopt ultraviolet lithography-evaporation to prepare a patterned metal electrode array, then spin-coat PMMA glue, specifically, spin-coat for 4-6S at 480-550rpm, then spin-coat for 50-75S at 2600-3250rpm, and obtain the pattern at the channel through development, then drip-coat the CNT solution, and obtain the product after acetone photoresist removal treatment.
10. Use of the CNT-IGZO thin film heterojunction bipolar transistor according to any of claims 1 to 7 or the fabrication method according to any of claims 8 to 9 for the fabrication of optoelectronic devices.
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Cited By (3)
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| CN113193001A (en) * | 2021-04-25 | 2021-07-30 | 国家纳米科学中心 | Flexible CMOS inverter and preparation method thereof |
| CN114361253A (en) * | 2021-12-29 | 2022-04-15 | 东南大学 | Oxide semiconductor bipolar transistor and preparation method thereof |
| WO2023216124A1 (en) * | 2022-05-11 | 2023-11-16 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, and circuit |
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Cited By (3)
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| CN113193001A (en) * | 2021-04-25 | 2021-07-30 | 国家纳米科学中心 | Flexible CMOS inverter and preparation method thereof |
| CN114361253A (en) * | 2021-12-29 | 2022-04-15 | 东南大学 | Oxide semiconductor bipolar transistor and preparation method thereof |
| WO2023216124A1 (en) * | 2022-05-11 | 2023-11-16 | 京东方科技集团股份有限公司 | Thin film transistor and preparation method therefor, and circuit |
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