JPH03297170A - Semiconductor device and logic circuit using it - Google Patents

Abstract

PURPOSE:To periodically modulate conductivity by disposing via an insulating film a second gate electrode at a part of a first gate electrode between second conductivity type source and drain regions formed in a predetermined distance on a first conductivity type semiconductor substrate surface. CONSTITUTION:On a p-type Si substrate an element isolation region 9 is formed and then a gate oxide film 6 is formed by a heat treatment, on which a polycrystalline silicon 10 is deposited for protection of the film 6. Then, a resist is applied and opening parts are provided in two n<+> diffusion layer regions for a source region 1 and a drain region 2. A resulting sample is implanted with arsenic ion and annealing is performed by a heat treatment in a nitrogen atmosphere. Then, polycrystalline silicon is deposited and phosphorous deposition is performed with an heat treatment. Thus, a first gate electrode 3 is yielded by dry etching. Then a silicon oxide film as an interlayer insulating film 7 and then polycrystalline silicon are deposited into a second gate electrode 4 with the same treatment. Thereafter, the film 7 is again deposited to open a contact hole and lay an aluminum wiring 11. Thus, FET conductivity can periodically be modulated.

Description

[Detailed description of the invention]

[Field of Industrial Application] The present invention relates to a semiconductor device having an insulated gate type (MIS type) field effect transistor that utilizes energy quantization through one-dimensional conduction, and a logic circuit using the field effect transistor, and in particular to a nonlinear The present invention relates to a semiconductor device having a MIS type field effect transistor having such characteristics and a logic circuit using the field effect transistor. [Prior Art] Most conventional transistors that utilize one-dimensional conduction of electrons utilize the increased mobility of electrons, and new conduction characteristics have been achieved by controlling the discontinuous energy levels. There isn't. Regarding the one-dimensional conduction of electrons, for example, the Japanese
Journal of Applied Physics, Volume 19, Number 12, December, 1980, pp
, L735-L738 (Japanese Journ
al of Applied Physics, vo
l. 19, No, 12. December, 1980
．． pp, L735-L738), and it has been pointed out that in one-dimensional conduction, scattering is significantly suppressed, so mobility increases. [Problems to be Solved by the Invention] The above-mentioned conventional techniques utilize the increase in mobility in one-dimensional conduction, and do not control the discrete energy levels. An object of the present invention is to control discrete energy levels caused by -dimensional conduction and to realize a semiconductor device having an MIS type field effect transistor that realizes new conduction characteristics not seen before, and a semiconductor device using the field effect transistor. Its purpose is to provide logic circuits.

[Means for Solving the Problems] The above objects include (1) a semiconductor substrate of a first conductivity type; An insulated gate field effect transistor includes source and drain regions of a second conductivity type and a first gate electrode formed on the semiconductor substrate between the source and drain regions via a gate insulating film. A semiconductor device, characterized in that a second gate electrode is disposed in a portion of the first gate electrode via an insulating film, (2) the semiconductor device according to 1 above, wherein the first gate electrode (3) In the semiconductor device according to item 1 above, the width of the first gate electrode is 0.1 μm or less.
A semiconductor device characterized in that the channel formed by the first gate electrode has a width constituting one-dimensional conduction of electrons, (4) the semiconductor device according to 1.2 or 3 above, in which the second A semiconductor device characterized in that a gate electrode has a width of 0.1 μm or less, (5) a semiconductor substrate of a first conductivity type, and a first conductivity type formed on a surface of the semiconductor substrate at a predetermined interval. source and drain regions of a second conductivity type that are of a different conductivity type, and a gate electrode formed on the semiconductor substrate via a gate insulating film to form a channel between the source and drain regions. (6) A semiconductor device having an insulated gate field effect transistor, characterized in that it has means for controlling a quantized energy level of the energy of electrons traveling in the channel, (6) the semiconductor device according to item 5 above; In semiconductor devices, control of quantized energy level is
A semiconductor device characterized in that the second gate electrode is electrically floating with an IA# film interposed therebetween; (7) In the semiconductor device described in 5 above, the width of the gate electrode is determined by the gate electrode. The channel formed is one electron
(8) In the semiconductor device described in 5.6 or 7 above, the portion whose energy level of the channel is controlled has a length of 0. .1 μm or less, (9) a semiconductor device of a first conductivity type;
A semiconductor device having an insulated gate field effect transistor comprising source and drain regions of a second conductivity type, which are of a conductivity type different from the conductivity type, and a channel formed between the source and drain regions. A semiconductor device characterized in that a gate electrode is disposed in a portion of the channel with an insulating film interposed therebetween. (10) The semiconductor device according to 9 above, wherein the width of the channel is 0.1 μm or less; (11) The semiconductor device according to 9 above,
A semiconductor device characterized in that the width of the channel is such that the channel constitutes one-dimensional conduction of electrons, (12
) In the semiconductor device according to 9.10 or 11 above,
A semiconductor device characterized in that the gate electrode has a width of 0,1 μm or less, (13) a semiconductor substrate of a first conductivity type, and a semiconductor substrate formed at a predetermined interval on the surface of the semiconductor substrate,
a source and drain region of a second conductivity type that is a conductivity type different from the first conductivity type; and a first gate electrode provided on the semiconductor substrate between the source and train regions with a gate insulating film interposed therebetween; , has a Ma gate type field effect transistor consisting of a second gate electrode provided on a portion of the first gate electrode via an insulating film, and is connected to the second gate electrode via a resistor, respectively. and two input terminals. A logic circuit comprising: an output terminal connected to one of the source and drain regions; a power terminal connected via a resistor; and a ground terminal connected to the other of the source and drain regions; 14) A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type different from the first conductivity type formed at a predetermined interval on the surface of the semiconductor substrate, and the source. , a gate electrode provided on the semiconductor substrate via a gate insulating film to form a channel between the drain regions, and means for controlling the quantized energy level of the energy of electrons traveling through the channel. It has two input terminals each connected to the means for controlling the energy level via a resistor, an output terminal connected to one of the source and drain regions, and a resistor. (15) a logic circuit comprising: a power supply terminal connected to the semiconductor substrate; and a ground terminal connected to the other of the source and drain regions; (15) a semiconductor substrate of a first conductivity type; formed at predetermined intervals,
a source and train region of a second conductivity type different from the first conductivity type; a channel provided between the source and drain regions; and a channel provided in a portion of the channel via an insulating film. an insulated gate field effect transistor consisting of a gate electrode, two input terminals each connected to the gate electrode via a resistor, an output terminal connected to one of the source and drain regions, and a resistor. This is achieved by a logic circuit characterized in that it has a power terminal connected to the power supply terminal via the logic circuit, and a ground terminal connected to the other of the source and drain regions. [Function] In order to explain the present invention in detail, FIG. 1(a) shows a plan view of an example of a field effect transistor of the present invention, and FIG. 1(b) shows a cross-sectional view taken along line AA'. A first gate electrode 3 for forming a channel is provided between a source region 1 and a drain region 2, and a second gate electrode 4 is provided on a portion of the first gate electrode 3. The following discussion will proceed assuming that the field effect transistor in FIG. 1 is an N-MOS. First, referring to FIG. 1, the drain current and gate voltage characteristics in the case where the second gate electrode 4 is not provided will be explained. 1st
When a positive potential is applied to the first gate electrode to form a channel, energy is quantized at low temperatures due to one-dimensional conduction if the width of the first gate electrode is sufficiently narrow. FIG. 2 shows the energy level of channel 8 at that time. In the case of one-dimensional electrons, the density of states DO81(E) is given by DO8,(E)ccE-172. At this time, assuming that the potential under the first gate is a well-type potential, the interval ΔE between energy levels is expressed by equation (1). ΔE= (2n+1)h”/8mW2 (1)n
is the quantum number counted from the lower energy band, h is the blank constant, m is the effective mass of the electron, and W is the channel width. Now, let's increase the first gate voltage. As the first gate voltage increases, the electron density in the channel increases. By the way, the Fermi energy EF is given by the electron density ns as follows. EF=h"n5"78m In other words, increasing the gate voltage is equivalent to increasing the Fermi energy of the electron. To explain using FIG. 2, as the gate voltage is increased, the Fermi energy increases. That is, in FIG. 2, EF increases from the bottom. E
When F matches the quantized energy level, a current flows. When EF increases further, the current decreases. The current increases again when it matches the next quantized energy level. In this way, when EF coincides with the quantized energy level, the current value takes a maximum value, and the dependence of the current on the gate voltage becomes as shown in FIG. Next, let us consider a structure in which an electrically floating second gate electrode is provided. When a negative potential is applied to the second gate electrode 4 in FIG. 1, the inversion of the peripheral portion of the first gate electrode 3 is suppressed as shown in FIG. The width of the channel 8 formed can be narrowed. FIG. 4(a) shows the channel 8 when the second gate voltage is O■, and FIG. 4(b) shows the channel 8 when the second gate voltage is negative potential.
Indicates the width of This means that the width of the channel 8 can be changed by the second gate electrode 4. In fact, narrowing of the band by 10-15% is possible. By the way, as can be seen from equation (1), changing the channel width means changing the interval between energy levels. Specifically, as the channel width becomes narrower, the spacing between energy levels becomes wider. If we focus on the same energy level, the energy level will increase. When a negative potential is applied to the second gate electrode to raise the energy level, no current flows. When the level rises further and reaches the next level, current flows. Therefore, the second gate voltage dependence of the current in this device is, for example, as shown in FIG. 5(a), and the current-voltage characteristic is as shown in FIG. 5(b). [Example] An example of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 6 is a manufacturing process diagram of a semiconductor device having an MIS type field effect transistor according to an embodiment of the present invention. Element isolation regions 9 are formed on a p-type Si substrate 5 with a specific resistance of 10 Ω by the usual LOCO8 method. Then, 850℃, 30
A 10 nm thick gate oxide film 6 is formed by a dry oxidation method. 5 by CVD method for the purpose of protecting the gate oxide film 6.
0 nm thick polycrystalline silicon 1o is deposited. A resist is applied to a thickness of 1 μm, openings are formed in predetermined portions by photolithography, that is, two n-diffusion layer regions for source region 1 and drain region 2, and arsenic ions are formed at an acceleration voltage of 120°C. Type in. The implantation amount was lXl0"cm-". Of course, these diffusion layer regions may be formed using phosphorus ions. An annealing step is performed at 900° C. for 10 minutes in a nitrogen atmosphere (FIG. 6(a)). Next, 50 nm of polycrystalline silicon is deposited by CVD, and phosphorus is deposited at 875° C. for 20 minutes. After that, the width was 0.08 by photolithography and dry etching.
A polycrystalline silicon film is processed into a micrometer-thin line shape to form the first gate electrode 3 (FIG. 6(b)). Next, as an interlayer insulating film 7, a PS G film with a thickness of 50 nm is formed.
A silicon oxide film (Phospho 5 Ilicate Glass) film is deposited by the LPCVD method. Next, 1100n of polycrystalline silicon was deposited by CVD method,
Perform phosphorus deposition at 875°C for 20 minutes. Thereafter, by photolithography and dry etching, a polycrystalline silicon crotch is processed to have a width of 0.3 μm in a shape that covers a part of the thin line-shaped first gate 1- formed earlier, thereby forming a second gate electrode 4. (Figure 6(C)). Then, PSG (Phosp) was applied to a thickness of 200 nm.
h. A silicon oxide film 7 such as Sj, 1icate glass) film is deposited by the LPCVD method to serve as an interlayer insulating film, contact holes are opened by photolithography and dry etching, and aluminum wiring 11 is provided, as shown in FIG. 6(d). Make it. Through the above process, a desired semiconductor device was obtained, whose main parts are shown in plan view in FIG. The device obtained as above exhibited conduction characteristics as shown in Figures 5(a) and (b).In this example, a p-type substrate was used, but if all polarities were changed, an n-type substrate could be used. A P-channel MIS type field effect transistor can also be realized. Example 2 The semiconductor device shown in FIG. 7 was obtained by the same process as in Example 1. The difference from Example 1 is that the width of the second gate electrode is 0.05 μm, and the electrons in the part where the energy level is controlled are close to the O dimension, and the density of states is 8th. As shown in Figure (a), it is completely discontinuous. Furthermore, as the influence of scattering in this region is suppressed, the conduction becomes close to parisistic. In addition, for comparison, Fig. 8(b) shows the second
The density of states of electrons under the first gate electrode with no gate electrode on top is shown. As a result, in this example, as shown in FIG. 9, vibrations could be made clearer than in Example 1. Embodiment 3 FIG. 10 is a manufacturing process diagram of a semiconductor device having an MIS type field effect transistor according to another embodiment of the present invention. Ordinary LOC on O degree off p-type Si substrate 5 with specific resistance 10Ω・■
Element isolation regions (not shown) are formed using the O8 method. Next, a resist was applied to a thickness of 1 μm, and the shape shown in FIG. 10(a) was obtained by photolithography and hydrazine etching. Of course, instead of hydrazine etching,
An etching technique that is dependent on surface orientation may be used; the point is to form a shape with a sharp tip as shown in FIG. 1o (, ). Thereafter, a resist is applied to a thickness of 1 μm, and an opening is formed at a predetermined portion by photolithography, that is, at the apex of the central triangle in FIG. 10(a), which is the channel region, for the purpose of threshold voltage control. Then, phosphorus ions are implanted by lXl0"cm-" at an accelerating voltage of 40kV. Of course,
Arsenic ions may be used for this implantation. Next, Si0.6' is deposited by CVD. Thereafter, a resist is applied to a thickness of 1 μm, and predetermined areas, ie, source region 1 and drain region 2, are formed by photolithography.
The two? An opening is provided in the diffusion layer region, and arsenic ions are implanted at an accelerating voltage of 120 kV. The amount of input is IXIO
Of course, these n-diffusion layer regions may be formed using phosphorus ions.An annealing process in a nitrogen atmosphere at 900°C for 10 minutes results in the formation of the n-diffusion layer regions as shown in FIG. 10(b). Next, 1100n of polycrystalline silicon was deposited and heated at 875°C for 2
Perform 0 minute phosphorus deposition. Thereafter, the polycrystalline silicon film was processed by photolithography and dry etching to form a second gate electrode 4 having a width of 0.3 μm, as shown in FIG. 10(c). Thereafter, aluminum electrode wiring 17 was formed by the same process as in Example 1, resulting in the result as shown in FIG. 10(d). According to this example, as a result of forming a channel at the apex of the triangle, it is possible to form a much narrower channel than in Example 1, so that the characteristics (vibration) are more clear than those shown in FIG. can be obtained. Although a p-type substrate is used in this embodiment, a p-channel MIS type field effect transistor using an n-type substrate can also be realized by changing all polarities. Example 4 The semiconductor device shown in FIG. 11 was obtained by the same process as in Example 3. The difference from Example 3 is that the width of the second gate is 0.05 μm, and the electrons in the part where the energy level is controlled are close to O-dimensional, and the density of states is as shown in Figure 8 ( It is completely discontinuous as shown in a). Furthermore, as the effects of scattering are suppressed, the conduction becomes close to parisistic. As a result, in this example, vibration could be made clearer than in Example 3. Embodiment 5 FIG. 12 is a circuit diagram of an example in which an exclusive OR circuit is constructed using the semiconductor devices in Embodiments 1 to 4. The two output terminals VINI and V I N 2 are each connected to the second gate electrode 4 via a resistor, and the output terminal Vo
ut to either source 1' or drain 2', and power supply terminal VD to source 1' or drain 2' via a resistor.
and the other of the source 1' or drain 2' is grounded. When a semiconductor device having the characteristics as shown in FIG. 13 is used, the output with respect to the input becomes as shown in Table 1, and an exclusive OR can be constructed. (Left below) Table 1 [Effects of the Invention] According to the present invention described above, by utilizing the control of discontinuous energy levels formed due to one-dimensional conduction,
The conductivity of the MIS field effect transistor can be periodically modulated by the gate electrode. this is,
Characteristics that would require a complex circuit configuration in a macro device are achieved with a single, minute element. In this sense, the present invention can be effective for future LSIs and the like.

[Brief explanation of drawings]

FIG. 1(a) is a plan view of one embodiment of the field effect transistor of the present invention, FIG. 1(b) is a sectional view taken along line AA', and FIG.
FIG. 3 is a diagram showing energy levels, FIG. 3 is a diagram showing voltage-current characteristics of a one-dimensional channel MO8 type field effect transistor, and FIG. 4 is a cross-sectional view of the device to explain the function of the second gate electrode. FIG. 5 is a diagram showing the second gate voltage dependence of current and a diagram showing voltage-current characteristics, FIG. 6 is a manufacturing process diagram of the field effect transistor of Example 1, and FIG. 7 is Example 2.
8 is a cross-sectional view of a field effect transistor of
FIG. 9 is a diagram showing the characteristics of the field effect transistor of Example 2, FIG. 10 is a diagram showing the manufacturing process of the field effect transistor of Example 3, and FIG. 11 is a diagram showing the field effect transistor manufacturing process of Example 4. FIG. 12 is a sectional view of a field effect transistor, and FIG. 12 is an exclusive OR circuit diagram constructed according to the present invention.
FIG. 3 is a characteristic diagram of a semiconductor device when an exclusive OR circuit is realized.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of a first conductivity type, and a source of a second conductivity type, which is of a conductivity type different from the first conductivity type, formed at a predetermined interval on the surface of the semiconductor substrate; In a semiconductor device having an insulated gate field effect transistor comprising a drain region and a first gate electrode formed on the semiconductor substrate between the source and drain regions via a gate insulating film, the first A semiconductor device characterized in that a second gate electrode is disposed in a portion of the gate electrode with an insulating film interposed therebetween. 2. The semiconductor device according to claim 1, wherein the first gate electrode has a width of 0.1 μm or less. 3. The semiconductor device according to claim 1, wherein the width of the first gate electrode is such that a channel formed by the first gate electrode constitutes one-dimensional conduction of electrons. Semiconductor equipment. 4. The semiconductor device according to claim 1, 2 or 3,
A semiconductor device characterized in that the width of the second gate electrode is 0.1 μm or less. 5. a semiconductor substrate of a first conductivity type; source and drain regions of a second conductivity type that are of a conductivity type different from the first conductivity type formed at a predetermined interval on the surface of the semiconductor substrate; and the source In a semiconductor device having an insulated gate field effect transistor comprising a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween to form a channel between the drain regions, electrons traveling through the channel are A semiconductor device comprising means for controlling a quantized energy level. 6. The semiconductor device according to claim 5, wherein the quantized energy level is controlled by the second gate electrode electrically floating with an insulating film interposed therebetween. 7. The semiconductor device according to claim 5, wherein the width of the gate electrode is such that a channel formed by the gate electrode constitutes one-dimensional conduction of electrons. 8. The semiconductor device according to claim 5, 6 or 7,
A semiconductor device characterized in that the length of the portion of the channel whose energy level is controlled is 0.1 μm or less. 9. A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type different from the first conductivity type formed at a predetermined interval on the surface of the semiconductor substrate, and the source; 1. A semiconductor device having an insulated gate field effect transistor comprising a drain region and a channel formed between the channels, wherein a gate electrode is disposed in a portion of the channel with an insulating film interposed therebetween. 10. The semiconductor device according to claim 9, wherein the width of the channel is 0.1 μm or less. 11. The semiconductor device according to claim 9, wherein the width of the channel is such that the channel constitutes one-dimensional conduction of electrons. 12. The semiconductor device according to claim 9, 10 or 11, wherein the width of the gate electrode is 0.1 μm or less. 13. A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type different from the first conductivity type formed at a predetermined interval on the surface of the semiconductor substrate, and the source. , a first gate electrode provided on the semiconductor substrate between the drain regions via a gate insulating film, and a second gate electrode provided on a portion of the first gate electrode via an insulating film. The insulated gate field effect transistor has two input terminals each connected to the second gate electrode through a resistor, and an output terminal connected to one of the source and drain regions through the resistor. 1. A logic circuit comprising: a power terminal connected to the source region; and a ground terminal connected to the other of the source and drain regions. 14. A semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type different from the first conductivity type formed at a predetermined interval on the surface of the semiconductor substrate, and the source. , a gate electrode provided on the semiconductor substrate via a gate insulating film to form a channel between the drain regions, and means for controlling the quantized energy level of the energy of electrons traveling through the channel. an insulated gate field effect transistor having two input terminals each connected to the means for controlling the energy level via a resistor, an output terminal connected to one of the source and drain regions, and a resistor. 1. A logic circuit comprising: a power supply terminal connected to the source terminal via the ground terminal; and a ground terminal connected to the other of the source and drain regions. 15. A semiconductor substrate of a first conductivity type, a source/drain region of a second conductivity type different from the first conductivity type formed at a predetermined interval on the surface of the semiconductor substrate, and the source. , has an insulated gate field effect transistor consisting of a channel provided between a drain region and a gate electrode provided in a part of the channel with an insulating film interposed therebetween; connected 2
an output terminal connected to one of the source and drain regions, a power supply terminal connected via a resistor, and a ground terminal connected to the other of the source and drain regions. A logic circuit that