JP2539465B2 - Semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor device, and more particularly to a fine MIS type field effect transistor utilizing a quantum effect.

[Conventional technology]

In a conventional MIS field-effect transistor, the source / drain regions provided on a semiconductor substrate are connected by a semiconductor surface inversion layer formed by a single-connected gate electrode, and its conductivity is controlled by the potential applied to the gate electrode. It was something to control. In these transistors, the quantum interference effect of electrons is not considered. There are many examples of MIS type field effect transistors, but as an example in which the gate electrode is divided, there is JP-A-61-279176. However, there is no description about quantum interference effect. In addition,
Japanese Unexamined Patent Publication (Kokai) No. 61-18182 discloses a semiconductor element in which the conduction path of electrons between the input section and the output section is ring-shaped.
In the prior art described above, a current is modulated by applying a voltage to the control electrode provided on one side of the ring-shaped branch path and changing the phase of the electron wave of the one-sided conduction path, whereas the present invention is based on both branch paths. The difference is that the current is controlled by applying a magnetic field or an electric field to.

[Problems to be solved by the invention]

An object of the present invention is to realize new conduction characteristics by utilizing the quantum interference effect in a MIS type semiconductor device.

[Means for solving problems]

The above object is realized by forming the gate electrode of the MIS field effect transistor in a multi-connection shape and generating an electric field in the substrate.

[Action]

FIG. 1 is a top view of a transistor showing the feature of the present invention. The gate electrode 1 that connects the source region 2 and the drain region 3 provided on the surface of the p-type substrate has a ring-shaped portion in the central portion. The semiconductor surface inversion layer induced by this gate also becomes a region of multiple connections showing a ring shape. The electron current flowing out of the source region 2 is divided into a first path 7 and a second path 8 as shown in FIG.
It becomes one again and reaches the drain region 3.

If the length of the path of each electron is shorter than the scattering length Lφ that changes the phase of the electron, a quantum interference effect occurs at the portion where the electron waves merge. As shown in FIG. 3, this interference can be controlled by the magnetic flux penetrating the region surrounded by the two paths, and the phase shift φ _m due to the magnetic field is Is represented. Here, e is the electron charge, h is Planck's constant, B _z is the z-axis component of the magnetic flux density, and S is the area of the region surrounded by the two paths. On the other hand, a phase shift can be generated by providing an electric field E between the two paths as shown in FIG. Becomes Where E _y is the electric field in the y direction, and v _x is the traveling speed of the electron. The two n ⁺ impurity regions in FIG. 1 are provided to generate an electric field E _y in the p-type substrate, and both are given 0 or a positive potential to form a depletion layer in the p-type substrate. Form and generate an electric field E _y .

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

Example 1 FIG. 5 shows the manufacturing process of Example 1. Specific resistance 10Ω ・ cm
An element isolation region 12 is formed on the p-type silicon substrate 11 by the normal LOCOS method. Next, a 20 nm silicon oxide film 14 is formed by a dry oxidation method at 950 ° C. for 25 minutes. A resist is applied to a thickness of 1 μm, an opening is provided in a predetermined portion, that is, a source / drain region and two n ⁺ diffusion regions 13 for applying an electric field by photolithography, and arsenic ions are implanted at an acceleration voltage of 80 kV. . The implantation amount was 5 × 10 ¹⁵ cm ^-2 . Of course, these n ⁺ regions may be formed by using phosphorus ions.
The drive-in process in a nitrogen atmosphere at 950 ° C. for 20 minutes results in the state shown in FIG. 5 (b). The n ⁺ region 13 visible here is for applying an electric field. Next, 200 nm polycrystalline silicon15
And deposit phosphorus for 20 minutes at 875 ° C. After that, predetermined source and drain regions are connected by a photo-etching method and dry etching, and the polycrystalline silicon film is processed into a shape including a multiple connection portion. Then 400nm
A PSG (Phospho Silicate Glass) film or other silicon oxide film 16 is deposited by LPCVD to an inter-layer insulating film with a thickness of 1 to form a contact hole again by photoetching and dry etching, and aluminum wiring 17 is formed. , FIG. 5 (d) was obtained. As described above, a desired semiconductor device having a top view of FIG. 1 was obtained. The opening of the polycrystalline silicon gate electrode is 0.1 μm
× 0.1 μm and the line width is 0.1 μm.

The device obtained as a result showed the conductivity characteristics shown in FIG. One of the two n ⁺ regions for applying an electric field is grounded, and the other is called a second gate to apply a positive voltage. This causes the conductivity to oscillate with respect to the second gate voltage.

Although the p-type substrate is used in this embodiment, a p-channel MISFET using an n-type substrate can be realized if all polarities are changed. Further, even one of the two n ⁺ regions for applying an electric field can fulfill the function.

Example 2 A device isolation region 12, an n ⁺ impurity region 13 and a polycrystalline silicon gate 15 are formed by the same process as in Example 1. Then boron ion is implanted with an energy of 20 kV and an implant amount of 1
Strike with × 10 ¹² cm ^-2 . After that, when the aluminum electrode wiring 17 is applied again by the same steps as in Example 1, the structure shown in FIG. 7 is obtained.

According to the present embodiment, the threshold voltage of the portion where the polycrystalline silicon gate 15 is not present becomes high, and the occurrence of inversion can be suppressed. As a result, it is possible to prevent the inversion layer from becoming a single crystal. The same effect as the first embodiment can be obtained.

Third Embodiment A device isolation region 12, an n ⁺ impurity region 13 and a polycrystalline silicon gate 15 are formed by the same process as in the first or second embodiment.
To form. Then, the PSG film 26 having a thickness of 200 nm is deposited by the LPCVD method. Further, polycrystalline silicon 25 having a thickness of 200 nm is deposited, and phosphorus is deposited at 875 ° C. for 20 minutes. Second
The polycrystalline silicon film is processed by dry etching so as to cover the portion where the first polycrystalline silicon 15 is absent, and is used as the second gate electrode. Thereafter, as in Example 1, a PSG film is deposited, contact holes are opened, and aluminum electrode wiring is further provided to obtain a sectional structure as shown in FIG. Also,
A structural view seen from above is shown in FIG. 8 (b).

In this structure, by applying a voltage to the second polycrystalline silicon gate electrode, it is possible to effectively suppress the inversion of the portion without the first polycrystalline silicon gate.

Example 4. A 200 nm silicon oxide film is deposited on the surface of a p-type Si substrate by the LPCVD method (FIG. 9 (a)). Next, using a photo-etching method, the silicon oxide film is processed into a predetermined shape, and the Si substrate is dug down to 300 nm using this silicon oxide film as a mask.
Figure 9 (b) is obtained. After that, a silicon oxide film is deposited to a thickness of 300 nm by the LPCVD method to fill the groove. After applying a photoresist of 2 μm and flattening it, the silicon oxide film up to the surface of the substrate is removed by the edback method to obtain the structure of FIG. 9 (c). FIG. 9 (d) shows a top view of the same structure, where the region where the silicon oxide film is embedded can be seen. After removing the silicon oxide film remaining on the surface once
A gate oxide film of 20 nm is formed by a dry oxidation method at 950 ° C. for 25 minutes. A hole is formed in the resist where the n ⁺ impurity region is to be formed by photo-etching, and arsenic ions are implanted at an accelerating voltage of 80 kV by 5 × 10 ¹⁵ cm ^-2 , and then at 950 ° C. for 20 minutes in a nitrogen atmosphere. It is diffused in the drive-in process to obtain FIG. 9 (e). Further, a polycrystalline silicon film is deposited to a thickness of 200 nm by the CVD method, and phosphorus is deposited at 875 ° C. for 20 minutes. It is processed into a predetermined shape by dry etching to obtain FIG. 9 (f). In this embodiment, since the conductive channel is limited to the ring-shaped multiple connection region due to the buried element isolation, the shape of the polycrystalline silicon gate is as shown in the top view of FIG. 9 (g). , Need not be multiple concatenated. Considering the alignment accuracy of lithography, it is better to use a single connection. After that, as in Examples 1 to 3, a PSG film for an interlayer insulating film is deposited, contact holes are formed, and aluminum electrode wiring is provided to obtain a sectional structure as shown in FIG. 9 (h).

In this example, the same characteristics as in the above example were obtained.

Example 5 By the same steps as in Example 1, the element isolation region 12, the n ⁺ impurity region 13 and the polycrystalline silicon gate 15 are formed.
Then, using this polycrystalline silicon gate as a mask, p-type Si
The substrate was dug down to 100 nm (Fig. 10 (a)). Again as in Example 1, a PSG film for an interlayer insulating film was deposited to a thickness of 300 nm, contact holes were opened, and aluminum electrode wiring was provided to obtain FIG. 10 (b). In this example, the Si of the portion not covered by the gate electrode is
The reason is that the substrate was dug down and the conductive channel was limited to just below the gate electrode. In this embodiment, the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

According to the present invention, the conductivity of the MISFET can be periodically modulated by the second gate electrode (actually n ⁺ impurity region). This effect is purely quantum theory, has a period independent of temperature, etc., and can be effective for future LSIs and the like.

[Brief description of drawings]

FIG. 1 is a top view for explaining the features of the present invention, and FIGS.
FIG. 5 is a diagram for explaining the principle of the present invention, FIG. 5 is a cross-sectional view showing the manufacturing process of Example 1, FIG. 6 is a characteristic diagram of a device obtained by the present invention, and FIG. 7 is a cross-section of Example 2. Figure, 8th
FIG. 9 is a sectional view and a top view of the third embodiment, FIG. 9 is a diagram showing a process of the fourth embodiment, and FIG. 10 is a sectional view of the fifth embodiment. 1 ... Gate electrode, 2 ... Source region, 3 ... Drain region, 4,13,33 ... n ⁺ impurity region, 6 ... Inversion layer region,
5,17,36 …… Al electrode, 11 …… p type Si substrate, 12,32 …… Element isolation region, 14,16,26,31,35 …… Silicon oxide film, 1,15,2
1,25,34 …… Polycrystalline silicon gate electrode.

Claims (5)

(57) [Claims] 1. A source / drain electrode formed on a semiconductor substrate, a gate electrode having a ring shape for connecting between the source / drain electrodes to form the semiconductor substrate surface inversion layer, and a ring shape of the gate. And a means for controlling two paths on the surface of the semiconductor substrate formed by the above method. 2. The semiconductor device according to claim 1, wherein the semiconductor substrate is of a first conductivity type, and the source and drain electrodes are of a second conductivity type impurity region. apparatus. 3. The semiconductor device according to claim 1, wherein the means for controlling is a means for generating a magnetic flux penetrating an area surrounded by the two paths. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the means for controlling is a means for generating a magnetic field between the two paths. . 5. The semiconductor device according to claim 1, wherein the controlling means comprises at least one impurity region for generating an electric field in the semiconductor substrate. Semiconductor device.