JPH05343681A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05343681A JPH05343681A JP15100692A JP15100692A JPH05343681A JP H05343681 A JPH05343681 A JP H05343681A JP 15100692 A JP15100692 A JP 15100692A JP 15100692 A JP15100692 A JP 15100692A JP H05343681 A JPH05343681 A JP H05343681A
- Authority
- JP
- Japan
- Prior art keywords
- region
- channel
- substrate
- film
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 26
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000005684 electric field Effects 0.000 claims description 8
- 239000012212 insulator Substances 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 38
- 108091006146 Channels Proteins 0.000 description 37
- 239000010409 thin film Substances 0.000 description 9
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000002955 isolation Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体基板上にＭＯＳ
トランジスタなどの素子を形成する半導体装置に関す
る。BACKGROUND OF THE INVENTION The present invention relates to a MOS on a semiconductor substrate.
The present invention relates to a semiconductor device which forms an element such as a transistor.
【０００２】[0002]
【従来の技術】従来より、各種の半導体装置が提案され
ており、特にＭＯＳトランジスタを内蔵したものが多く
利用されている。そして、このような半導体装置におい
ては、その集積度を上昇させるために素子構造の微細化
が進んでいる。2. Description of the Related Art Conventionally, various types of semiconductor devices have been proposed, and in particular, those having a built-in MOS transistor are widely used. In such a semiconductor device, the element structure is being miniaturized in order to increase the degree of integration.
【０００３】ここで、通常の半導体装置は、平板状の半
導体基板（例えば、Ｓｉ基板）の所定の領域に複数のＭ
ＯＳトランジスタ形成している場合が多い。この場合に
は、ゲート領域を薄い絶縁層を介しゲート電極で覆った
状態でその両側の領域にイオンをドープして、ソース領
域、ドレイン領域を形成しＭＯＳトランジスタを半導体
基板の所定領域に形成している。そして、このような半
導体装置のＭＯＳトランジスタを微細化していくと、各
種の問題が生じる。すなわち、ドレイン付近の電界増加
に伴いドレイン空乏層がソース近傍の電位障壁近くまで
伸びパンチスルー電流が発生するなどの短チャネル効果
が発生したり、チャネル内における電界強度の増加に伴
いキャリアのエネルギーが増加し衝突電離により電子正
孔対が発生するホットキャリア効果が発生したり、さら
にチャネルの垂直方向の電界が大きくなりキャリアの移
動度が小さくなったり、隣接する素子との素子分離が十
分行えなくなる等の問題が発生する。従って、従来の半
導体装置では、そのゲート長をサブミクロン程度以下と
すると、十分な性能、信頼性を保持できないという問題
点があった。Here, in a typical semiconductor device, a plurality of M's are provided in a predetermined area of a flat semiconductor substrate (eg, Si substrate).
In many cases, OS transistors are formed. In this case, the gate region is covered with a gate electrode through a thin insulating layer, and regions on both sides of the gate region are doped with ions to form a source region and a drain region, and a MOS transistor is formed in a predetermined region of a semiconductor substrate. ing. When the MOS transistor of such a semiconductor device is miniaturized, various problems occur. That is, a short channel effect occurs such that the drain depletion layer extends near the potential barrier near the source and a punch through current occurs as the electric field near the drain increases, and the carrier energy increases as the electric field strength increases in the channel. A hot carrier effect is generated in which electron-hole pairs are generated due to collision ionization, the electric field in the vertical direction of the channel is increased, and the carrier mobility is reduced, and element isolation from an adjacent element cannot be performed sufficiently. Problems such as occur. Therefore, the conventional semiconductor device has a problem that sufficient performance and reliability cannot be maintained if the gate length is set to submicron or less.
【０００４】一方、これらの問題点を改善するものとし
て、ＳＯＩ（Ｓｉｌｉｃｏｎ ＯｎＩｎｓｕｌａｔｏ
ｒ）超薄膜トランジスタが提案されている。このＳＯＩ
超薄膜トランジスタは、半導体基板上に酸化絶縁膜を形
成し、この酸化絶縁膜上にソース、ゲート、ドレイン領
域を形成したものである。この超薄膜トランジスタによ
れば、絶縁膜上にトランジスタを形成するため、短チャ
ネル効果、ホットキャリア効果の発生を抑制できると共
に、チャネル全体に電圧を印加できるため垂直方向の電
界を小さくしてキャリア移動度を大きく維持でき、さら
に素子分離性に優れているという効果が得られる。On the other hand, as to improve these problems, SOI (S ilicon O n I nsulato
r) Ultra thin film transistors have been proposed. This SOI
The ultra-thin film transistor is formed by forming an oxide insulating film on a semiconductor substrate, and forming source, gate, and drain regions on the oxide insulating film. According to this super thin film transistor, since the transistor is formed on the insulating film, the occurrence of short channel effect and hot carrier effect can be suppressed, and since a voltage can be applied to the entire channel, the electric field in the vertical direction is reduced to reduce carrier mobility. It is possible to maintain a large value, and further, it is possible to obtain an effect that the element isolation property is excellent.
【０００５】しかし、この超薄膜トランジスタはその構
造上、絶縁膜上にトランジスタを形成するためのＳｉ基
板を形成することが必要である。ところが、絶縁膜（例
えば、ＳｉＯ2 ）にＳｉ単結晶層を形成することは技術
的に非常に難しい。特に、良質なＳｉエピタキシャル膜
を形成することは現在のところ不可能であり、好適な性
能を持つ超薄膜トランジスタを製造することは困難であ
った。However, because of the structure of this ultra-thin film transistor, it is necessary to form a Si substrate for forming the transistor on an insulating film. However, it is technically very difficult to form a Si single crystal layer on an insulating film (eg, SiO 2 ). In particular, it is impossible at present to form a high-quality Si epitaxial film, and it has been difficult to manufacture an ultrathin film transistor having suitable performance.
【０００６】そこで、本願発明者らは、超薄膜トランジ
スタに類似の効果を得られる半導体装置として、Ｓｉ基
板上に突出部を設け、この突出部内にソース、チャネ
ル、ドレイン領域を設ける縦型超薄膜トランジスタを特
願平４−１７１７６公報号で提案している。すなわち、
この縦型超薄膜トランジスタは、Ｓｉ基板上に突起部を
異方性エッチングによって形成している。そして、均一
な膜厚を有する絶縁体膜（いわゆる、ゲート酸化膜）を
介し配置されたゲート電極が、この突起部の中央部分に
カバーしており、ゲート電極の内側をチャネル領域と
し、その両側がドレイン領域、ソース領域とされてい
る。そして、ゲート電極の電位を変更することにより、
チャネル領域の状態を変化させ、ソース及びドレイン領
域間の導通を制御できる。一方、ドレイン領域、ソース
領域及びチャネル領域の下方に、基板の組成がそのまま
残る素子分離部を形成している。Therefore, the inventors of the present invention have proposed a vertical type ultra-thin film transistor in which a projecting portion is provided on a Si substrate and a source, a channel and a drain region are provided in the projecting portion, as a semiconductor device having an effect similar to that of the super thin film transistor. It is proposed in Japanese Patent Application No. 4-17176. That is,
In this vertical type super thin film transistor, a projection is formed on a Si substrate by anisotropic etching. A gate electrode, which is arranged with an insulating film (so-called gate oxide film) having a uniform thickness, covers the central portion of this protrusion, and the inside of the gate electrode serves as a channel region, and both sides thereof are formed. Are the drain region and the source region. Then, by changing the potential of the gate electrode,
The state of the channel region can be changed to control conduction between the source and drain regions. On the other hand, below the drain region, the source region and the channel region, an element isolation portion in which the composition of the substrate remains is formed.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上述の
ゲート電極に均一に絶縁体膜を形成した縦型超薄膜トラ
ンジスタにおいて、チャネル領域の上端部は、その上方
のゲート電圧のみならず、Ｓｉ突出部の側壁のゲート電
圧の影響も受けるため、電界が密になっている。従っ
て、Ｓｉ突出部上端部のチャネル部は、Ｓｉ突出部側壁
のチャネル部よりも低いゲート電圧でオンセットしてし
まい、トランジスタのスイッチング特性が悪化するとい
う問題点があった。However, in the vertical type super thin film transistor in which the insulating film is uniformly formed on the gate electrode, the upper end portion of the channel region is not limited to the gate voltage above it but also the Si protruding portion. The electric field is dense because it is also affected by the gate voltage on the side wall. Therefore, the channel portion at the upper end of the Si protruding portion is turned on at a gate voltage lower than that of the channel portion at the side wall of the Si protruding portion, which causes a problem that the switching characteristics of the transistor are deteriorated.
【０００８】本発明は、上記問題点を解決することを課
題としてなされたものであり、縦型超薄膜トランジスタ
とした際に、上端部のチャネル部の電界強度を改善し、
チャネル領域のチャネル部に流れる電流の方向を基板と
ほぼ平行にして、良好なトランジスタのスイッチング特
性が得られる半導体装置を提供することを目的とする。The present invention has been made to solve the above problems, and when a vertical type super thin film transistor is formed, the electric field strength of the channel portion at the upper end is improved,
It is an object of the present invention to provide a semiconductor device in which the direction of current flowing in the channel part of the channel region is made substantially parallel to the substrate and good switching characteristics of the transistor can be obtained.
【０００９】[0009]
【課題を解決するための手段】本発明に係る半導体装置
は、半導体基板上に素子領域を突出形成し、ここにソー
ス領域と、ドレイン領域と、該ソース領域及びドレイン
領域間にチャネル領域と、を設け、そのチャネル領域に
絶縁体膜を介して電界を印加するゲート電極を設けた電
界効果トランジスタを有する半導体装置であって、前記
チャネル領域の前記絶縁体膜は、チャネル領域の上端部
において、膜厚が他の側壁の膜厚より厚いことを特徴と
する。A semiconductor device according to the present invention comprises an element region projectingly formed on a semiconductor substrate, a source region, a drain region, and a channel region between the source region and the drain region. And a field effect transistor having a gate electrode for applying an electric field to the channel region via an insulator film, wherein the insulator film in the channel region is at the upper end of the channel region, It is characterized in that the film thickness is thicker than the film thickness of other side walls.
【００１０】[0010]
【作用】本発明に係る半導体装置において、チャネル領
域（Ｓｉ突出部）の上端部の絶縁体膜厚を側壁の膜厚よ
り厚くしたので、Ｓｉ突出部上端部のチャネル部におい
て、その上方のゲート電圧の影響が弱められる。In the semiconductor device according to the present invention, the film thickness of the insulator at the upper end of the channel region (Si protrusion) is made thicker than the film thickness of the side wall. The influence of voltage is weakened.
【００１１】[0011]
【実施例】以下、本発明に係る半導体装置について、図
面に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention will be described below with reference to the drawings.
【００１２】図１は、上述のようにして製造された半導
体装置の構成を説明するための斜視図である。FIG. 1 is a perspective view for explaining the structure of the semiconductor device manufactured as described above.
【００１３】ｐ型のＳｉの基板１０の上部には、突出部
２０が形成されている。そして、この突出部２０の両側
には、ｎ+ 型のドレイン領域２２、ｎ+ 型のソース領域
２４が形成されており、このドレイン領域２２、ソース
領域２４に挟まれた領域に基板１０と同じｐ型のチャネ
ル領域２６が形成されている。そして、これらドレイン
領域２２、ソース領域２４、チャネル領域２６はその下
端が突出部２０内に収まっており、突出部２０の下部に
は基板１０の一部である素子分離部２８が形成されてい
る。A protrusion 20 is formed on the p-type Si substrate 10. An n + type drain region 22 and an n + type source region 24 are formed on both sides of the protruding portion 20, and the region between the drain region 22 and the source region 24 is the same as the substrate 10. A p-type channel region 26 is formed. The lower ends of the drain region 22, the source region 24, and the channel region 26 are contained in the protruding portion 20, and an element isolation portion 28 that is a part of the substrate 10 is formed below the protruding portion 20. ..
【００１４】また、基板１０および突出部２０の表面は
すべてＳｉＯ2 で形成される酸化膜３０によって覆われ
ており、チャネル領域２６の表面にはゲート電極３２が
形成されている。このため、この酸化膜３０はゲート酸
化膜として機能する。また、ゲート電極３２は、外部と
の電気的接続のため、基板１０の所定の端部まで引き回
されている。The surfaces of the substrate 10 and the protrusions 20 are all covered with an oxide film 30 made of SiO 2 , and a gate electrode 32 is formed on the surface of the channel region 26. Therefore, this oxide film 30 functions as a gate oxide film. Further, the gate electrode 32 is routed to a predetermined end portion of the substrate 10 for electrical connection with the outside.
【００１５】更に、突出部２０の上端部で酸化膜３０の
下方には、異方性エッチングのための線上パターン用酸
化膜１２が残留している。従って、このゲート電極３２
の上端部の酸化膜は、側壁の酸化膜より厚くなってい
る。Further, the oxide film 12 for a line pattern for anisotropic etching remains below the oxide film 30 at the upper end of the protrusion 20. Therefore, this gate electrode 32
The oxide film on the upper end of the is thicker than the oxide film on the side wall.
【００１６】このような半導体装置では、突出部２０内
に１つのＭＯＳトランジスタが構成されている。従っ
て、ドレイン領域２２、ソース領域２４にそれぞれドレ
イン電極、ソース電極を接続すれば、ゲート電極３２へ
の電圧の印加によって、チャネル領域２６の電位を制御
しドレイン領域２２→ソース領域２４間の電流を制御す
ることができる。この例では、形成されているＭＯＳト
ランジスタがｎチャネルであるため、ゲート電極に正の
電圧を印加することによって、電流が流れる。In such a semiconductor device, one MOS transistor is formed in the protruding portion 20. Therefore, if a drain electrode and a source electrode are connected to the drain region 22 and the source region 24, respectively, the potential of the channel region 26 is controlled by applying a voltage to the gate electrode 32 to control the current between the drain region 22 and the source region 24. Can be controlled. In this example, since the formed MOS transistor is an n-channel, a current flows by applying a positive voltage to the gate electrode.
【００１７】特に、本実施例の装置によれば、突出部２
０の上端部で酸化膜３０の下方に、所定の膜厚の酸化膜
１２が設けられている。従ってこのゲート酸化膜は、こ
の部分の膜厚が側壁膜厚より厚くなっている。このた
め、チャネル領域２６の上端部のチャネル部において、
その上端部のゲート電圧の影響が弱められ、このチャネ
ル部の閾値電圧が従来より高くなって、他の部分に先駆
けてオンセットされることがない。Particularly, according to the apparatus of this embodiment, the protrusion 2
An oxide film 12 having a predetermined thickness is provided below the oxide film 30 at the upper end of 0. Therefore, in this gate oxide film, the film thickness at this portion is thicker than the sidewall film thickness. Therefore, in the channel portion at the upper end of the channel region 26,
The influence of the gate voltage at the upper end portion is weakened, the threshold voltage of the channel portion becomes higher than in the conventional case, and it is not turned on before the other portions.
【００１８】一方、前述の素子分離部２８は基板１０の
一部である。そこで、衝突電離によって発生する基板と
同極性の余剰キャリア（本例の場合、正孔）が基板１０
に排出されることになり、チャネル領域２６に溜まるこ
とがない。従って、余剰キャリアの蓄積に伴うキンク
（Ｋｉｎｋ）現象の発生がなく、また余剰の正孔による
疑似短チャネル効果の発生がない。また、消費電力によ
り発生した熱が基板１０に容易に拡散するため、チャネ
ル領域２６の加熱を防止することができる。On the other hand, the element isolation portion 28 described above is a part of the substrate 10. Therefore, excess carriers (holes in this example) having the same polarity as the substrate generated by impact ionization are generated in the substrate 10.
Will not be accumulated in the channel region 26. Therefore, a Kink phenomenon due to the accumulation of surplus carriers does not occur, and a pseudo short channel effect due to surplus holes does not occur. Further, since the heat generated by the power consumption is easily diffused to the substrate 10, it is possible to prevent the channel region 26 from being heated.
【００１９】さらに、トランジスタを縦型とし、チャネ
ル領域２６をゲート電極３２によって取り囲んでいるた
め、チャネル領域全体の電圧を所定の値に制御すること
ができ、動作性能を非常に高いものとすることができ
る。Further, since the transistor is of a vertical type and the channel region 26 is surrounded by the gate electrode 32, the voltage of the entire channel region can be controlled to a predetermined value, and the operating performance is extremely high. You can
【００２０】本実施例の半導体装置の製造方法につい
て、図２に基づいて説明する。まず、Ｓｉ単結晶からな
る基板１０表面上に、ＳｉＯ2 膜（またはＳｉＮ膜）１
２による線幅０．１μｍ程度の線状パターンを形成する
（Ｓ１）。この線状パターンの形成は、電子（ＥＢ）ビ
ーム描画露光装置および多層レジスト露光技術などを利
用した超微細パターニング技術によって行う。そして、
このＳｉＯ2 （またはＳｉＮ）線状パターンをマスクと
して、ＲＩＥ（Ｒｅａｃｔｉｖｅ Ｉｏｎ Ｅｔｃｈ
- ｉｎｇ）などによって基板１０に異方性エッチングを
施し、所定の凹部４０を形成して突出部２０を形成する
（Ｓ２）。次に、このマスクとして機能したＳｉＯ2 膜
１２を除去することなく、基板１０の全表面を熱酸化し
ＳｉＯ2 の酸化膜３０を形成する（Ｓ３）。そして、全
表面にポリシリコン層Ｐｏｌｙ−Ｓｉを形成した（Ｓ
４）後、通常のフォトリソグラフィにより、ゲート電極
３２を形成する（Ｓ５）。その後、イオン注入によりド
レイン領域２２、ソース領域２４を形成する（本実施例
では、例えばリンの注入によるｎ+ 領域の形成）。ここ
で、このイオン注入は、不純物の照射方向をマスク、電
圧印加などによって斜め方向のみに限定する斜入射イオ
ン注入装置によって行う（Ｓ６）。そして、ソース及び
ドレイン領域の酸化膜を除去したのち、必要に応じてア
ニール処理を行って各領域の結晶構造等を調整する。A method of manufacturing the semiconductor device of this embodiment will be described with reference to FIG. First, the SiO 2 film (or SiN film) 1 is formed on the surface of the substrate 10 made of Si single crystal.
A linear pattern having a line width of about 0.1 μm is formed by 2 (S1). The formation of this linear pattern is performed by an ultrafine patterning technique using an electron (EB) beam drawing exposure device and a multilayer resist exposure technique. And
The SiO 2 (or SiN) linear pattern as a mask, RIE (R eactive I on E tch
substrate 10 is anisotropically etched to form a predetermined recess 40 and form a protrusion 20 (S2). Next, without removing the SiO 2 film 12 functioning as the mask, the entire surface of the substrate 10 is thermally oxidized to form an SiO 2 oxide film 30 (S3). Then, a polysilicon layer Poly-Si was formed on the entire surface (S
4) After that, the gate electrode 32 is formed by normal photolithography (S5). After that, the drain region 22 and the source region 24 are formed by ion implantation (in the present embodiment, for example, phosphorus is implanted to form an n + region). Here, this ion implantation is performed by an oblique incidence ion implantation apparatus in which the irradiation direction of impurities is limited to only the oblique direction by masking, voltage application, etc. (S6). Then, after removing the oxide film in the source and drain regions, an annealing process is performed as necessary to adjust the crystal structure and the like of each region.
【００２１】[0021]
【発明の効果】以上説明したように、本発明に係る半導
体装置によれば、チャネル領域（Ｓｉ突出部）の上端部
の絶縁体膜厚をその側壁の膜厚より厚くしたので、Ｓｉ
突出部の上端部のチャネル部において、その上方のゲー
ト電圧の影響が弱められた。従って、Ｓｉ突出部上端の
チャネル部の閾値電圧が従来より高くなり、この部分が
他の部分に先駆けてオンセットされることがない。ま
た、チャネル領域のチャネル部に流れる電流の方向が、
基板とほぼ平行になる。As described above, according to the semiconductor device of the present invention, the insulator film thickness at the upper end of the channel region (Si protrusion) is made thicker than the film thickness at the side wall thereof.
In the channel portion at the upper end of the protrusion, the influence of the gate voltage above it was weakened. Therefore, the threshold voltage of the channel portion at the upper end of the Si protruding portion becomes higher than in the conventional case, and this portion will not be onset prior to other portions. In addition, the direction of the current flowing in the channel part of the channel region is
It is almost parallel to the substrate.
【００２２】更に、線上パターン用の酸化膜を除去しな
いので、工程が簡略化できる。Further, since the oxide film for the line pattern is not removed, the process can be simplified.
【図１】半導体装置の構成を示す斜視図である。FIG. 1 is a perspective view showing a configuration of a semiconductor device.
【図２】半導体装置の製造工程の説明図である。FIG. 2 is an explanatory diagram of a manufacturing process of a semiconductor device.
１０ 基板 １２ ＳｉＯ2 膜 ２０ 突出部 ２２ ドレイン領域 ２４ ソース領域 ２６ チャネル領域 ３０ 酸化膜 ３２ ゲート電極 ４０ 凹部10 Substrate 12 SiO 2 Film 20 Projection 22 Drain Region 24 Source Region 26 Channel Region 30 Oxide Film 32 Gate Electrode 40 Recess
Claims (1)
ここにソース領域と、ドレイン領域と、該ソース領域及
びドレイン領域間にチャネル領域と、を設け、そのチャ
ネル領域に絶縁体膜を介して電界を印加するゲート電極
を設けた電界効果トランジスタを有する半導体装置であ
って、 前記チャネル領域の前記絶縁体膜は、チャネル領域の上
端部において、膜厚が他の側壁の膜厚より厚いことを特
徴とする半導体装置。1. A device region is formed on a semiconductor substrate in a protruding manner,
A semiconductor having a field effect transistor in which a source region, a drain region, and a channel region are provided between the source region and the drain region, and a gate electrode for applying an electric field is provided in the channel region through an insulator film. A semiconductor device, wherein the insulator film in the channel region has a film thickness thicker than film thicknesses of other side walls at an upper end portion of the channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15100692A JPH05343681A (en) | 1992-06-11 | 1992-06-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15100692A JPH05343681A (en) | 1992-06-11 | 1992-06-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05343681A true JPH05343681A (en) | 1993-12-24 |
Family
ID=15509235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15100692A Pending JPH05343681A (en) | 1992-06-11 | 1992-06-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05343681A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198158B1 (en) * | 1998-05-08 | 2001-03-06 | Micron Technology, Inc. | Memory circuit including a semiconductor structure having more usable substrate area |
| DE10220923A1 (en) * | 2002-05-10 | 2003-11-27 | Infineon Technologies Ag | Non-volatile flash semiconductor memory and manufacturing process |
| WO2004023519A2 (en) * | 2002-09-05 | 2004-03-18 | Infineon Technologies Ag | High-density nrom-finfet |
| US7135742B1 (en) * | 2000-02-08 | 2006-11-14 | Fujitsu Limited | Insulated gate type semiconductor device and method for fabricating same |
| CN100433333C (en) * | 2002-12-20 | 2008-11-12 | 因芬尼昂技术股份公司 | Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement, and method for the production of a fin field effect transistor memory cell |
| EP2169715A2 (en) | 2002-10-18 | 2010-03-31 | Infineon Technologies AG | Integrated switching assembly with condenser and production method |
| US7884418B2 (en) | 2007-06-26 | 2011-02-08 | Elpida Memory, Inc. | Semiconductor device and transistor |
-
1992
- 1992-06-11 JP JP15100692A patent/JPH05343681A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6198158B1 (en) * | 1998-05-08 | 2001-03-06 | Micron Technology, Inc. | Memory circuit including a semiconductor structure having more usable substrate area |
| US6403430B1 (en) | 1998-05-08 | 2002-06-11 | Micron Technology, Inc. | Semiconductor structure having more usable substrate area and method for forming same |
| US6566206B2 (en) | 1998-05-08 | 2003-05-20 | Micron Technology, Inc. | Semiconductor structure having more usable substrate area and method for forming same |
| US7135742B1 (en) * | 2000-02-08 | 2006-11-14 | Fujitsu Limited | Insulated gate type semiconductor device and method for fabricating same |
| DE10220923B4 (en) * | 2002-05-10 | 2006-10-26 | Infineon Technologies Ag | Method for producing a non-volatile flash semiconductor memory |
| DE10220923A1 (en) * | 2002-05-10 | 2003-11-27 | Infineon Technologies Ag | Non-volatile flash semiconductor memory and manufacturing process |
| US7157768B2 (en) | 2002-05-10 | 2007-01-02 | Infineon Technologies Ag | Non-volatile flash semiconductor memory and fabrication method |
| WO2004023519A3 (en) * | 2002-09-05 | 2004-06-10 | Infineon Technologies Ag | High-density nrom-finfet |
| WO2004023519A2 (en) * | 2002-09-05 | 2004-03-18 | Infineon Technologies Ag | High-density nrom-finfet |
| EP2169715A2 (en) | 2002-10-18 | 2010-03-31 | Infineon Technologies AG | Integrated switching assembly with condenser and production method |
| EP2169715A3 (en) * | 2002-10-18 | 2013-07-10 | Infineon Technologies AG | Integrated switching assembly with condenser and production method |
| CN100433333C (en) * | 2002-12-20 | 2008-11-12 | 因芬尼昂技术股份公司 | Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement, and method for the production of a fin field effect transistor memory cell |
| US7884418B2 (en) | 2007-06-26 | 2011-02-08 | Elpida Memory, Inc. | Semiconductor device and transistor |
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