CA1060587A - Electrical circuit logic elements - Google Patents
Electrical circuit logic elementsInfo
- Publication number
- CA1060587A CA1060587A CA253,926A CA253926A CA1060587A CA 1060587 A CA1060587 A CA 1060587A CA 253926 A CA253926 A CA 253926A CA 1060587 A CA1060587 A CA 1060587A
- Authority
- CA
- Canada
- Prior art keywords
- schottky
- terminal
- schottky diode
- diodes
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000005468 ion implantation Methods 0.000 claims abstract description 6
- 239000004065 semiconductor Substances 0.000 claims description 14
- 230000000903 blocking effect Effects 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000001465 metallisation Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000003199 nucleic acid amplification method Methods 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/12—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using diode rectifiers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
- H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
- H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
- H10D84/613—Combinations of vertical BJTs and one or more of diodes, resistors or capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/65—Integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Bipolar Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A bipolar S3TL-gate (Small Swing Schottky Transistor Logic) is proposed, in which two Schottky diodes, mutually differing either in area, but with a low start voltage are employed using identical processing for metallization, and/or mutually differing doping levels of the silicon surface, preferably effected by means of ion implantation.
A bipolar S3TL-gate (Small Swing Schottky Transistor Logic) is proposed, in which two Schottky diodes, mutually differing either in area, but with a low start voltage are employed using identical processing for metallization, and/or mutually differing doping levels of the silicon surface, preferably effected by means of ion implantation.
Description
~060587 , The invention relates to electrical circuit logic elements, in particular a bipolar gate for LSI embodiment, in which there are at least two Schottky diodes which fulfill different functions in a semiconductor body.
A known, high-speed bipolar gate logic element for LSI circuits employs various Schottky-diodes, each connected to a base electrode of a common pnp-transistor serving as a current source, and a Schottky trans-istor being provided, as described in Electronics, December 1974 pages 36 and 38. The production of this so-called C3L,gate (C3L = Complementary , .
Constant Current Logic) is difficult, inasmuch as two mutually different .. . . . .
Schottky diode types must be formed by technological steps, together with i:
';; a pnp-transistor. The need for different types of Schottky dlode leads to the use of complex production processes in order to ensure a reasonable yield and fair compatibility. On the other hand the pnp-transistor which serves as a current source makes still higher demands on all the process ,,. ~ ,....
steps leading to this component, which results in a smaller yield being , obtainable. In addition the pnp-transistor necessitates an additional ~- capacitance, and in the case of poor amplification high base currents may ~, ':'.' ; flow which do not participate in any switch-over operation. Thus the ?
;i 20 presence of a pnp-transistor leads to a loss of switching time, and of power when operating.
.i . .
One object of the present invention is to provide a high-speed ; bipolar gate with a simple production process, high packing density, and ., , . ~.
good amplification.
~ According to the invention there is provided a semiconductor logic - element, comprising a bipolar transistor and at least two Schottky diodes, ~ the two Schottky diodes being produced side by side in regions of one type A,"' "~'' Of conductivity on the surface of a semiconductor crystal in such a fashion ~ that the two Schottky diodes show different threshold voltages, characterized ... .
."~.~. . ~
~ ~ -2-., .,,. ~
,, .
s .
- . ; . . i : ,. . , : :
in that the Schottky diodes show different dopings of the semiconductor -crystal beneath the Schottky contacts and in that the different dopings are produced by means of ion implantation and by forming a thin, highly doped layer which is thinner than the space-charge region at zero volts between a metal Schottky contact and the semiconductor crystal.
A logic element constructed in accordance with the invention is relatively simple to produce, and yet provides a good amplification, with high packing density and a short switching time.
Preferably said diodes have mutually different doping levels pro-duced by ion implantation. This causes a change in the threshold voltage -of the various Schottky diodes, as described for example in "Applied Phys.
Letters,~ Vol. 24, No. 8, 1974, pages 369 to 371. The ion implantation should produce a thin, highly doped layer having a thickness which is smaller than the space charge zone existing between the metal electrode and the semi-conductor body at a potential difference of zero volts. Doping with a greater penetration depth than the space charge zone would lead to high conduotion currents.
Advantageously, the Schottky diode metal electrodes consist of coatings of titanium on the semiconductor body. `
The invention facilitates the production of a logic element, in particular a bipolar gate for LSI circuits, which is simple to produce and exhibits a high-speed switching behaviour with a high packing density. The ~ ~ technologically differing Schottky diodes may be formed by Schottky diodes ¦~ which differ in area and have a low threshold voltage, using identical metallization technology. However, a change in the threshold voltage is preferably obtained by using differing doping levels of the semiconductor ~ body, preferably with the aid of ion implantation. In addition the pnp-¦~1 transistor required in the C3L_gate is replaced by a resistor, as a result of which the switching ."
1: :
.,.. - . . . ~ - - - ., , . :
1(~60587 behaviour is further improved.
The invention will now be described with reference to the draw-ings, in which:-Figure 1 is a circuit diagram illustrating a bipolar NAND-gate with two inputs;
Figure 2 is a circuit dia6ram of a bipolar gate with multiple outputs;
Figure 3 is a plan view of an exemplary construction of the part surrounded by a broken line in Figure 2; and Figure 4 is a cross-section on the line IV-IV shown in Figure 3.
In the embodiment shown in Figure 1, a first terminal of a first Schottky diode 2 is connected in one direction to a first input 1, to block when operating. A second input 3 is connected to a first input of a second Schottky diode 4 which is likewise poled in the blocking direction with respect to the input 3. The second terminal of the terminal of the first Schottky d$ode 2 is connected to one terminal of a resistor 5, to a first terminal of a third Schottky diode 6 that is poled in the opposite direction to the diodes 2 and 4, and to the base a transistor 7, and to the second ter-minal of the second Schottky diode 4. The other terminal of the resistor 5 carries a reference potential Ucc, which may be at earth. The second ter-minal of the third Schottky diode 6 is connected to the collector of the transistor 7 and to an output 8.
When operating, the inputs 1 and 3 carry an input voltage UE~ and there is a voltage drop UDL across each of the Schottky diodes 2 and 4, whereas there is a voltage drop UDc across the different Schottky diode 6. The emitter of the transistor 7 is maintained at a reference potential UEE which may be earth. An output voltage UA is presented to the output 8. The ga~e illustrated in Figure 1 fulfills two logic l~Q587 functions:
The resistor 5 together with the two Schottky diodes 2 and 4, form an AND-diode link. The transistor 7 and the Schottky diode 6 together form an inverter, with means for prevention of saturation.
In order to ensure a satisfactory function of a plurality of gates of this type (see Figure 2) in the case of large combinations of such logic circuits, the relationship between the diode voltages should satisfy the expression UDL<UDc. This can be achieved by means of different threshold value voltages, and/or different internal resistances for the Schottky diodes 2 and 4, compared with 6. This can be achieved by altering the diode surface area or the diode thresh-old value by means of differing doping levels. Preferably we have:-UBC>UDC>UDL
where UBc = base-collector threshold value of the transistor 7. -A voltage ~U = UDc = UDL, corresponds to the logic voltage range whereas Us = UB ~ UDc determines the degree of the saturation.
As the switching time is considerably impaired in the case of saturation of the transistor 7, it is preferable to adhere to a voltage difference Us. In addition it is necessary to adhere to a corresponding voltage range ~U to ensure that the gate is free from interference.
As will be shown in the following, Schottky diodes with a low threshold value are particularly advantageous.
For the values UBc = 0.7 V; Us = 0-3 Vj and ~U = 0.1 V, we DC UBc ~ Us = 4 V, and UDL = UD - ~U = 0 3 V
Thus the threshold value voltages of the Schottky diodes 2, 4 and 6 should if possible lie below 0.4 V. This can be achieved if the Schottky contacts consist of coatings of mutually differing area, formed on the semiconductor body, by titanium, and allowing for the ,i:: . - . - . :~ ,-~060587 current density in the components.
A bipolar gate with a transistor 7, possessing an emitter of length 8 ~m, two titanium-Schottky diodes 2 and 4 each having an area of 8 x 8 ~m, and a titanium-Schottky-diode 6 having an area of 16 x 16 ~m pro-duces a voltage range ~U = 140 mV, with a speed-power-product A = 0.27 pJ.
~ere the transit time of the gate amounts to approximately 0. 7 ns.
In the case of oxide insulation (see Figure 4), and an emitter size of approximately 4 x 8 ~m, a packing density of approximately 200 gates/mm can be achieved for gates each with three inputs.
Figure 2 illustrates the electric circuit of the bipolar gate construction represented in Figure 3. A Schottky diode 24 is connected in the blocking direction to an input 13. Three Schottky diodes 25, 26 and 27 are connected in parallel to respective outputs 35, 36 and 37 each diode being connected in the blocking direction to the preced-ing output 8, to form input Schottky diodes (corresponding to the Schottky diode 24) of separate succeeding gates. Schottky diodes 24, 25 and 26 are of mutually identical construction, whilst the Schottky diode 6 possesses a Schottky contact of different area.
Figure 3 is a plan view of the fundamental components of 20 that part of the circuit shown in Figure 2 that is surrounded by a broken line 38 and Figure 4 shows a cross-section on the line IV-IV
through Figure 3. A n conducting zone (buried layer) 41 is provided in a p-conducting semiconductor body 40. Zones 42 and 43, which are n conducting, lie on the zone 41. Also provided are p conducting zones 44 and 45 and a n conducting zone 46. Oxide layers 50 serve to insulate ad~acent components. The Schottky diode 27 consists of a titanium-Schottky contact 51 and the zone 43. The Schottky diode 6 consists of a Schottky contact 52 and the zone 42. The transistor _ 6 --. :, - , . ... , ~ .; . . , .. ~.: .: . .
1~)60587 7 has an emitter contact 53. The Schottky contact s 51 and 52 possess ' mutually different surfaces areasO
' :. " ' , ' , ' , :' : ,. ..... . .
A known, high-speed bipolar gate logic element for LSI circuits employs various Schottky-diodes, each connected to a base electrode of a common pnp-transistor serving as a current source, and a Schottky trans-istor being provided, as described in Electronics, December 1974 pages 36 and 38. The production of this so-called C3L,gate (C3L = Complementary , .
Constant Current Logic) is difficult, inasmuch as two mutually different .. . . . .
Schottky diode types must be formed by technological steps, together with i:
';; a pnp-transistor. The need for different types of Schottky dlode leads to the use of complex production processes in order to ensure a reasonable yield and fair compatibility. On the other hand the pnp-transistor which serves as a current source makes still higher demands on all the process ,,. ~ ,....
steps leading to this component, which results in a smaller yield being , obtainable. In addition the pnp-transistor necessitates an additional ~- capacitance, and in the case of poor amplification high base currents may ~, ':'.' ; flow which do not participate in any switch-over operation. Thus the ?
;i 20 presence of a pnp-transistor leads to a loss of switching time, and of power when operating.
.i . .
One object of the present invention is to provide a high-speed ; bipolar gate with a simple production process, high packing density, and ., , . ~.
good amplification.
~ According to the invention there is provided a semiconductor logic - element, comprising a bipolar transistor and at least two Schottky diodes, ~ the two Schottky diodes being produced side by side in regions of one type A,"' "~'' Of conductivity on the surface of a semiconductor crystal in such a fashion ~ that the two Schottky diodes show different threshold voltages, characterized ... .
."~.~. . ~
~ ~ -2-., .,,. ~
,, .
s .
- . ; . . i : ,. . , : :
in that the Schottky diodes show different dopings of the semiconductor -crystal beneath the Schottky contacts and in that the different dopings are produced by means of ion implantation and by forming a thin, highly doped layer which is thinner than the space-charge region at zero volts between a metal Schottky contact and the semiconductor crystal.
A logic element constructed in accordance with the invention is relatively simple to produce, and yet provides a good amplification, with high packing density and a short switching time.
Preferably said diodes have mutually different doping levels pro-duced by ion implantation. This causes a change in the threshold voltage -of the various Schottky diodes, as described for example in "Applied Phys.
Letters,~ Vol. 24, No. 8, 1974, pages 369 to 371. The ion implantation should produce a thin, highly doped layer having a thickness which is smaller than the space charge zone existing between the metal electrode and the semi-conductor body at a potential difference of zero volts. Doping with a greater penetration depth than the space charge zone would lead to high conduotion currents.
Advantageously, the Schottky diode metal electrodes consist of coatings of titanium on the semiconductor body. `
The invention facilitates the production of a logic element, in particular a bipolar gate for LSI circuits, which is simple to produce and exhibits a high-speed switching behaviour with a high packing density. The ~ ~ technologically differing Schottky diodes may be formed by Schottky diodes ¦~ which differ in area and have a low threshold voltage, using identical metallization technology. However, a change in the threshold voltage is preferably obtained by using differing doping levels of the semiconductor ~ body, preferably with the aid of ion implantation. In addition the pnp-¦~1 transistor required in the C3L_gate is replaced by a resistor, as a result of which the switching ."
1: :
.,.. - . . . ~ - - - ., , . :
1(~60587 behaviour is further improved.
The invention will now be described with reference to the draw-ings, in which:-Figure 1 is a circuit diagram illustrating a bipolar NAND-gate with two inputs;
Figure 2 is a circuit dia6ram of a bipolar gate with multiple outputs;
Figure 3 is a plan view of an exemplary construction of the part surrounded by a broken line in Figure 2; and Figure 4 is a cross-section on the line IV-IV shown in Figure 3.
In the embodiment shown in Figure 1, a first terminal of a first Schottky diode 2 is connected in one direction to a first input 1, to block when operating. A second input 3 is connected to a first input of a second Schottky diode 4 which is likewise poled in the blocking direction with respect to the input 3. The second terminal of the terminal of the first Schottky d$ode 2 is connected to one terminal of a resistor 5, to a first terminal of a third Schottky diode 6 that is poled in the opposite direction to the diodes 2 and 4, and to the base a transistor 7, and to the second ter-minal of the second Schottky diode 4. The other terminal of the resistor 5 carries a reference potential Ucc, which may be at earth. The second ter-minal of the third Schottky diode 6 is connected to the collector of the transistor 7 and to an output 8.
When operating, the inputs 1 and 3 carry an input voltage UE~ and there is a voltage drop UDL across each of the Schottky diodes 2 and 4, whereas there is a voltage drop UDc across the different Schottky diode 6. The emitter of the transistor 7 is maintained at a reference potential UEE which may be earth. An output voltage UA is presented to the output 8. The ga~e illustrated in Figure 1 fulfills two logic l~Q587 functions:
The resistor 5 together with the two Schottky diodes 2 and 4, form an AND-diode link. The transistor 7 and the Schottky diode 6 together form an inverter, with means for prevention of saturation.
In order to ensure a satisfactory function of a plurality of gates of this type (see Figure 2) in the case of large combinations of such logic circuits, the relationship between the diode voltages should satisfy the expression UDL<UDc. This can be achieved by means of different threshold value voltages, and/or different internal resistances for the Schottky diodes 2 and 4, compared with 6. This can be achieved by altering the diode surface area or the diode thresh-old value by means of differing doping levels. Preferably we have:-UBC>UDC>UDL
where UBc = base-collector threshold value of the transistor 7. -A voltage ~U = UDc = UDL, corresponds to the logic voltage range whereas Us = UB ~ UDc determines the degree of the saturation.
As the switching time is considerably impaired in the case of saturation of the transistor 7, it is preferable to adhere to a voltage difference Us. In addition it is necessary to adhere to a corresponding voltage range ~U to ensure that the gate is free from interference.
As will be shown in the following, Schottky diodes with a low threshold value are particularly advantageous.
For the values UBc = 0.7 V; Us = 0-3 Vj and ~U = 0.1 V, we DC UBc ~ Us = 4 V, and UDL = UD - ~U = 0 3 V
Thus the threshold value voltages of the Schottky diodes 2, 4 and 6 should if possible lie below 0.4 V. This can be achieved if the Schottky contacts consist of coatings of mutually differing area, formed on the semiconductor body, by titanium, and allowing for the ,i:: . - . - . :~ ,-~060587 current density in the components.
A bipolar gate with a transistor 7, possessing an emitter of length 8 ~m, two titanium-Schottky diodes 2 and 4 each having an area of 8 x 8 ~m, and a titanium-Schottky-diode 6 having an area of 16 x 16 ~m pro-duces a voltage range ~U = 140 mV, with a speed-power-product A = 0.27 pJ.
~ere the transit time of the gate amounts to approximately 0. 7 ns.
In the case of oxide insulation (see Figure 4), and an emitter size of approximately 4 x 8 ~m, a packing density of approximately 200 gates/mm can be achieved for gates each with three inputs.
Figure 2 illustrates the electric circuit of the bipolar gate construction represented in Figure 3. A Schottky diode 24 is connected in the blocking direction to an input 13. Three Schottky diodes 25, 26 and 27 are connected in parallel to respective outputs 35, 36 and 37 each diode being connected in the blocking direction to the preced-ing output 8, to form input Schottky diodes (corresponding to the Schottky diode 24) of separate succeeding gates. Schottky diodes 24, 25 and 26 are of mutually identical construction, whilst the Schottky diode 6 possesses a Schottky contact of different area.
Figure 3 is a plan view of the fundamental components of 20 that part of the circuit shown in Figure 2 that is surrounded by a broken line 38 and Figure 4 shows a cross-section on the line IV-IV
through Figure 3. A n conducting zone (buried layer) 41 is provided in a p-conducting semiconductor body 40. Zones 42 and 43, which are n conducting, lie on the zone 41. Also provided are p conducting zones 44 and 45 and a n conducting zone 46. Oxide layers 50 serve to insulate ad~acent components. The Schottky diode 27 consists of a titanium-Schottky contact 51 and the zone 43. The Schottky diode 6 consists of a Schottky contact 52 and the zone 42. The transistor _ 6 --. :, - , . ... , ~ .; . . , .. ~.: .: . .
1~)60587 7 has an emitter contact 53. The Schottky contact s 51 and 52 possess ' mutually different surfaces areasO
' :. " ' , ' , ' , :' : ,. ..... . .
Claims (3)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A semiconductor logic element, comprising a bipolar transistor and at least two Schottky diodes, the two Schottky diodes being produced side by side in regions of one type of conductivity on the surface of a semiconductor crystal in such a fashion that the two Schottky diodes show different threshold voltages, characterized in that the Schottky diodes show different dopings of the semiconductor crystal beneath the Schottky contacts and in that the different dopings are produced by means of ion implantation and by forming a thin, highly doped layer which is thinner than the space-charge region at zero volts between a metal Schottky contact and the semiconductor crystal.
2. A device according to claim 1, characterized in that at a first input (1) a first Schottky diode (2) is disposed in blocking direction of a first terminal, in that at a second input (3) a second Schottky diode (4) is disposed in blocking direction of a first terminal, in that the second terminal of the first and of the second Schottky diode (2 or 4) is connected with a first terminal of a resistor (5), with a terminal of a third Schottky diode (6) and with the base of a bipolar transistor (7), in that the second terminal of the resistor (5) is placed on a reference potential (Ucc), in that the second terminal of the third Schottky diode (6) is connected with an output (8) as well as with the collector of the transistor (7) and in that the first and the second Schottky diodes (2 or 4) are doped differently beneath the Schottky contact than the third Schottky diode.
3. A device according to claim 1, characterized in that at one input (13) a first Schottky diode (24) is disposed in blocking direction of a first terminal, in that a second terminal of the first Schottky diode (24) is connected with the collector of the bipolar transistor (7) through a resistor (5) at the reference potential (Ucc) as well as through a Schottky diode (6) poled in the direction of flow, in that furthermore this terminal of the first Schottky diode (24) is disposed directly at the base of the bipolar transistor (7), in that the emitter of the bipolar transistor (7) is placed on the reference potential (Ucc) and its collector through an output (8) on a plurality of Schottky diodes (25, 26, 27) which are poled in the direction of flow and in that finally by means of different doping beneath the Schottky contacts the Schottky diode (6) is provided with a threshold voltage different from that of the remaining Schottky diodes.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE2524579A DE2524579C3 (en) | 1975-06-03 | 1975-06-03 | Semiconductor logic element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1060587A true CA1060587A (en) | 1979-08-14 |
Family
ID=5948131
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA253,926A Expired CA1060587A (en) | 1975-06-03 | 1976-06-02 | Electrical circuit logic elements |
Country Status (7)
| Country | Link |
|---|---|
| AT (1) | AT336930B (en) |
| CA (1) | CA1060587A (en) |
| CH (1) | CH610160A5 (en) |
| DE (1) | DE2524579C3 (en) |
| FR (1) | FR2313820A1 (en) |
| GB (1) | GB1551276A (en) |
| IT (1) | IT1079512B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4156246A (en) * | 1977-05-25 | 1979-05-22 | Bell Telephone Laboratories, Incorporated | Combined ohmic and Schottky output transistors for logic circuit |
| US4347585A (en) * | 1980-06-09 | 1982-08-31 | International Business Machines Corporation | Reproduce only storage matrix |
| US4415817A (en) * | 1981-10-08 | 1983-11-15 | Signetics Corporation | Bipolar logic gate including circuitry to prevent turn-off and deep saturation of pull-down transistor |
| NL8300843A (en) * | 1983-03-09 | 1984-10-01 | Philips Nv | INTEGRATED LOGIC CIRCUIT. |
-
1975
- 1975-06-03 DE DE2524579A patent/DE2524579C3/en not_active Expired
- 1975-08-08 AT AT618375A patent/AT336930B/en not_active IP Right Cessation
-
1976
- 1976-04-12 CH CH461076A patent/CH610160A5/en not_active IP Right Cessation
- 1976-05-11 GB GB19306/76A patent/GB1551276A/en not_active Expired
- 1976-05-26 IT IT23666/76A patent/IT1079512B/en active
- 1976-05-28 FR FR7616222A patent/FR2313820A1/en active Granted
- 1976-06-02 CA CA253,926A patent/CA1060587A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2524579A1 (en) | 1976-12-23 |
| CH610160A5 (en) | 1979-03-30 |
| GB1551276A (en) | 1979-08-30 |
| FR2313820B1 (en) | 1982-09-03 |
| DE2524579B2 (en) | 1980-03-27 |
| IT1079512B (en) | 1985-05-13 |
| FR2313820A1 (en) | 1976-12-31 |
| AT336930B (en) | 1977-06-10 |
| ATA618375A (en) | 1976-09-15 |
| DE2524579C3 (en) | 1980-11-27 |
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