JPH0291975A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0291975A JPH0291975A JP63242281A JP24228188A JPH0291975A JP H0291975 A JPH0291975 A JP H0291975A JP 63242281 A JP63242281 A JP 63242281A JP 24228188 A JP24228188 A JP 24228188A JP H0291975 A JPH0291975 A JP H0291975A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- voltage
- type
- threshold voltage
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims description 22
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 230000007423 decrease Effects 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 2
- 230000002195 synergetic effect Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 11
- 230000005669 field effect Effects 0.000 description 11
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 5
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005036 potential barrier Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電力用の半導体装置に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a power semiconductor device.
従来、半導体整流装置としてはｐｎダイオード。 Conventionally, pn diodes have been used as semiconductor rectifiers.
ｐＩｎダイオードあるいはショットキーダイオード等が
用いられてきた。これらの素子は半導体のホモ接合ある
いは金属−半導体接合によって生じる電位障壁の整流作
用を利用している。第３図に典型的々従来のダイオード
の電流−電圧特性を示す。A pIn diode, a Schottky diode, etc. have been used. These devices utilize the rectifying effect of a potential barrier created by a semiconductor homojunction or a metal-semiconductor junction. FIG. 3 shows the current-voltage characteristics of a typical conventional diode.
同図のように、これらのダイオードの順方向特性２１で
は、電位障壁の拡散電位に対応するオフセット電圧を生
じる。このオフセット電圧は、ｐｎダイオードで０．６
ｖ程度、ショットキーダイオードで０．５ｖ程度である
。したがって、これらの素子を半導体整流素子として用
いた場合、オフセットがない場合に比べて、出力電流と
順方向電圧との積で与えられる順方向損失が大きいとい
う欠点を有している。As shown in the figure, the forward characteristics 21 of these diodes produce an offset voltage corresponding to the diffusion potential of the potential barrier. This offset voltage is 0.6 with a pn diode.
For a Schottky diode, it is about 0.5V. Therefore, when these elements are used as semiconductor rectifying elements, they have the disadvantage that the forward loss given by the product of the output current and the forward voltage is larger than when there is no offset.
また、従来、順方向電圧の低減を目的として、絶縁ゲー
ト型電界効果トランジスタあるいはバイポーラトランジ
スタを半導体整流素子として用いることが試みられてい
る。これらの素子では、ｐｎダイオードやｐｌｎダイオ
ード、ショットキーダイオードとは異な）、第３図の特
性２２に示すように電流をＯｖから流すことが可能であ
シ、順方向電圧を低くでき、順方向損失低減が可能であ
る。Furthermore, attempts have been made to use insulated gate field effect transistors or bipolar transistors as semiconductor rectifiers for the purpose of reducing forward voltage. In these devices, as shown in characteristic 22 in Figure 3, it is possible to flow current from Ov (unlike pn diodes, pln diodes, and Schottky diodes), and the forward voltage can be lowered. Loss can be reduced.
しかしながら、上述した従来の絶縁ゲート型電界効果ト
ランジスタあるいはバイポーラトランジスタなどの素子
は、ｐｎダイオード等とは異なシ３端子素子であるため
、整流素子として動作させる場合、制御端子に適切な制
御信号を加える必要がある。このため、（１）整流回路
が複雑化する、（Ｈ）制御信号の適切な設定が困難であ
る、といった欠点を有していた。However, since the conventional insulated gate field effect transistor or bipolar transistor described above is a three-terminal device unlike a pn diode, etc., when operating it as a rectifier, an appropriate control signal is applied to the control terminal. There is a need. For this reason, it has the following disadvantages: (1) the rectifier circuit becomes complicated; and (H) it is difficult to appropriately set the control signal.
本発明は以上の点に鑑みてなされたもので、その目的は
、順方向電圧が小さく、かつ順方向損失が小さい２端子
の半導体整流装置を提供することにある。The present invention has been made in view of the above points, and an object thereof is to provide a two-terminal semiconductor rectifier with low forward voltage and low forward loss.
上記の目的を達成する丸め、本発明の半導体装置は、第
１の導電型の半導体基板の第１の主面側に形成され次第
２の導電型を有するチャネル形成領域と、前記チャネル
形成領域内に形成された第１の導電型を有するドレイン
領域と、前記ドレイン領域内において前記第１の主面側
から半導体基板に達するように形成された溝と、前記溝
内に形成されたゲート絶縁膜およびゲート電極と、前記
半導体基板の第２の主面側に形成されたソース電極とか
ら構成される構造の絶縁ゲート型電界効果トランジスタ
から成シ、前記溝内に形成された前記ゲート絶縁膜の一
部が除去されて前記ゲート電極と前記半導体基板との間
でショットキー接合部を設け、さらに前記チャネル形成
領域と前記ドレイン領域と前記ゲート電極とを互いに電
気的に接続する電極を設けたものである。To achieve the above object, the semiconductor device of the present invention includes a channel forming region having a second conductivity type, which is formed on a first main surface side of a semiconductor substrate having a first conductivity type; a drain region having a first conductivity type formed in the drain region, a groove formed in the drain region so as to reach the semiconductor substrate from the first main surface side, and a gate insulating film formed in the groove. and an insulated gate field effect transistor having a structure including a gate electrode and a source electrode formed on the second main surface side of the semiconductor substrate, and the gate insulating film formed in the groove. A part is removed to provide a Schottky junction between the gate electrode and the semiconductor substrate, and an electrode is further provided to electrically connect the channel forming region, the drain region, and the gate electrode to each other. It is.
したがって、本発明においては、Ｏｖから電流が流れ始
める絶縁ゲート型電界効果トランジスタを整流素子とし
て使用する場合において制御端子を独立の端子とせず、
２端子素子として動作させ）さらにショットキーダイオ
ードを絶縁ゲート型電界効果トランジスタと並列に形成
することにより、従来の３端子整流素子の低い順方向電
圧を２端子で実現することができる。Therefore, in the present invention, when using an insulated gate field effect transistor from which current begins to flow from Ov as a rectifier, the control terminal is not an independent terminal;
Furthermore, by forming a Schottky diode in parallel with an insulated gate field effect transistor (operating as a two-terminal device), the low forward voltage of a conventional three-terminal rectifying device can be realized with two terminals.
以下、本発明を図面に示す実施例に基づいて説明する。 Hereinafter, the present invention will be explained based on embodiments shown in the drawings.
第１図は本発明による一実施例の半導体装置の構造を示
す断面図である。同図において、１は低抵抗のｈ型半導
体基板、２はこの基板１上に形成されたｎｆＪｌエピタ
キシャル半導体層、３はこの半導体層２上に形成された
ｐ型領域、４はこのｐ型領域３内に形成された低抵抗の
ａ型ドレイン領域である。また、５は前記ドレイン領域
４内においてその主面側からエピタキシャル半導体層２
つまシ半導体基板に達するように形成された矩形の溝１
０内に施されたゲート絶縁膜、６は前記溝１０内に形成
されたゲート絶縁ａ５の一部が除去されてその半導体層
２とショットキー接合を形成するべき施されたゲート電
極、Ｔは前記各ｐ型領域３とドレイン領域４とゲート電
極６とを互いに電気的に接続するためにその主面上に形
成されたアノード電極、８は半導体基板１の他の主面側
に形成されたカソード電極である。FIG. 1 is a sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. In the figure, 1 is a low resistance h-type semiconductor substrate, 2 is an nfJl epitaxial semiconductor layer formed on this substrate 1, 3 is a p-type region formed on this semiconductor layer 2, and 4 is this p-type region. A low resistance a-type drain region formed within the 3. Further, 5 is an epitaxial semiconductor layer 2 in the drain region 4 from its main surface side.
Rectangular groove 1 formed to reach the semiconductor substrate
0 is a gate insulating film formed in the trench 10, 6 is a gate electrode formed to form a Schottky junction with the semiconductor layer 2 after a part of the gate insulating layer a5 formed in the groove 10 is removed, and T is a gate electrode formed in the groove 10. An anode electrode 8 formed on the main surface of each p-type region 3, drain region 4, and gate electrode 6 to electrically connect them to each other is formed on the other main surface side of the semiconductor substrate 1. It is a cathode electrode.
すなわち、この実施例の半導体装置は、低抵抗のｎ型半
導体基板１上にｎ型エピタキシャル半導体層２を形成し
、その主面側にｐ型領域３をチャネル形成領域として形
成するとともに、このｐ型領域３内に低抵抗のｎ型ドレ
イン領域４を形成する。そして、該ドレイン領域４内に
おいてその主面側からエピタキシャル半導体層２に達す
る溝１０を形成して、この溝１０内にゲート絶縁膜５．
ゲート電極６を順次形成して成る構造の溝型二重拡散絶
縁ゲート型電界効果トランジスタから構成し、前記溝１
０内に形成されたゲート絶縁膜５の一部を除去してその
ゲート電極６と半導体層２との間でショットキー接合部
を設ける。さらに、前記ｐ型領域３とドレイン領域４と
ゲート電極６とを接続して７ノード電極７とし、半導体
基板１の他の主面側に形成したソース電極をカソード電
極８としたものである。That is, in the semiconductor device of this embodiment, an n-type epitaxial semiconductor layer 2 is formed on a low-resistance n-type semiconductor substrate 1, and a p-type region 3 is formed as a channel formation region on the main surface side of the layer. A low resistance n-type drain region 4 is formed within the type region 3. A trench 10 reaching the epitaxial semiconductor layer 2 from the main surface side of the drain region 4 is formed in the drain region 4, and a gate insulating film 5.
The trench type double diffused insulated gate field effect transistor has a structure in which gate electrodes 6 are successively formed.
A portion of the gate insulating film 5 formed within the gate electrode 6 is removed to provide a Schottky junction between the gate electrode 6 and the semiconductor layer 2. Furthermore, the p-type region 3, drain region 4, and gate electrode 6 are connected to form a seven-node electrode 7, and the source electrode formed on the other main surface side of the semiconductor substrate 1 is used as a cathode electrode 8.
次に動作を説明すゐ。上記実施例の構造において、まず
絶縁ゲート型電界効果トランジスタのしきい値電圧がＯ
ｖ程度となるように％ ｐ型領域３の不純物濃度、ゲー
ト絶縁膜５の膜厚等を設定し、しきい値電圧ｖｔｈ、ｎ
型エピタキシャル半導体層２とゲート電極６で形成され
るショットキー接合の接合電圧ｖＭ、ｎ型エピタキシャ
ル半導体層２とｐ型領域３で形成されるｐｎ接合の拡散
電圧ｖｂｌとの間ＫＮ Ｏ≦ｖｔｈ ＜ ｖ、、 ＜
Ｖｂｉという関係が成シ立つようＫする。Next, I will explain the operation. In the structure of the above embodiment, first, the threshold voltage of the insulated gate field effect transistor is O
The impurity concentration of the p-type region 3, the film thickness of the gate insulating film 5, etc. are set so that the threshold voltage vth, n
KN O≦vth< v,, <
K so that the relationship Vbi is established.
このとき、カソード電極８に対してしきい値電圧以上の
電圧をアノード電極７に印加すると、ｐ型領域３のゲー
ト絶縁膜５の下の表面にｎ型チャネル９が形成され、ア
ノード電極７→ｎ型ドレイン領域４→ｎ型チヤネル９→
ｎｆｉエピタキシヤル半導体層２→ｎ型半導体基板１→
カソード電極８という電流経路が形成され、チャネル電
流が流れる。この際、ｐ型領域３はアノード電位と等し
くカソード電極８に対して正の電位であυ、これは絶縁
ゲート型電界効果トランジスタの基板を正にバイアスす
ることに相当するので絶縁ゲート型電界効果トランジス
タのしきい値電圧は低下する。At this time, when a voltage higher than the threshold voltage of the cathode electrode 8 is applied to the anode electrode 7, an n-type channel 9 is formed on the surface of the p-type region 3 under the gate insulating film 5, and the anode electrode 7→ n-type drain region 4→n-type channel 9→
nfi epitaxial semiconductor layer 2 → n-type semiconductor substrate 1 →
A current path called cathode electrode 8 is formed, and a channel current flows. At this time, the p-type region 3 is at a positive potential υ with respect to the cathode electrode 8, which is equal to the anode potential, and this corresponds to positively biasing the substrate of the insulated gate field effect transistor, so the insulated gate field effect transistor The threshold voltage of the transistor decreases.
したがって、アノード電極７に印加される電圧を正方向
に大きくしていくと、ゲート電極６の電位増加とｐ型領
域３のバイアス効果によるしきい値電圧の低下の相乗効
果によって電流は大幅に増加する。すなわち、電流は電
圧Ｏｖから流れ始め、しかも大幅な増加を示すので、頭
方向電圧は小さくなる。Therefore, when the voltage applied to the anode electrode 7 is increased in the positive direction, the current increases significantly due to the synergistic effect of the increase in the potential of the gate electrode 6 and the decrease in the threshold voltage due to the bias effect of the p-type region 3. do. That is, the current starts flowing from the voltage Ov and shows a significant increase, so the head voltage becomes small.
つぎに、カソード電極８に対してｎ型エピタキシャル半
導体層２とゲート電極６によって形成されるショットキ
ー接合の接合電圧以上の電圧をアノード電極７１Ｃ印加
すると、ｐ型領域のゲート絶縁膜５の下の表面Ｋｎ型チ
ャネル９が形成され、７ノ一ド電極７→ｎ型ドレイン領
域４→ｎ型チヤネル９→ｎ型エピタキシヤル半導体層２
→ｎ型半導体基板１→カソード電極８という電流経路が
形成され、チャネル電流が流れるとともに、アノード電
極１→ケート電極６→ｎ型エピタキシヤル半導体層２→
ｎ型半導体基板１→カソード電極８という経路でショッ
トキーダイオード電流が流れる。Next, when a voltage higher than the junction voltage of the Schottky junction formed by the n-type epitaxial semiconductor layer 2 and the gate electrode 6 is applied to the anode electrode 71C to the cathode electrode 8, the voltage below the gate insulating film 5 in the p-type region is A surface Kn-type channel 9 is formed, and 7 node electrode 7 → n-type drain region 4 → n-type channel 9 → n-type epitaxial semiconductor layer 2
A current path is formed → n-type semiconductor substrate 1 → cathode electrode 8, and a channel current flows, and the anode electrode 1 → cathode electrode 6 → n-type epitaxial semiconductor layer 2 →
A Schottky diode current flows through the path from the n-type semiconductor substrate 1 to the cathode electrode 8.
さらに、カソード電極８に対してｎ型エピタキシャル半
導体層２とｐ型領域３で形成されるｐｎ接合の拡散電圧
以上の電圧をアノードを極７に印加すると、ｐ型領域３
のゲート絶縁膜５の下の表面Ｋｎ型チャネル９が形成さ
れ、アノード電極７→ｎ型ドレイン領域４→ｎ型チヤネ
ル９→ｎ型エピタキシヤル半導体層２→ｎ型半導体基板
１→カソード電極８という電流経路が形成され、チャネ
ル電流が、アノード電極７→ゲート電極６→ｎ型エピタ
キシヤル半導体層２→ｎ型半導体基板１→カンード電極
８という経路でショットキーダイオード電流が流れると
ともに、アノード電極７−＋ ｐ型領域３→ｎ型エピタ
キシャル半導体層２→ｎ型半導体基板１→カンード電極
８という経路でダイオード電流が流れる。Furthermore, when a voltage higher than the diffusion voltage of the pn junction formed by the n-type epitaxial semiconductor layer 2 and the p-type region 3 is applied to the anode electrode 7, the p-type region 3
A Kn-type channel 9 is formed on the surface under the gate insulating film 5 of the anode electrode 7 → n-type drain region 4 → n-type channel 9 → n-type epitaxial semiconductor layer 2 → n-type semiconductor substrate 1 → cathode electrode 8. A current path is formed, and a Schottky diode current flows along the path of anode electrode 7 → gate electrode 6 → n-type epitaxial semiconductor layer 2 → n-type semiconductor substrate 1 → cando electrode 8, and a Schottky diode current flows through the anode electrode 7 - + A diode current flows through the path of p-type region 3 → n-type epitaxial semiconductor layer 2 → n-type semiconductor substrate 1 → cando electrode 8.
一方、アノード電極７にカソード電極８に対してしきい
値電圧以下の電圧を印加した場合、チャネルが形成され
ないためチャネル電流は流れず、ショットキーダイオー
ド電流、ダイオード電流も流れない。On the other hand, when a voltage lower than the threshold voltage is applied to the anode electrode 7 with respect to the cathode electrode 8, a channel is not formed, so no channel current flows, and neither a Schottky diode current nor a diode current flows.
第２図に本実施例による半導体装置の電流−電圧特性を
示す。ここで、順方向については、しきい値電圧ｖｔｈ
以上で同図の特性１１に示すようにチャネル電流が流れ
始め、ｎ型エピタキシャル半導体層２とゲート電極６に
よって形成されるショットキー接合の接合電圧’Ｐｇ以
上で同図の特性１２に示すようにショットキーダイオー
ド電流が流れ始め、さらにｎ型エピタキシャル半導体層
２とｐ型領域３で形成されるｐｎ接合の拡散電圧”ｂ１
以上では同図の特性１３に示すようにダイオード電流が
流れ始める。よって、全電流はこれらの和となり、同図
の特性１４に示すようになる。一方、逆方向には電流は
流れない。FIG. 2 shows the current-voltage characteristics of the semiconductor device according to this example. Here, in the forward direction, the threshold voltage vth
With the above, the channel current starts to flow as shown in characteristic 11 of the figure, and when the junction voltage of the Schottky junction formed by the n-type epitaxial semiconductor layer 2 and the gate electrode 6 exceeds 'Pg, as shown in characteristic 12 of the figure. The Schottky diode current begins to flow, and the diffusion voltage "b1" of the pn junction formed between the n-type epitaxial semiconductor layer 2 and the p-type region 3 increases.
In this case, a diode current begins to flow as shown in characteristic 13 in the figure. Therefore, the total current is the sum of these values, as shown in characteristic 14 in the figure. On the other hand, no current flows in the opposite direction.
このように、本実施例による半導体装置では、しきい値
電圧の設定によってＯＶから順方向電流を流し始めるこ
とが可能であり、順方向電圧が小さい２端子の整流素子
を実現することができる。As described above, in the semiconductor device according to this embodiment, it is possible to start flowing forward current from OV by setting the threshold voltage, and a two-terminal rectifier with a small forward voltage can be realized.
なお、本発明は上述の実施例にのみ限定される”もので
はなく、特許請求の範囲に記載された範囲内において種
々変更し得るものであることは言うまでもない。It goes without saying that the present invention is not limited only to the above-described embodiments, but can be modified in various ways within the scope of the claims.
以上のように、本発明による半導体装置は、Ｏｖから電
流が流れ始める絶縁ゲート型電界効果トランジスタを、
その制御端子を独立の端子とせず２−９へ−
端子素子として動作させるとともに、ショットキーダイ
オードを絶縁ゲート型電界効果トランジスタと並列に形
成するようＫしたので、順方向電圧の増加に伴って、チ
ャネル電流、ショットキーダイオード電流およびダイオ
ード電流を頴次流し始めることによって項方向電圧の小
さい整流素子を２端子で実現することが可能でラシ、整
流回路の構成を複雑化することなく整流素子の順方向損
失を低減できる効果がある。As described above, the semiconductor device according to the present invention includes an insulated gate field effect transistor in which current begins to flow from Ov.
Since the control terminal is not made an independent terminal and is operated as a terminal element, and the Schottky diode is formed in parallel with the insulated gate field effect transistor, as the forward voltage increases, By starting to flow the channel current, Schottky diode current, and diode current sequentially, it is possible to realize a rectifying element with a small voltage in the forward direction using two terminals. This has the effect of reducing directional loss.
第１図は本発明による一実施例の半導体装置の断面図、
第２図は本発明による実施例の半導体装置の電流−電圧
特性を示す図、第３図は従来のダイオードおよび３端子
整流素子の電流−電圧特性を示す図である。
１・・・・低抵抗ｎ型半導体基板、２・・・・ｈ型エピ
タキシャル半導体層、３・Φ・・ｐ型領−ト電極、Ｔ・
・・・アノード電極、８曇・拳ｅカソード電極、９・・
・・ｎ型チャネル、１０・・・・溝。
特許出願人 日本電信電話株式会社
代 理 人 山 川 政 樹（ほか１名）第２因
第１＠
第３図FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a diagram showing current-voltage characteristics of a semiconductor device according to an embodiment of the present invention, and FIG. 3 is a diagram showing current-voltage characteristics of a conventional diode and a three-terminal rectifier. DESCRIPTION OF SYMBOLS 1...Low resistance n-type semiconductor substrate, 2...H-type epitaxial semiconductor layer, 3...Φ...p-type region electrode, T...
...anode electrode, 8 cloudy fist e cathode electrode, 9...
...n-type channel, 10...groove. Patent applicant: Nippon Telegraph and Telephone Corporation Agent: Masaki Yamakawa (and 1 other person) 2nd cause 1 @ Figure 3
Claims (1)
第２の導電型を有するチャネル形成領域と、前記チャネ
ル形成領域内に形成された第１の導電型を有するドレイ
ン領域と、前記ドレイン領域内において前記第１の主両
側から半導体基板に達するように形成された溝と、前記
溝内に形成されたゲート絶縁膜およびゲート電極と、前
記半導体基板の第２の主面側に形成されたソース電極と
から構成される構造の絶縁ゲート型電界効果トランジス
タから成り、前記溝内に形成された前記ゲート絶縁膜の
一部が除去されて前記ゲート電極と前記半導体基板との
間でショットキー接合部を設け、さらに前記チャネル形
成領域と前記ドレイン領域と前記ゲート電極とを互いに
電気的に接続する電極を設けたことを特徴とする半導体
装置。a channel formation region having a second conductivity type formed on the first main surface side of a semiconductor substrate having a first conductivity type; and a drain region having a first conductivity type formed within the channel formation region. , a groove formed in the drain region to reach the semiconductor substrate from both sides of the first main surface, a gate insulating film and a gate electrode formed in the groove, and a second main surface side of the semiconductor substrate. A part of the gate insulating film formed in the groove is removed to form a gap between the gate electrode and the semiconductor substrate. What is claimed is: 1. A semiconductor device comprising: a Schottky junction; and an electrode for electrically connecting the channel forming region, the drain region, and the gate electrode to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63242281A JPH0291975A (en) | 1988-09-29 | 1988-09-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63242281A JPH0291975A (en) | 1988-09-29 | 1988-09-29 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0291975A true JPH0291975A (en) | 1990-03-30 |
Family
ID=17086928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63242281A Pending JPH0291975A (en) | 1988-09-29 | 1988-09-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0291975A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5258640A (en) * | 1992-09-02 | 1993-11-02 | International Business Machines Corporation | Gate controlled Schottky barrier diode |
| US5430323A (en) * | 1992-10-02 | 1995-07-04 | Fuji Electric Co., Ltd. | Injection control-type Schottky barrier rectifier |
| JP2003178369A (en) * | 2002-08-09 | 2003-06-27 | Sony Corp | Right management method, record regeneration method and right providing device |
| WO2005074025A2 (en) * | 2002-12-20 | 2005-08-11 | Hamza Yilmaz | Self-aligned trench mos junctions field-effect transistor for high-frequency applications |
| WO2011105434A1 (en) * | 2010-02-23 | 2011-09-01 | 富士電機ホールディングス株式会社 | Semiconductor device |
| WO2013057564A1 (en) * | 2011-10-18 | 2013-04-25 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method of producing the same |
-
1988
- 1988-09-29 JP JP63242281A patent/JPH0291975A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5258640A (en) * | 1992-09-02 | 1993-11-02 | International Business Machines Corporation | Gate controlled Schottky barrier diode |
| US5430323A (en) * | 1992-10-02 | 1995-07-04 | Fuji Electric Co., Ltd. | Injection control-type Schottky barrier rectifier |
| JP2003178369A (en) * | 2002-08-09 | 2003-06-27 | Sony Corp | Right management method, record regeneration method and right providing device |
| WO2005074025A2 (en) * | 2002-12-20 | 2005-08-11 | Hamza Yilmaz | Self-aligned trench mos junctions field-effect transistor for high-frequency applications |
| WO2005074025A3 (en) * | 2002-12-20 | 2006-01-26 | Hamza Yilmaz | Self-aligned trench mos junctions field-effect transistor for high-frequency applications |
| WO2011105434A1 (en) * | 2010-02-23 | 2011-09-01 | 富士電機ホールディングス株式会社 | Semiconductor device |
| US8896084B2 (en) | 2010-02-23 | 2014-11-25 | Yoshitaka Sugawara | Semiconductor device |
| WO2013057564A1 (en) * | 2011-10-18 | 2013-04-25 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device and method of producing the same |
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