JPH06291337A - Voltage regulation - Google Patents

Voltage regulation

Info

Publication number
JPH06291337A
JPH06291337A JP7353893A JP7353893A JPH06291337A JP H06291337 A JPH06291337 A JP H06291337A JP 7353893 A JP7353893 A JP 7353893A JP 7353893 A JP7353893 A JP 7353893A JP H06291337 A JPH06291337 A JP H06291337A
Authority
JP
Japan
Prior art keywords
region
type
base region
constant voltage
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP7353893A
Other languages
Japanese (ja)
Inventor
Kazuo Yamagishi
和夫 山岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP7353893A priority Critical patent/JPH06291337A/en
Publication of JPH06291337A publication Critical patent/JPH06291337A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To provide a voltage regulation diode for a MOSFET type not exceeding 6V, where a backward direction characteristic and a forward direction characteristic are improved up to a stage of the practical use. CONSTITUTION:The P-type base region 2 and drain region 3 are formed on the surface side of a semiconductor substrate being an n-type collector region 1 while an n-type emitter region 4 is formed in the central part of the base region 2 and an anode electrode 7 formed on the emitter region 4 is extended on an insulating film 6 on a channel part 5 between the base region 2 and the drain region so as to form a p-channel type MOSFET 11 of the drain region 3, the base region 2 and the emitter region 4. Then, a p-type by-pass region 10 partially contacting the anode electrode 7 and the base region 2 with the emitter region 4 in a MOSFET type voltage regulation type where an NPN transistor is formed of the collector region 1, the base region 2 and the emitter region 4 in the vertical direction is formed, in order to improve a breakdown waveform.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、MOSFETのゲート
電圧でツェナーブレークダウン電圧をコントロールする
MOSFET型の6V以下用定電圧ダイオードに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET type constant voltage diode for 6V or less, which controls the Zener breakdown voltage by the gate voltage of the MOSFET.

【0002】[0002]

【従来の技術】6V以下の電圧でブレークダウンを起こ
す定電圧ダイオードとしては、PN接合型ダイオードが
一般的である。このPN接合型定電圧ダイオードの逆方
向特性のブレークダウン波形は、図7の波形(ヘ)に示
すように印加される逆電圧VRがブレークダウンを起こ
させるしきい値のツェナー電圧VZの前後のときに逆電
流IRが緩いカーブを描いて流れ、ブレークダウン後は
逆電流IRが逆電圧VRにほぼ比例して流れる波形となっ
ている。かかるPN接合型定電圧ダイオードは、ツェナ
ー電圧VZ付近のブレークダウン波形が立ち上がりの悪
い緩いカーブの波形であり、また、ブレークダウン後の
波形が傾き角θの小さい傾斜した波形であるために、ミ
リ単位の微小電流制御などに不適当なことが多い。
2. Description of the Related Art A PN junction type diode is generally used as a constant voltage diode which causes a breakdown at a voltage of 6 V or less. The breakdown waveform of the reverse characteristic of this PN junction type constant voltage diode is the zener voltage V Z of the threshold value at which the reverse voltage V R applied causes breakdown as shown in the waveform (f) of FIG. The reverse current I R flows in a gentle curve before and after, and after the breakdown, the reverse current I R flows in almost proportion to the reverse voltage V R. In such a PN junction type constant voltage diode, the breakdown waveform in the vicinity of the Zener voltage V Z is a waveform of a gentle curve with a poor rise, and the waveform after breakdown is an inclined waveform with a small inclination angle θ. It is often unsuitable for millimeter current control.

【0003】そこで、上記のブレークダウン波形をシャ
ープなものに改善した6V以下用定電圧ダイオードとし
て、例えば図4に示すようなMOSFET型定電圧ダイ
オードが知られている。図4の定電圧ダイオードを、図
5の等価回路を参照して説明する。
Therefore, as a constant voltage diode for 6 V or less in which the above-mentioned breakdown waveform is improved to a sharp one, for example, a MOSFET type constant voltage diode as shown in FIG. 4 is known. The constant voltage diode of FIG. 4 will be described with reference to the equivalent circuit of FIG.

【0004】N型の半導体基板(1)の表面にP型不純
物を選択拡散してベース〔ソース〕領域(2)とその近
傍にドレイン領域(3)が形成される。ベース領域(2)
の中央部にN型不純物を選択拡散してN+型のエミッタ
〔ゲート〕領域(4)が形成される。この半導体基板
(1)の表面に形成された絶縁膜(6)のエミッタ領域
(4)とドレイン領域(3)上の部分が選択的に除去され
て、露呈したエミッタ領域(4)上にアノード〔ゲー
ト〕電極(7)が形成され、ドレイン領域(3)上にショ
ート電極(8)が形成される。アノード電極(7)は、ベ
ース領域(2)とドレイン電極(3)の間のチャネル部
(5)上の絶縁膜(6)上まで延在する。半導体基板
(1)の裏面にカソード電極(9)が形成される。半導体
基板(1)は、例えばN+型サブストレート(1')にN-
型エピタキシャル層(1'')を積層したもので、半導体
基板(1)でコレクタ領域(1)が形成される。
P-type impurities are selectively diffused on the surface of an N-type semiconductor substrate (1) to form a base [source] region (2) and a drain region (3) in the vicinity thereof. Base area (2)
N type impurities are selectively diffused in the central portion of the N to form an N + type emitter [gate] region (4). A portion of the insulating film (6) formed on the surface of the semiconductor substrate (1) on the emitter region (4) and the drain region (3) is selectively removed, and the anode is formed on the exposed emitter region (4). A [gate] electrode (7) is formed, and a short electrode (8) is formed on the drain region (3). The anode electrode (7) extends onto the insulating film (6) on the channel portion (5) between the base region (2) and the drain electrode (3). A cathode electrode (9) is formed on the back surface of the semiconductor substrate (1). The semiconductor substrate (1) is, for example, N -type substrate (1 ′) and N
A type epitaxial layer (1 '') is laminated to form a collector region (1) on a semiconductor substrate (1).

【0005】横に並ぶドレイン領域(3)とベース領域
(2)、エミッタ領域(4)でPチャネル型MOSFET
(11)が形成され、縦方向のコレクタ領域(1)とベー
ス領域(2)、エミッタ領域(4)でN+PN+型トランジ
スタ(12)が形成される。トランジスタ(12)のベース
領域(2)がMOSFET(11)のソース領域となり、
トランジスタ(12)のエミッタ領域(4)がMOSFE
T(11)のゲート領域となって、MOSFET(11)の
ゲート電圧VTで定電圧ダイオードのツェナー電圧VZ
コントロールされる。
A drain region (3), a base region (2), and an emitter region (4) arranged side by side are P-channel MOSFETs.
(11) is formed, and an N + PN + type transistor (12) is formed by the vertical collector region (1), base region (2) and emitter region (4). The base region (2) of the transistor (12) becomes the source region of the MOSFET (11),
The emitter region (4) of the transistor (12) is MOSFE
In the gate region of T (11), the zener voltage V Z of the constant voltage diode is controlled by the gate voltage V T of the MOSFET (11).

【0006】すなわち、図4の定電圧ダイオードに逆バ
イアス電圧を印加すると、アノード電極(7)に印加さ
れるマイナスのゲート電圧VTが所定の値になったとき
に、MOS構造のチャネル部(5)が導通してMOSF
ET(11)がオンし、このときのチャネル部(5)を流
れるチャネル電流がトランジスタ(12)のベース電流と
なってトランジスタ(12)がオンする。トランジスタ
(12)のオンで定電圧ダイオードがフレークダウンをし
て、図6(a)の波形(ハ)に示すブレークダウン波形
が得られる。
That is, when a reverse bias voltage is applied to the constant voltage diode shown in FIG. 4, when the negative gate voltage V T applied to the anode electrode (7) reaches a predetermined value, the channel portion of the MOS structure ( 5) becomes conductive and MOSF
The ET (11) is turned on, and the channel current flowing through the channel portion (5) at this time becomes the base current of the transistor (12), and the transistor (12) is turned on. When the transistor (12) is turned on, the constant voltage diode breaks down, and the breakdown waveform shown in the waveform (c) of FIG. 6A is obtained.

【0007】MOSFET(11)をオンさせるゲート電
圧VTをコントロールすることで、定電圧ダイオードの
ツェナー電圧VZ付近のブレークダウン波形を立ち上が
りのシャープな波形にすることができる。また、トラン
ジスタ(12)の電流増幅率h FEで、ブレークダウン後の
波形の傾きを90°近くに起こすことができる。このよ
うなブレークダウン波形の定電圧ダイオードは、ミリ単
位の微小電流制御などに有利である。
Gate voltage for turning on the MOSFET (11)
Pressure VTBy controlling the
Zener voltage VZThe breakdown waveform in the vicinity rises
It is possible to make a sharp waveform. Also, Tran
Current gain h of transistor (12) FEAnd after the breakdown
It is possible to cause the waveform inclination to approach 90 °. This
A constant voltage diode with a breakdown waveform
This is advantageous for controlling a small amount of current.

【0008】[0008]

【発明が解決しようとする課題】ところで、図4のMO
SFET型定電圧ダイオードは、MOSFET(11)が
オンしたときに横方向に並ぶエミッタ領域(4)・ベー
ス領域(2)・チャネル部(5)・ドレイン領域(3)の
区域にN+PNPのサイリスタが寄生的に発生する。こ
の寄生サイリスタは、定電圧ダイオードがブレークダウ
ンを起こすと即座にオンして、図6(a)に示すよう
に、ツェナー飽和電流IBOを小さく制限して、ツェナー
飽和電流IBOが実用上に必要な値まで大きく設定できな
くなる不具合があった。
By the way, the MO of FIG.
The SFET type constant voltage diode has N + PNP in the area of the emitter region (4), the base region (2), the channel portion (5), and the drain region (3) which are arranged side by side when the MOSFET (11) is turned on. Thyristor occurs parasitically. This parasitic thyristor is turned on immediately when the constant voltage diode breaks down, and as shown in FIG. 6A, the Zener saturation current I BO is limited to a small value so that the Zener saturation current I BO becomes practical. There was a problem that the required value could not be set too high.

【0009】また、図4の定電圧ダイオードの順方向特
性は、図6(b)の波形(ニ)のようになる。つまり、
アノード電極(7)にプラスの順電圧VFを印加した場
合、トランジスタ(12)のベース領域(2)が電気的に
浮いた状態になっているので、エミッタ領域(4)の耐
圧が逆方向の耐圧となって外に現われて、順電圧VF
順電流IFの順方向特性の波形は、通常のツェナーダイ
オードの図6(b)の鎖線のVF波形(ホ)と逆のLV
CEO波形(ニ)となる。そのため、図4の定電圧ダイオ
ードは、順方向特性の利用分野が極限られる用途の狭い
ものとなっている。
The forward characteristic of the constant voltage diode of FIG. 4 is as shown in the waveform (d) of FIG. 6 (b). That is,
When a positive forward voltage V F is applied to the anode electrode (7), since the base region (2) of the transistor (12) is in an electrically floating state, the breakdown voltage of the emitter region (4) is in the reverse direction. appear in the outside becomes the breakdown voltage, the waveform of the forward characteristic of the forward voltage V F and the forward current I F, V F waveform and reverse (e) LV in chain line in FIG conventional Zener diode 6 (b)
It becomes the CEO waveform (d). Therefore, the constant voltage diode of FIG. 4 has a narrow range of applications where the field of application of the forward characteristic is extremely limited.

【0010】実際、図4の定電圧ダイオードは文献上の
もので、逆方向特性と順方向特性の双方が利用分野の狭
いものであることから、未だ実用化されていないのが現
状である。
Actually, the constant voltage diode of FIG. 4 is based on the literature, and since both the reverse characteristic and the forward characteristic have narrow fields of use, they are not yet in practical use.

【0011】本発明の目的は、逆方向特性と順方向特性
を実用的な段階まで改善したMOSFET型の6V以下
用定電圧ダイオードを提供することにある。
It is an object of the present invention to provide a MOSFET type constant voltage diode for 6 V or less in which the reverse characteristic and the forward characteristic are improved to a practical level.

【0012】[0012]

【課題を解決するための手段】本発明は、コレクタ領域
となる一導電型半導体基板の表面の離反する二領域に他
導電型不純物を選択拡散して形成されたベース領域及び
ドレイン領域と、ベース領域に他導電型不純物を選択拡
散して形成されたエミッタ領域と、ベース領域とドレイ
ン領域の間のチャンネル部上とベース領域上とに形成さ
れた絶縁膜と、エミッタ領域上と絶縁膜上に形成された
アノード電極と、半導体基板の裏面に形成されたカソー
ド電極を有するMOSFET型の定電圧ダイオードにお
ける前記エミッタ領域に部分的に、前記ベース領域と同
一導電型で、前記アノード電極とベース領域を導通させ
るバイパス領域を形成したことにより、上記目的を達成
するものである。
SUMMARY OF THE INVENTION According to the present invention, a base region and a drain region formed by selectively diffusing impurities of another conductivity type in two regions of a surface of a one conductivity type semiconductor substrate, which are collector regions, are separated from each other, and a base. An emitter region formed by selectively diffusing another conductivity type impurity into the region, an insulating film formed on the channel region between the base region and the drain region and on the base region, and on the emitter region and the insulating film. In the MOSFET constant voltage diode having the formed anode electrode and the cathode electrode formed on the back surface of the semiconductor substrate, the anode electrode and the base region are partially formed in the same emitter type as the base region. By forming the bypass region for conduction, the above object is achieved.

【0013】[0013]

【作用】MOSFET型定電圧ダイオードのベース領域
〔ソース領域〕とアノード電極〔ゲート電極〕をバイパ
ス領域でコンタクトさせることにより、MOSFETの
オン時に流れるチャネル電流が抑制されてエミッタ領域
とベース領域とコネクタ領域で形成されるトランジスタ
の電流増幅率hFEが下がり、エミッタ領域とベース領域
とチャネル部とドレイン領域の横方向に寄生的に発生す
るサイリスタがオンするタイミングが遅れ、これにより
逆方向特性のツェナー飽和電流IBOが増大する。
By contacting the base region [source region] and the anode electrode [gate electrode] of the MOSFET type constant voltage diode in the bypass region, the channel current flowing when the MOSFET is turned on is suppressed, and the emitter region, the base region and the connector region are suppressed. The current amplification factor h FE of the transistor formed in 1 is decreased, and the timing at which the thyristor parasitically generated in the lateral direction of the emitter region, the base region, the channel portion, and the drain region is turned on is delayed, which causes Zener saturation of the reverse characteristic. The current I BO increases.

【0014】また、ベース領域〔ソース領域〕とアノー
ド電極〔ゲート電極〕をバイパス領域でコンタクトさせ
ると、順方向に対しては通常のPN接合型定電圧ダイオ
ードと同様な順方向特性となる。
When the base region [source region] and the anode electrode [gate electrode] are brought into contact with each other in the bypass region, the forward characteristic is the same as that of a normal PN junction type constant voltage diode in the forward direction.

【0015】[0015]

【実施例】図4の定電圧ダイオードに適用した本発明実
施例を図1に、その等価回路を図2に示す。なお、図1
及び図2における図4及び図5と同一、又は、相当部分
には同一符号を付して、説明は省略する。
FIG. 1 shows an embodiment of the present invention applied to the constant voltage diode of FIG. 4 and its equivalent circuit is shown in FIG. Note that FIG.
2 and FIG. 2 that are the same as or equivalent to those in FIG. 4 and FIG.

【0016】図1のMOSFET型6V以下用定電圧ダ
イオードは、エミッタ領域(4)の中央部にベース領域
(2)と同一導電型のバイパス領域(10)をベース領域
(2)まで形成して、バイパス領域(10)でベース領域
(2)とアノード電極(7)をコンタクトしたことを特徴
とする。この定電圧ダイオードは、等価回路的には図2
に示すように、Pチャネル型MOSFET(11)のソー
スとベース間、或いは、N+PN+型トランジスタ(12)
のベースとエミッタ間に抵抗(13)が接続されたものと
なる。この抵抗(13)は、Pチャネル型MOSFET
(11)をオンさせるチャネル電流がベース領域(2)を
流れるときのベース領域(2)での抵抗成分に相当す
る。トランジスタ(12)のベースとエミッタ間への抵抗
(13)の追加接続により、トランジスタ(12)の電流増
幅率hFEが下がる。
In the MOSFET type constant voltage diode for 6 V or less of FIG. 1, a bypass region (10) of the same conductivity type as the base region (2) is formed up to the base region (2) in the center of the emitter region (4). The base region (2) and the anode electrode (7) are in contact with each other in the bypass region (10). This constant voltage diode is equivalent to that shown in FIG.
As shown in, between the source and the base of the P-channel MOSFET (11) or the N + PN + type transistor (12)
A resistor (13) is connected between the base and the emitter of. This resistor (13) is a P-channel MOSFET
It corresponds to the resistance component in the base region (2) when the channel current that turns on (11) flows in the base region (2). The additional connection of the resistor (13) between the base and the emitter of the transistor (12) reduces the current amplification factor h FE of the transistor (12).

【0017】図1の定電圧ダイオードは、図4の定電圧
ダイオードと同様に、MOSFET(11)のゲート電圧
Tで定電圧ダイオードのツェナー電圧VZがコントロー
ルされる。つまり、アノード電極(7)に印加されるマ
イナスのゲート電圧VTが所定の値になったときに、チ
ャネル部(5)が導通してMOSFET(11)がオン
し、このときのチャネル部(5)を流れるチャネル電流
でトランジスタ(12)がオンして、定電圧ダイオードが
フレークダウンを起こす。
In the constant voltage diode of FIG. 1, the zener voltage V Z of the constant voltage diode is controlled by the gate voltage V T of the MOSFET (11) as in the constant voltage diode of FIG. That is, when the negative gate voltage V T applied to the anode electrode (7) reaches a predetermined value, the channel part (5) is turned on and the MOSFET (11) is turned on. The transistor (12) is turned on by the channel current flowing in (5), and the voltage regulator diode flakes down.

【0018】図1の定電圧ダイオードの場合も、MOS
FET(11)がオンしたときに、横方向に並ぶエミッタ
領域(4)・ベース領域(2)・チャネル部(5)・ドレ
イン領域(3)の区域にN+PNPのサイリスタが寄生的
に発生する。この寄生サイリスタは、定電圧ダイオード
のブレークダウン電流でオンするが、バイパス領域(1
0)による抵抗(13)の追加によるトランジスタ(12)
の電流増幅率hFEの低下で寄生サイリスタのオンするタ
イミングが遅れる。その結果、図1の定電圧ダイオード
の逆方向特性は、図3(a)のブレークダウン波形
(イ)に示すようになり、ブレークダウンから寄生サイ
リスタがオンするまでの時間延長分だけツェナー飽和電
流IBOが大きくなる。このツェナー飽和電流IBOの増大
率は、バイパス領域(10)の面積、不純物濃度などで容
易に調整でき、ツェナー飽和電流IBOを実用上に必要な
値にすることが可能となった。
In the case of the constant voltage diode shown in FIG.
When the FET (11) is turned on, N + PNP thyristors are parasitically generated in the areas of the emitter region (4), the base region (2), the channel part (5), and the drain region (3) that are arranged side by side. To do. This parasitic thyristor turns on by the breakdown current of the constant voltage diode, but the bypass area (1
Transistor (12) by adding resistor (13) by (0)
Due to the decrease of the current amplification factor h FE of, the timing of turning on the parasitic thyristor is delayed. As a result, the reverse characteristic of the constant voltage diode in FIG. 1 becomes as shown in the breakdown waveform (a) in FIG. 3 (a), and the Zener saturation current is increased by the time extension from the breakdown until the parasitic thyristor turns on. I BO gets bigger. Growth rate of the Zener saturation current I BO is the area of the bypass area (10), can be easily adjusted by such an impurity concentration, it becomes possible to the value required for practical use zener saturation current I BO.

【0019】また、図1の定電圧ダイオードの順方向特
性は、図2(b)の波形(ロ)に示すように、通常のツ
ェナーダイオードの順方向特性と同様なVF波形とな
る。つまり、アノード電極(7)にプラスの順電圧VF
印加した場合、トランジスタ(12)のベース領域(2)
がバイパス領域(10)でアノード電極(7)にコンタク
トされている状態にあるので、順方向耐圧はコレクタ領
域(1)とベース領域(2)のPN接合の耐圧となり、順
方向特性は図2(b)の波形(ロ)となる。
The forward characteristic of the constant voltage diode shown in FIG. 1 has a V F waveform similar to the forward characteristic of a normal Zener diode, as shown in the waveform (b) of FIG. That is, when a positive forward voltage V F is applied to the anode electrode (7), the base region (2) of the transistor (12) is
Is in contact with the anode electrode (7) in the bypass region (10), the forward breakdown voltage is the breakdown voltage of the PN junction between the collector region (1) and the base region (2), and the forward characteristics are as shown in FIG. The waveform (b) in (b) is obtained.

【0020】なお、図1の定電圧ダイオードは、Pチャ
ネル型で説明したが、本発明はNチャネル型定電圧ダイ
オードであっても同様に適応できる。
Although the constant voltage diode of FIG. 1 has been described as a P-channel type, the present invention can be similarly applied to an N-channel type constant voltage diode.

【0021】[0021]

【発明の効果】本発明によれば、MOSFET型定電圧
ダイオードのベース領域〔ソース領域〕とアノード電極
〔ゲート電極〕をコンタクトするバイパス領域により、
MOSFETのオン時に流れるチャネル電流が抑制され
てエミッタ領域とベース領域とコネクタ領域で形成され
るトランジスタの電流増幅率hFEが下がり、エミッタ領
域とベース領域とチャネル部とドレイン領域の横方向に
寄生的に発生するサイリスタがオンするタイミングが遅
れて、逆方向特性のツェナー飽和電流IBOの増大化が図
れ、ブレークダウン波形のシャープな実用価値の高い定
電圧ダイオードが提供できる。
According to the present invention, the bypass region for contacting the base region [source region] and the anode electrode [gate electrode] of the MOSFET type constant voltage diode,
The channel current that flows when the MOSFET is turned on is suppressed, and the current amplification factor h FE of the transistor formed in the emitter region, the base region, and the connector region is lowered, and the parasitic current is parasitic in the lateral direction of the emitter region, the base region, the channel portion, and the drain region. When the thyristor generated at 1 is turned on, the Zener saturation current I BO having the reverse characteristic can be increased, and a constant voltage diode having a sharp breakdown waveform and high practical value can be provided.

【0022】また、バイパス領域の追加形成で、通常の
PN接合型定電圧ダイオードと同様な順方向特性が得ら
れて、通常のPN接合型定電圧ダイオードと同様な広い
用途に適用できるMOSFET型定電圧ダイオードが提
供できる。
Further, by forming the bypass region, the forward characteristic similar to that of the normal PN junction type constant voltage diode is obtained, and the MOSFET type constant voltage diode which can be applied to a wide range of applications like the normal PN junction type constant voltage diode is obtained. A voltage diode can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示す断面図FIG. 1 is a sectional view showing an embodiment of the present invention.

【図2】図1の定電圧ダイオードの等価回路図FIG. 2 is an equivalent circuit diagram of the constant voltage diode shown in FIG.

【図3】(a)は図1の定電圧ダイオードの逆方向特性
図、(b)は図1の定電圧ダイオードの順方向特性図
3A is a reverse characteristic diagram of the constant voltage diode of FIG. 1, and FIG. 3B is a forward characteristic diagram of the constant voltage diode of FIG.

【図4】本発明の前提となるMOSFET型6V以下用
定電圧ダイオードの断面図
FIG. 4 is a sectional view of a MOSFET type constant voltage diode for 6 V or less, which is a premise of the present invention.

【図5】図4の定電圧ダイオードの等価回路図5 is an equivalent circuit diagram of the constant voltage diode of FIG.

【図6】(a)は図4の定電圧ダイオードの逆方向特性
図、(b)は図4の定電圧ダイオードの順方向特性図
6A is a reverse characteristic diagram of the constant voltage diode of FIG. 4, and FIG. 6B is a forward characteristic diagram of the constant voltage diode of FIG.

【図7】一般的なPN接合型定電圧ダイオードの逆方向
特性図
FIG. 7 is a reverse characteristic diagram of a general PN junction type constant voltage diode.

【符号の説明】[Explanation of symbols]

1 半導体基板〔コレクタ領域〕 2 ベース領域 3 ドレイン領域 4 エミッタ領域 5 チャネル部 6 絶縁層 7 アノード電極 9 カソード電極 10 バイパス領域 11 MOSFET 12 トランジスタ 1 Semiconductor substrate [collector region] 2 Base region 3 Drain region 4 Emitter region 5 Channel part 6 Insulating layer 7 Anode electrode 9 Cathode electrode 10 Bypass region 11 MOSFET 12 Transistor

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 コレクタ領域となる一導電型半導体基板
の表面の離反する二領域に他導電型不純物を選択拡散し
て形成されたベース領域及びドレイン領域と、ベース領
域に他導電型不純物を選択拡散して形成されたエミッタ
領域と、ベース領域とドレイン領域の間のチャネル部上
とベース領域上に形成された絶縁膜と、エミッタ領域上
と絶縁膜上に形成されたアノード電極と、半導体基板の
裏面に形成されたカソード電極とを有するMOSFET
型の定電圧ダイオードであって、 前記エミッタ領域に部分的に、前記ベース領域と同一導
電型で、前記アノード電極とベース領域を導通させるバ
イパス領域を形成したことを特徴とする定電圧ダイオー
ド。
1. A base region and a drain region formed by selectively diffusing another conductivity type impurity in two regions of a surface of a one conductivity type semiconductor substrate, which are collector regions, separated from each other, and another conductivity type impurity is selected in the base region. A diffused emitter region, an insulating film formed on the channel region between the base region and the drain region and on the base region, an anode electrode formed on the emitter region and the insulating film, and a semiconductor substrate Having a cathode electrode formed on the back surface of the
1. A constant voltage diode of the type: wherein a bypass region, which has the same conductivity type as that of the base region and is electrically connected to the anode electrode and the base region, is formed in the emitter region.
【請求項2】 請求項1記載のドレイン領域とコレクタ
領域及びベース領域がPチャネル型MOSFETで、コ
レクタ領域とベース領域及びエミッタ領域がNPN型ト
ランジスタであることを特徴とする定電圧ダイオード。
2. A constant voltage diode according to claim 1, wherein the drain region, the collector region and the base region are P-channel type MOSFETs, and the collector region, the base region and the emitter region are NPN type transistors.
JP7353893A 1993-03-31 1993-03-31 Voltage regulation Withdrawn JPH06291337A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7353893A JPH06291337A (en) 1993-03-31 1993-03-31 Voltage regulation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7353893A JPH06291337A (en) 1993-03-31 1993-03-31 Voltage regulation

Publications (1)

Publication Number Publication Date
JPH06291337A true JPH06291337A (en) 1994-10-18

Family

ID=13521117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7353893A Withdrawn JPH06291337A (en) 1993-03-31 1993-03-31 Voltage regulation

Country Status (1)

Country Link
JP (1) JPH06291337A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07131037A (en) * 1993-10-29 1995-05-19 Nec Corp Semiconductor element
US6791123B2 (en) * 2001-10-01 2004-09-14 Nec Electronics Corporation ESD protection element
JP2010512003A (en) * 2006-11-30 2010-04-15 アルファ アンド オメガ セミコンダクター,リミテッド Vertical TVS diode array structure without latch-up phenomenon using trench insulation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07131037A (en) * 1993-10-29 1995-05-19 Nec Corp Semiconductor element
US6791123B2 (en) * 2001-10-01 2004-09-14 Nec Electronics Corporation ESD protection element
JP2010512003A (en) * 2006-11-30 2010-04-15 アルファ アンド オメガ セミコンダクター,リミテッド Vertical TVS diode array structure without latch-up phenomenon using trench insulation

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