JP3084859B2 - Junction type field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a junction field effect transistor having a PN junction in a channel region.

[0002]

2. Description of the Related Art Generally, a junction type field effect transistor,
For example, a Schottky (barrier) gate field effect transistor made of GaAs controls a carrier flow by providing a Schottky barrier in a gate region and reversely biasing the Schottky barrier to change the width of a space charge region. is there.

As shown in FIG. 11, a conventional GaAs Schottky (barrier) gate field effect transistor has two N-type high concentration regions (low resistance regions) 22 and 23 on the surface of a semi-insulating GaAs substrate 21. With
An N-type low-concentration region (channel region) 24 is provided between the low-resistance regions 22 and 23. This channel region 24
Has a P-type high-concentration region 25 serving as a gate PN junction Ja.
Is formed. Then, a drain electrode 26 and a source electrode 27 are formed on the two low-resistance regions 22 and 23 by ohmic contact, respectively.
A gate electrode 28 formed by Schottky contact is formed thereon.

In the example shown in the figure, the ground potential Vss is applied to the source electrode 27, and the gate electrode 28 is negatively connected to the source such that the PN junction Ja formed by the channel region 24 and the high concentration region 25 is in a reverse bias state. potential V _G is applied. A drain electrode 26, a positive potential V _D is applied.

[0005] Then, the gate voltage V _G applied to the gate electrode 28, the space charge region extends downwardly from the gate. As a result, electron passage flowing from the source to the drain (channel) is subjected to modulation by the depth of the space charge region, the drain current is also controlled by the gate voltage V _G. FIG. 12 shows an equivalent circuit of the Schottky gate field effect transistor.

[0006]

Generally [0007] To improve the high frequency characteristics of a Schottky gate field effect transistor, it increases the cutoff frequency f _T, it is necessary to increase the resistance ratio of the input and output. Therefore, the characteristics of the junction field-effect transistor are improved as the gate length is shorter and the distance between the gate and source is smaller.

However, when the gate length is shortened, the energy per unit area increases, which causes a decrease in electrostatic strength, and causes a new problem that the reliability and the life of the transistor are significantly reduced. .

The present invention has been made in view of such problems, and an object of the present invention is to improve the characteristics (high-frequency characteristics) of a transistor without reducing the reliability and life of the transistor. It is an object of the present invention to provide a junction type field effect transistor which can be used.

[0009]

According to the present invention, a drain electrode 6 and a source electrode 7 are provided on low resistance regions 2 and 3 formed on the surface of a substrate 1, respectively, and a channel region 4 having a PN junction Ja is provided. In the junction field-effect transistor in which the gate electrode 8 is provided, at least one junction diode D is formed in the low-resistance region 3 below the source electrode 7, and the extraction electrode 10 of the junction diode D, the gate electrode 8, Are electrically connected to each other.

Further, a drain electrode 6 and a source electrode 7 are provided on the low resistance regions 2 and 3 formed on the surface of the substrate 1, respectively, and a channel region having _first and _second PN junctions Ja1 and Ja2. A first and a second gate electrode 8
In a junction type field effect transistor having a so-called dual gate structure provided with a and 8b, the source electrode 7
First and second junction diodes D ₁ and D ₂ are formed in the lower resistance lowering region 3, and the extraction electrode 10 a of the first junction diode D ₁ and the first gate electrode 8 a are electrically connected. while, constituting a second extraction electrode 10b of the junction diode D ₂ and a second gate electrode 8b are electrically connected.

The junction diode D (D₁, D
_Two) To form a PN junction Jb (Jb ₁, Jb_Two) Resistance
To the PN junction Ja (Ja₁, J
a_Two) Is set smaller than the resistance.

[0012]

According to the structure of the present invention, at least one junction diode D is formed in the low resistance region 3 below the source electrode 7, and the extraction electrode 10 and the gate electrode 8 of the junction diode D are electrically connected. And the resistance of the PN junction Jb constituting the junction diode D is set to be smaller than the resistance of the PN junction Ja in the channel region 4. Therefore, with the shortening of the gate length, the gate electrode 8 as a high potential (voltage higher than the breakdown voltage V _T) is applied, the high potential is absorbed by the junction diode D, and breakdown (breakdown) behavior of the junction field effect transistor according to a high potential Can be avoided.

For a junction type field effect transistor having a dual gate structure, first and second junction diodes D ₁ and D ₂ are formed in the low resistance region 3 below the source electrode 7 to form a _first junction diode. bonding the extraction electrodes 10a of the diode D ₁ and a first gate electrode 8a as well as electrically connected, to electrically connect the second extraction electrode 10b of the junction diode D ₂ and a second gate electrode 8b of the Thus, the breakdown phenomenon due to the high potential can be avoided.

As described above, according to the junction field effect transistor of the present invention, the gate length can be reduced without causing the breakdown phenomenon,
The improvement in the high-frequency characteristics of the transistor itself can be further promoted.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view showing the configuration of a junction field-effect transistor according to the first embodiment, for example, an N-channel Schottky (barrier) gate field-effect transistor (hereinafter simply referred to as a transistor) Tr1 made of GaAs.

As shown, the transistor Tr1 has two N-type high-concentration regions (low-resistance regions) 2 and 3 on the surface of a semi-insulating GaAs substrate 1, and these low-resistance regions 2 and 3 There is an N-type low concentration region (channel region) 4 between them. This channel region 4 has a gate PN
A P-type high-concentration region 5 serving as the junction Ja is formed. A drain electrode 6 and a source electrode 7 are formed on the two low-resistance regions 2 and 3 by ohmic contact, respectively.
Further, the gate electrode 8 is formed on the P-type high concentration region 5 by Schottky contact.

In the illustrated example, the ground potential V is applied to the source electrode 7.
ss is applied to the gate electrode 8, so that PN junction Ja with the channel region 4 in the high concentration region 5 is reversely biased state, a negative potential V _G to the source is applied. A positive potential V _D is applied to the drain electrode 6.

[0018] Then, the gate voltage V _G applied to the gate electrode 8, the space charge region extends downwardly from the gate. As a result, electron passage flowing from the source to the drain (channel) being modulated by the depth of the space charge region, the drain current is also controlled by the gate voltage V _G.

In this embodiment, one P-type high-concentration region 9 is formed in the low-resistance region 3 below the source electrode 7 to form a junction diode D formed by a PN junction Jb. The P-type high-concentration region 9 of the junction diode D
An extraction electrode 10 is formed thereon, and the extraction electrode 10 and the gate electrode 8 are electrically connected. FIG. 2 shows an equivalent circuit of the transistor Tr1.

Next, the operation of the transistor according to this embodiment will be described with reference to FIG. FIG. 3 shows the reverse breakdown voltage characteristics of the transistor Tr1, with the horizontal axis representing the gate-source voltage V _GS and the vertical axis representing the reverse current Is. In this figure, the curve shows the reverse breakdown voltage characteristics of the junction diode,
The curve shows the reverse breakdown voltage characteristics of the transistor. As can be seen from this figure, the junction diode D has its breakdown voltage V _F is set to be lower than the breakdown voltage V _T of the transistor Tr1.

Normally, the operating potential width (generally +1 V to -1)
Transistor Tr1 operating in V range), electron passage flowing from the source to the drain (channel) to receive the modulated by the depth of the space charge region, the drain current is also controlled by the gate voltage V _G.

When the gate length is designed to be short, for example, in order to improve the high-frequency characteristics, the energy per unit area increases, the high potential in the negative direction is easily applied to the gate electrode 8, and the breakdown voltage V _When a high potential equal to or higher than _T is applied, junction breakdown occurs at the PN junction Ja of the transistor Tr1.

However, in this embodiment, the PN
Since the junction diode D which is a cemented Jb is formed, the junction diode D at (breakdown voltage V _F of the junction diode) before the voltage reaches the breakdown voltage V _T of the transistor Tr1 is broken down, the transistor Tr1 Absorb such energy. As a result, the transistor T
The PN junction Ja of r1, will not take the high potential or voltage V _F, junction breakdown of the transistor Tr1 is avoided.

By the way, P constituting the junction diode D
When the N-junction Jb has a high resistance, that is, when the resistance of the low-resistance region 3 below the source electrode 7 is high, as shown in FIG. Lean on. At this time, the reverse withstand voltage curve of the junction diode D is determined by the transistor Tr1.
If each curve and the slope becomes smaller than the reverse breakdown voltage curve crosses of the transistor Tr1 takes a voltage larger than its breakdown voltage V _T transistor Tr
1 will be caused.

Therefore, in order to effectively prevent the destruction of the junction of the transistor Tr1, the PN constituting the junction diode D is required.
The resistance of the junction Jb is changed to the channel region 4 of the transistor Tr1.
It is important to make the resistance smaller than the resistance of the PN junction Ja in the above, so that the reverse breakdown curve of the junction diode D does not intersect with the reverse breakdown curve of the transistor Tr1 as shown by a broken line, for example. That is, the resistance is lowered by implanting silicon (Si) into the region 3 extending from below the source electrode 7 to the junction diode D.

According to the first embodiment, the source electrode 7
One junction diode D is formed in the low resistance region 3 of FIG.
Then, the extraction electrode 10 of the junction diode D is connected to the gate electrode.
The pole 8 is electrically connected to the
The resistance of the PN junction Jb constituting the
It is set to be smaller than the resistance of the PN junction Ja in region 4.
As the gate length is shortened, the gate electrode
8 at high potential (breakdown voltage V _TAbove high voltage) was applied
Even if the high potential is absorbed by the junction diode D
And breakdown of transistor Tr1 due to high potential
(Yield) phenomenon can be avoided. This means that
Gate without causing breakdown
Length can be shortened.
The high frequency characteristics of the star itself can be effectively improved
You.

Next, a modification of the first embodiment in which the junction diode D has a so-called back-to-back structure will be described with reference to FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof will be omitted.

The transistor Tr2 according to this modification is
It has substantially the same configuration as the first embodiment, except that two P-type high-concentration regions 9a and 9b are formed in the low-resistance region 3 below the source electrode 7, so that the first and second PN junctions Jb ₁ and Jb ₂ first and second junction diodes D ₁ and D
It differs in having _two .

The junction diodes D ₁ and D ₁
In _2, the gate electrode 8 of the first extraction electrode 10a and the transistor Tr2 of the junction diode D ₁ with electrical connection, the second extraction electrode 10 of the junction diode D ₂ of
a source electrode 7 of b and transistor Tr2 are electrically connected, as shown in an equivalent circuit diagram of FIG. 6, the junction diode D ₁ and D ₂ in the so-called Back-to back configuration. Also in this modification, each PN junction Jb ₁ and Jb ₁
The resistance of b ₂ is set smaller than the resistance of the PN junction Ja in the channel region 4 of the transistor Tr2.

According to this modification, the breakdown (breakdown) phenomenon of the transistor Tr2 due to the high potential can be avoided as in the first embodiment, and the transistor T
The high frequency characteristics of r2 itself can be effectively improved.

Next, the transistor is set to Dual gate
A second embodiment having a structure will be described with reference to FIGS. The components corresponding to those in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted.

The transistor Tr3 according to the second embodiment
Has almost the same structure as the modification of the first embodiment, but has two P-type high-concentration regions 5a and 5a in the channel region 4.
b is formed, and the first and second P
Differs in that it has a N junction Ja ₁ and Ja _2. Gate electrodes 8a and 8b are formed on each of the P-type high concentration regions 5a and 5b, respectively. Also, the lower the source electrode 7 to the low-resistance region 3, two P type high concentration region 9a and 9b are formed, according to the first and second PN junction Jb ₁ and Jb ₂ of the first and second Junction diodes D ₁ and D ₂ are formed.

The junction diodes D ₁ and D ₁
In _2, the a first extraction electrode 10a of the junction diode D ₁ and the first gate electrode 8a is electrically connected, and a second extraction electrode 10b of the junction diode D ₂ and the second gate electrode 8b Make an electrical connection. Again, each P
The resistance of the N junctions Jb ₁ and Jb ₂ is set smaller than the resistance of the PN junctions Ja ₁ and Ja ₂ in the channel region 4 of the transistor Tr2.

According to the second embodiment, similarly to the first embodiment, the breakdown (breakdown) of the transistor Tr3 due to the high potential can be avoided, and the high-frequency characteristics of the transistor Tr3 itself can be effectively improved. Can be done.

Next, a modification of the second embodiment in which the junction diode has a so-called back-to-back structure will be described with reference to FIGS. 9 and 10. FIG. Components corresponding to those in FIG. 7 are denoted by the same reference numerals, and description thereof is omitted.

The transistor Tr4 according to this modification is
It has substantially the same configuration as that of the second embodiment, except that four P-type high-concentration regions 9a to 9
9d is formed, the first to fourth PN junction Jb ₁ ~Jb
_{4 in that} first to fourth junction diodes D _{1 to} D ₄ are formed. FIG. 10 shows an equivalent circuit thereof.

The junction diodes D _{1 to} D ₄
Among, the a first extraction electrode 10a of the junction diode D ₁ and the first gate electrode 8a is electrically connected, the third
Junction diode connects the extraction electrode 10c and the second gate electrode 8b of the D ₃ electrically, and each extraction electrode 10b and one of the second and fourth junction diode D ₂ and D ₄ of the
Od is electrically connected to the source electrode 7. These first
The second and third junction diodes D ₁ and D ₂ and the third and fourth junction diodes D ₃ and D ₄ have a back-to-back structure as in the second embodiment. Also in variation is set to be smaller than the resistance the PN junction Jb ₁ ～Jb PN junction Ja ₁ resistor of the transistor Tr4 in the channel region 4 of the first and second ₄ and Ja _2.

According to this modification, similarly to the first embodiment, the breakdown (breakdown) phenomenon of the transistor Tr3 due to the high potential can be avoided, and the transistor T3
The high frequency characteristics of r3 itself can be effectively improved.

[0039]

According to the junction field effect transistor of the present invention, the characteristics (high-frequency characteristics) of the transistor can be obtained without reducing the reliability and life of the transistor.
Can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a configuration of a junction field effect transistor according to a first embodiment, for example, an N-channel Schottky (barrier) gate field effect transistor (hereinafter simply referred to as a transistor) made of GaAs.

FIG. 2 is an equivalent circuit diagram of the transistor according to the first embodiment.

FIG. 3 is a characteristic diagram showing a reverse breakdown voltage characteristic of the transistor according to the first embodiment.

FIG. 4 is a characteristic diagram showing a reverse breakdown voltage characteristic when the junction diode has a high resistance in the transistor according to the first embodiment.

FIG. 5 is a cross-sectional view illustrating a configuration of a transistor according to a modification of the first embodiment.

FIG. 6 is an equivalent circuit diagram of a transistor according to a modification of the first embodiment.

FIG. 7 is a cross-sectional view illustrating a configuration of a transistor according to a second embodiment.

FIG. 8 is an equivalent circuit diagram of a transistor according to a second embodiment.

FIG. 9 is a cross-sectional view illustrating a configuration of a transistor according to a modification of the second embodiment.

FIG. 10 is an equivalent circuit diagram of a transistor according to a modification of the second embodiment.

FIG. 11 is a cross-sectional view illustrating a structure of a transistor according to a conventional example.

FIG. 12 is an equivalent circuit diagram of a transistor according to a conventional example.

[Explanation of symbols]

 Tr1, Tr2, Tr3, Tr4 Transistor D junction diode 1 Semi-insulating GaAs substrate 2, 3 Low resistance region 4 Channel region 5, 9 P type high concentration region 6 Drain electrode 7 Source electrode 8 Gate electrode 10 Extraction electrode

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-27534 (JP, A) JP-A-4-335536 (JP, A) JP-A-60-47470 (JP, A) JP-A-4- 12536 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 21/337 H01L 29/808 H01L 29/812

Claims (5)

(57) [Claims] 1. A junction field-effect transistor in which a drain electrode and a source electrode are provided on a low-resistance region formed on a substrate surface, and a gate electrode is provided on a channel region having a PN junction. A junction type field effect transistor, wherein at least one junction diode is formed in a low resistance region below the electrode, and an extraction electrode of the junction diode and the gate electrode are electrically connected. 2. A first and a second junction diode are formed in a low-resistance region below the source electrode, and an extraction electrode of the first junction diode and the gate electrode are electrically connected. 2. The junction field effect transistor according to claim 1, wherein an extraction electrode of the second junction diode and the source electrode are electrically connected. 3. A drain electrode and a source electrode are respectively provided on a low-resistance region formed on a substrate surface, and a first and a second electrode are provided on a channel region having first and second PN junctions.
In the junction type field effect transistor provided with the gate electrode, first and second junction diodes are formed in the low-resistance region below the source electrode, and the extraction electrode of the first junction diode and the first Is electrically connected to the extraction electrode of the second junction diode and the second junction diode.
And a gate electrode of the junction field-effect transistor. 4. The method according to claim 1, further comprising:
A fourth junction diode is formed, the extraction electrode of the first junction diode is electrically connected to the first gate electrode, and the extraction electrode of the third junction diode is connected to the second gate electrode.
4. The junction field effect according to claim 3, wherein the gate electrode of the second junction diode is electrically connected to each of the extraction electrodes of the second and fourth junction diodes and the source electrode. Transistor. 5. The junction field effect transistor according to claim 1, wherein a resistance of a PN junction constituting said junction diode is smaller than a resistance of a PN junction in said channel region.