JP2762919B2 - Semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a Schottky barrier field effect transistor (hereinafter referred to as ME).
SFET).

[0002]

2. Description of the Related Art A technique using a protection diode to protect a MESFET used in an input stage from an input surge voltage is disclosed in, for example, JP-A-63-81845 and JP-A-62-213175. I have.

FIG. 5 shows an example. MESFET61
Is connected to an input node 64 that supplies an input signal V _IN , and a drain D supplies a first power supply voltage V _DD .
Source S is connected to the second power supply voltage V
It is connected to a second power supply node 66 that supplies _SS . First
The protection diode 62 has a cathode connected to the first power supply node 65.
And the anode is connected to the input node 64 in a reverse bias state. The second protection diode 63 has a cathode connected to the input node 64 and an anode connected to the second power supply node 6.
6 is in a reverse bias state. Therefore, when an abnormal surge voltage higher than V _DD + V _f (V _f is a forward voltage of the first protection diode) is applied to the input node 64, the first protection diode 62 enters a forward state and turns on. On the other hand, when an abnormal surge voltage (absolute value is higher) lower than V _SS −V _f (V _f is a forward voltage of the second protection diode) is applied to the input node 64, the second protection diode 63 is turned on. This prevents the abnormal surge voltage from being applied to the gate G, thereby protecting the MESFET 61.

On the other hand, apart from the abnormal surge voltage applied to the input node, the output used as a high-output amplifier is 50
In the case of a high-output MESFET of 0 mV or more, the gate breakdown voltage becomes a problem even when the voltage between the gate and the drain is near the upper limit of the range of the normal use state.

Referring to FIG. 4, a semi-insulating G
n is formed on the GaAs substrate 51 via the GaAs buffer layer 52.
In a MESFET in which an operation layer 53 of type GaAs is formed, a source electrode 55 and a drain electrode 56 are ohmically connected to the operation layer 53, and a gate electrode 57 is Schottky connected to the bottom surface of the recess 54 formed in the operation layer 53. When the potential difference between the gate electrode 57 and the drain electrode 56 is increased to, for example, 20 V, a high electric field is generated at the region 60 surrounded by the circle in FIG. 4, that is, at the end of the gate electrode on the drain side, and sometimes avalanche multiplication occurs. It will be in the state that caused it. If such a high electric field is applied to the end of the gate electrode and held for a long time, the semiconductor crystallinity at the end is gradually deteriorated, and eventually the MESFET is destroyed due to poor gate breakdown voltage or the like.

As a countermeasure, a method is conceivable in which a diode is connected in the reverse direction between the gate and the drain to utilize the breakdown. That is, although the purpose of use is different, a diode such as the first protection diode 62 of FIG.
Just before V, the diode is broken down by its reverse characteristics. This diode thus acts as a kind of limiter.

[0007]

However, in order to improve the degree of integration and to simplify the manufacturing process, the above-mentioned diode is used in ME.
When a Schottky barrier diode (hereinafter, referred to as SBD) is formed on the operation layer of the SFET, the MESFET
A high electric field is generated at the end of the anode electrode of the SBD as in the case of the gate electrode. As a result, the degradation life of the SBD is also shortened, and a significant improvement in the life of the entire device cannot be expected.

On the other hand, if the area of the end of the anode electrode of the SBD is increased to reduce the high electric field, the life of the SBD is improved, but the total contact area of the anode electrode is inevitably reduced.
For example, the gate width (channel length) is 1 μm, and the gate length is 5
Since the size is increased to 10 μm × 50 μm with respect to the MESFET of mm, the parasitic capacitance of the SBD is increased to, for example, 0.6 pF, and the high frequency characteristics are sacrificed.

Accordingly, an object of the present invention is to extend the life of an SBD itself for preventing destruction due to a gate breakdown voltage failure of a MESFET without sacrificing high frequency characteristics,
Accordingly, it is an object of the present invention to provide a semiconductor device having improved reliability.

[0010]

The features of the present invention include a substrate,
For example, in a semiconductor element in which a MESFET is formed in a first region of an operation layer provided on a semi-insulating GaAs substrate, for example, an n-type GaAs layer, an SBD is formed in a second region of the operation layer which is thicker than the first region. Forming an anode electrode, connecting the anode electrode to the gate electrode of the MESFET ,
One operating layer has a third region having the same thickness as that of the first region, and the third region has a semiconductor element in which a cathode electrode of SBD is formed. Alternatively, the upper surface of the second region of the operation layer has a semiconductor element having a shape protruding from the upper surface of the first region.
In the child. Here, the thickness of the first region is the thickness of the portion where the source electrode and the drain electrode of the MESFET are formed. And a first electrode between the source electrode and the drain electrode.
A recess is formed in the region, and a gate electrode can be formed on the bottom surface of the recess.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is a plan view showing a layout thereof.

First, as shown in FIG.
A 500 nm-thick GaAs buffer layer 1 is formed on an aAs substrate 11 by MBE (molecular beam epitaxy).
2 to grow and subsequently form the working layer 13
N having a thickness of 500 nm and a silicon concentration of 1 × 10 ¹⁷ cm ^-3
A type GaAs layer 13 is grown. Next, wet etching is performed to remove the region 28 to a thickness of 300 nm. Next, oxygen ions are implanted into regions other than the operation layer 13 to increase the resistance. Thereby, the first film having a thickness (T ₂ ) of 300 nm is formed.
Region 19, the second region 2 having a thickness (T ₃ ) of 500 nm
An N-type GaAs operation layer 13 having a third region 29 having a thickness of 8 and a thickness (T ₂ ) of 300 nm is formed by being surrounded by a high-resistance region (field region) 25 unnecessary for operation.

Next, as shown in FIG. 1B, the vicinity of the gate region of the first region 19 is etched to a depth of 100%.
An nm recess portion 14 is formed. Therefore, recess 1
4 having a thickness (T _1), namely a bottom (upper surface) thickness of the operation layer beneath the recesses 14 (T ₁₎ becomes 200 nm.

Next, aluminum is deposited and patterned by a vapor deposition method. Thereby, the first region 1 of the operation layer 13
9, the gate electrode 17 of the MESFET 30 connected to the bottom (upper) portion 17 ′ of the recess portion 14 by Schottky connection;
And an anode 21 of the SBD 40 connected to the upper surface 21 ′ of the second region 28 of the operation layer 13 by Schottky connection, and the gate electrode 17 and the anode 21 are connected to the high resistance region 25 by extending over the high resistance region 25. To form an aluminum pattern. And this aluminum pattern is the input voltage (V _IN )
Is connected to the input node or input terminal.

Next, AuGe-Ni is deposited by an evaporation method and patterned. As a result, the ME that is ohmic-connected to the surface portion 15 ′ in the first region 19 of the operation layer 13 is formed.
An AuGe-Ni pattern of the source electrode 15 of the SFET 30 is formed. The pattern of the source electrode 15 is coupled to the node or terminal of low power supply voltage V _SS side.

Further, the surface portion 1 in the first region 19 of the operation layer 13 is formed by the patterning of AuGe-Ni.
A drain electrode 16 of the MESFET 30 that is ohmic-connected to 6 'and a cathode electrode 22 of the SBD 40 that is ohmic-connected to the surface portion 22' in the third region 29 of the operation layer 13, and the drain electrode 16 and the cathode electrode 22 are connected to each other. An AuGe-Ni pattern extending over the high resistance region 25 and connected is formed. The patterns of the cathode electrode 22 and the drain electrode 16 are connected to nodes or terminals on the high power supply voltage _VDD side.

A high-concentration n ⁺ surface layer may be formed as a part of the operation layer on the surface portions 15 ′, 16 ′, and 22 ′ of the operation layer to be ohmic-connected.

In FIG. 1 and FIG. 2, the aluminum pattern is indicated by two pairs of solid lines with a pair of lines descending to the right.
The e-Ni pattern is indicated by solid lines hatched to the left. In these figures, illustration of each interlayer insulating film is omitted.

The source-drain electrodes 15 of FIG.
3, three recess portions 14 extending in the vertical direction in FIG. 2 are formed, and three gate electrodes 17 are formed.
Are formed in the respective recessed portions, but illustration of the recessed portions is omitted in FIG.

The thickness T ₁ of the recessed portion 14 formed in the first region 19 having a thickness (T ₂₎ In this embodiment MES
This is an important factor for designing the characteristics of the FET 30, particularly the drain saturation current. Therefore, the thick T
The film thickness T ₁ of the recessed portion 14 is etched from the state of ₃ by etching.
Is difficult to obtain with good controllability. Therefore, as in the present embodiment, after the first region 19 having the thickness T ₂ for forming the source and drain electrodes 15 and 16 is formed by etching, the actually formed thickness T ₂ is measured and measured. It is necessary to determine the etching conditions for forming the recessed portion based on this. That is, for example, when the thickness T ₂ of the first region 19 is 300 nm in the design value but the measured value is 290 nm, the thickness T ₂ of the recessed portion 14 is removed by etching by a depth of 90 nm from the surface. ₁ is 200 nm as designed
Control so that

On the other hand, the film thickness T ₂ of the first region 19 affects the source resistance and the drain resistance, but does not have a primary influence on the characteristics of the MISFET 30 like the film thickness T ₁ of the recess portion 14. But the result inconvenience likely surge current flows to reduce the drain resistance when forming the drain electrode 16 to the thick film thickness T ₃ locations. Therefore it is not possible to form a drain electrode 16 to the large thickness T ₃ so as to form the anode electrode 21 of SBD40.

When an anode electrode is formed on a thin operating layer, arc-shaped equipotential lines are formed around the end of the anode electrode facing the cathode electrode, and a strong electric field region is formed at this end to cause destruction. Leads to. However, when the anode electrode is formed on a thick operating layer, it becomes an equipotential line extending in parallel under the anode electrode, and a uniformly relaxed electric field region is formed under the lower surface of the anode electrode to avoid a destruction phenomenon. Can be.

Further, in this embodiment, since the cathode electrode is located below the anode electrode, the electric field is more evenly distributed, and the concentration phenomenon can be further alleviated. However, the design can be formed on region 28 of a thick T ₃ of the operating layer of the cathode electrode like the anode electrode.

As described above, since the thickness of the operating layer below the gate electrode of the MESFET determines the characteristics of the MESFET, there is a restriction in increasing the thickness. However, MESFE
Since the thickness of the operating layer under the anode electrode of the SBD for preventing T from destruction does not have the above-described restrictions, the thickness can be increased in consideration of avoidance of destruction due to electric field concentration of the SBD itself.

In this embodiment, the difference between the thickness T ₂ of the first region forming the MISFET of the operation layer and the thickness T ₃ of the second region forming the anode electrode of the SBD was 200 nm. For the effects of the present invention can be obtained remarkably in the actual semiconductor device is the difference between the thickness T ₃ of the second region for forming the anode electrode of the _second thickness T ₂ and SBD of the first region 100n
m or more, and considering the manufacturing process and the like, the difference is preferably 400 nm or less.

As a result, it is not necessary to increase the area of the anode electrode of the SBD, so that the parasitic capacitance can be suppressed and the high frequency characteristics of the semiconductor element are not sacrificed.

The semiconductor device according to the first embodiment has a frequency of 4
A test was performed in which the device was operated for a long time at GHz. The test conditions are
V _DS (source-drain voltage) = 12 V, T _a (ambient temperature) = 200 ° C., a forced life test in which an excessive input was applied until the gain was reduced to −5 dB, and the number of samples was 10. Was.

As a result, it has been found that the deterioration life time until the output is reduced by 0.2 dB is improved by one digit or more compared to the MESFET in which the protection SBD is not coupled under the same conditions. It was confirmed that the semiconductor element had no practical problem.

FIG. 3 is a sectional view showing a semiconductor device related to the present invention. Note that, in FIG. 3, portions having the same or similar functions as those in FIG. 1 are denoted by the same reference numerals, and duplicate description will be omitted.

FIG . 3 shows a case where the ion implantation method is used for forming the operation layer. That is, the semi-insulating GaAs substrate 1
An n layer 13 serving as an operation layer is formed from the surface of the substrate 1 by an ion implantation method. That is, the first region 19 of the operation layer 13 is formed by the first ion implantation, and the bottom portion 28 ′ is deeper than the bottom portion 19 ′ of the first region 19 by the second ion implantation of an acceleration voltage higher than that of the first ion implantation. Is formed adjacent to the first region 19. Here, both regions can be formed by controlling the dose so as to have the same impurity concentration. Then, similarly to the first embodiment, the MESFET 30 is provided in the first region 19 and the SB
D40 is provided. In this embodiment, the cathode electrode 22 of the SBD 40 is also formed on the same thick (deep) second n-layer as the anode electrode 21. In this embodiment, MESF
Since the source electrode 15 and the drain electrode 16 of the ET and the anode electrode 21 and the cathode 22 of the SBD are formed on the same flat surface, the overall flatness is improved and the upper electrode wiring can be formed with high reliability.

1 to 3 are MESFETs.
A case has been described in which a recess is provided in the first region of the operation layer in which the gate electrode is formed. However, it is also possible to apply to a MESFET in which the gate electrode is formed on the same flat upper surface as the source and drain electrodes without providing the recess.

[0033]

As described above, according to the present invention, the MESFET 30 is provided in the first region 19 of the operation layer 13 provided on the substrate 11.
Formed on the anode electrode 21 of the SBD 40 for preventing the MESFET 30 from being broken due to a gate breakdown voltage failure.
Formed in the second region 28 having a thickness (T ₃ ) larger than the thickness (T ₂ ) of the first region,
Of the SBD can be extended without increasing the area of the SBD, that is, without increasing the parasitic capacitance.

Therefore, the semiconductor device having the MESFET to which the protection SBD of the present invention is connected has excellent high-frequency characteristics and high reliability.

[Brief description of the drawings]

FIG. 1 shows an intermediate step of a semiconductor device according to an embodiment of the present invention.
That is a sectional view (A) and a cross-sectional view of the semiconductor device (B).

FIG. 2 is a plan view showing a layout according to an embodiment of the present invention.

FIG. 3 is a sectional view showing a semiconductor device related to the present invention.

FIG. 4 is a cross-sectional view showing a conventional MISFET.

FIG. 5 is a circuit diagram showing protection means for an abnormal surge input voltage.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Semi-insulating GaAs substrate 12 GaAs buffer layer 13 Operating layer of n-type GaAs layer 14 Recessed part 15 Source electrode 15 'Surface part where source electrode is ohmic connected 16 Drain electrode 16' Surface part where drain electrode is ohmic connected 17 Gate electrode 17 'Surface portion where gate electrode is Schottky connected 19 First region of operation layer 21 Anode electrode 21' Surface portion where anode electrode is Schottky connected 22 Cathode electrode 22 'Surface portion where cathode electrode is ohmic connected 25 High resistance region (Field region) 28 Second region of operation layer 29 Third region of operation layer 30 MESFET 40 SBD 51 Semi-insulating GaAs substrate 52 GaAs buffer layer 53 N-type GaAs operation layer 54 Recess portion 55 Source electrode 56 Drain electrode 57 Gate voltage Pole 60 Gate electrode end where high electric field is generated 61 MESFET 62 First protection diode 63 Second protection diode 64 Input node 65 First power supply node 66 Second power supply node

──────────────────────────────────────────────────続 き Continued on the front page (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095-27/098 H01L 29/775-29/778 H01L 29 / 80-29/812

Claims (5)

(57) [Claims] In a semiconductor device in which a Schottky barrier field effect transistor is formed in a first region of an operation layer provided on a substrate, a shot is formed in a second region of the operation layer that is thicker than the first region. Forming an anode electrode of a key barrier diode, connecting the anode electrode to a gate electrode of the transistor , and
A third region having the same thickness as that of the first region;
3. A semiconductor device wherein a cathode electrode of the diode is formed in a region of No. 3 . 2. The method according to claim 1 , wherein the first region of the operation layer provided on the substrate is
Semiconductors with Schottky barrier field-effect transistors
In the body element, the movement is greater than the thickness of the first region.
In the second region of the layer, the Schottky barrier diode
Forming a node electrode, and forming the anode electrode
The upper surface of the second region protrudes from the upper surface of the first region
A semiconductor element characterized in that: 3. The thickness of the first region is a thickness of a portion where a source electrode and a drain electrode of the transistor are formed, and a thickness of the first region between the source electrode and the drain electrode. 3. The semiconductor device according to claim 1, wherein a recess is formed in the semiconductor device, and the gate electrode is formed on a bottom surface of the recess. Wherein said substrate is a semi-insulating GaAs substrate, a semiconductor device according to claim 1 or claim 2, wherein the active layer is an n-type GaAs layer. 5. The semiconductor device according to claim 4, wherein said n-type GaAs layer is formed on said semi-insulating GaAs substrate via a buffer layer.