JPH0244776A - Insulated gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To secure breakdown strength in the reverse direction by providing low impurity concentration which is determined by the desired breakdown strength in the reverse direction in a region into which carriers flow from an emitter electrode through a channel, forming a direct junction between said region and a reverse conductivity type collector layer, extending the collector layer to the surface at the opposite side, and providing a planar structure. CONSTITUTION:A low impurity concentration N-type Si substrate 2 corresponding to expected withstand voltage is used. A P<+> layer 1 is formed by impurity diffusion from one surface. A P<+> layer 11 is formed at a peripheral part other than an area based on the current capacity of an element by impurity diffusion using a mask from the other surface. Then, a P<+> layer 32 is thinly formed on the surface layer of the N<-> layer 2 at the lower parts of parts where an emitter layer and a channel layer are formed. An N<-> layer 20 is further laminated on said substrate. Thereafter, a P<+> layer 31 which reaches the P<+> layer 32 and whose lateral expansion is smaller and a P<+> layer 12 reaching the P<+> layer 11 are formed at the same time by impurity diffusion. A P-channel layer 3 is formed on the surface part. An N<+> emitter layer 4 is formed on a part of the layer 3. Thus the desired value of breakdown strength can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for converting the base current of a bipolar transistor into MO
The present invention relates to an insulated gate bipolar transistor supplied from an SFET in which current does not flow in the reverse direction.

[Conventional technology]

In recent years, insulated gate bipolar transistors (I
GBT (abbreviated as GBT) has a small voltage drop when used at high voltage (compared to MOS FET), and can be controlled by voltage compared to bipolar transistors, and has a substantial amplification factor. The N-channel IGBT is being put into practical use as a high-voltage switching device due to its ability to increase the An N-layer 2 with a low impurity concentration is formed, a second layer 3 is selectively formed on the surface of this N-layer 2, an N'''' emitter layer 4 is further selectively formed on this surface, and the second layer 3 is formed. The surface region sandwiched between the N− layer 2 and the N′ layer 4 is used as a channel formation region, and a gate electrode 6 is formed thereon via gate oxidation wj!5. An emitter electrode 7 is placed across the deep P'' layer 31 formed on the side and the N+ emitter layer 4, and the collector electrode 8 of the P'' layer 1 is brought into contact with the emitter electrode 7.

[Problem to be solved by the invention]

Generally reported IGBTs tend to cause latching when the current exceeds a certain level, so various methods have been proposed to prevent latching.

For example, in FIG. 2, the P' collector layer 1 and the emitter electrode contact the P' layer 31. N” between the emitter layer 4 and
The - layer 2 has a large effect on the withstand voltage, but in order to prevent latching, the N0 layer 21 is formed by increasing the concentration of the part of the N- layer 2 that is in contact with the P collector 111. This is effective in preventing latching by reducing the injection of holes from the 20 layer 1 during conduction, and is generally put into practical use.

However, in such a structure, when the collector potential is negative with respect to the emitter potential and the emitter-collector is in a reverse voltage state, a reverse voltage is applied to the N"P" layer, and the N"layer The higher the concentration of 21, the lower the reverse withstand voltage. In general IGBT application circuits, there are many applications in which it is desired to block current even when a reverse voltage is applied, and there has been a demand for IGBTs with high reverse withstand voltage.

The object of the present invention is to meet the demands of the market by creating an I/O device that has a high reverse withstand voltage and at the same time prevents the latching phenomenon.
The goal is to provide GBT.

[Means to solve the problem]

In order to solve the above problems, the IGBT of the present invention includes a first conductivity type layer having a low impurity concentration, one surface and a side surface of which are surrounded by a second conductivity type collector layer, and a first conductivity type layer having a low impurity concentration. A channel layer of the second conductivity type is formed on a part of the surface layer of the other side, an emitter layer of the first conductivity type is formed on the surface layer of the channel layer, and the emitter layer of the channel layer and the outer layer of the first conductivity type are formed. A gate electrode is provided on a channel forming region between the two via a gate insulating film, the emitter electrode is in contact with the emitter layer and a high impurity concentration region of the same conductivity type as the channel layer interposed therebetween, and the emitter electrode is a high impurity concentration region of a second conductivity type with the same extent as the channel layer existing under the channel layer via the layer of the first conductivity type; and a high impurity concentration region of the second conductivity type interposed between the emitter layer. It is assumed that they are connected by an impurity concentration region.

[Effect]

Only the first conductivity type layer with a low impurity concentration exists between the emitter electrode and the second conductivity type collector layer, and the collector layer reaches the surface on the side of the first conductivity type layer, resulting in a planar structure. Therefore, the reverse withstand voltage is high, and instead of the first conductivity type layer with high impurity concentration that reduces carrier injection from the collector layer, carriers injected from the collector layer exist under the channel layer. Carriers are absorbed into the emitter electrode from the intermediate region of the second conductivity type with a high impurity concentration through the region with a high impurity concentration in the channel layer, so carriers from the collector layer are not injected into the channel layer and lateral A latching phenomenon caused by the product of the resistance and the current due to injected carriers exceeding the diffusion potential between the emitter layer and the channel layer is prevented.

〔Example〕

Figure 1 (al, (bl) shows an embodiment of the present invention in a cross-sectional view and a plan view, and the same parts as in Figure 2 are given the same reference numerals. In this embodiment, N is used to prevent latching.

There is no layer 21, and the P' collector layer 1 and P' layers 11 and 12 surround the N- layer 2 and reach the surface where the emitter electrode 7 is provided, forming a Brenna type structure in which the PN junction is exposed on the surface. Further, below the channel Ji3, a P''1i32 having a lateral extent equal to or larger than that of the channel layer is provided across the N- layer 2, and is connected to the emitter ti7 via the P''N31.

3 fa+, (bl) and FIG. 4 fa+, (b) are explanatory diagrams of the manufacturing process of the IGBT shown in FIG. 29 by diffusion of impurities from the entire − surface (lower surface in the figure).
20 layers 11 are formed in the periphery of layer 1 except for an area based on the current capacity of the element by diffusing impurities using a mask in a photolithography process from the other surface (top surface in 1). In this case, the thickness of the N-layer 2 can be designed according to the impurity concentration and the spread of the depletion layer depending on the withstand voltage. 29 layers 32 are formed thinly. This 2
The thickness of the fourth layer 32 is determined from the amount of holes injected from the collector layer Pl and collected here, but - for boat fishing -
Figure 3 (
al, (shown in bl.

Furthermore, after laminating an N- layer 20 on this substrate by an epitaxial method or the like, impurity diffusion reaches a P layer 32 with a smaller width in the lateral direction.

Figure 4 (al, (b)
), thereafter, a P-type channel layer 3 is formed on the surface portion, and a N-type channel layer 4 is further formed on a portion thereof.

A plan view of this state is shown in FIG.
A gate electrode 6 is formed thereon, and an emitter electrode 7 is brought into contact with the opening of the gate oxide film 5, and a collector electrode 8 is brought into contact with the lower surface of the collector layer l, thereby completing the state shown in Figure 1+6). . In this case, the impurity concentration, channel length, etc. of the channel layer 3 can be designed in the same way as a general MOSFET (and appropriate electrical characteristics such as gate sensitivity can be provided as necessary).

What is important in such an IGBT is to collect the holes in the P layer 32 while minimizing the probability that the holes injected from the P° corelfta layer 1 will enter the channel layer 3 of the N'''' emitter layer 4. Therefore, it is preferable that the 20 layer 32 be made laterally equal to or slightly wider than the channel layer 3, and designed to increase the probability that electrons IO injected through the N channel will reach the collector layer 1. Since the structure is similar to that of a general planar diode, the reverse breakdown voltage can be set to a desired breakdown voltage value.

The principle of operation of this IGBT to prevent latching is as follows. Now, if a voltage that makes the collector positive is applied between the emitter terminal E and the collector terminal C, give the gate terminal G the positive potential necessary to form a channel with the emitter terminal E and make it conductive. As a result, electrons 10 from the N emitter layer 4 flow into the N-calendar 20 through the upper channel of the channel layer 3.The flowing electrons 10 pass through the N-layer 2 and reach the P collector with a certain probability, and at the same time It is injected from the layer 1 into the N- layer 2, and reaches the emitter electrode 7 through the layer 32 with a high probability. Some of the holes reach the channel layer 3, but the potential generated by the lateral resistance in the channel layer below the emitter layer 4 and the injected holes is
If the resistance is smaller than the diffusion resistance of the PN junction with the channel layer 3, latching does not occur.The effect of 0 or more is exactly the same in the P-channel ■GBT.

〔Effect of the invention〕

The present invention makes the region into which carriers flow from the emitter electrode of the IGBT through the channel a low impurity concentration determined by the desired reverse breakdown voltage, forms a direct junction with the collector layer of the opposite conductivity type, and connects the collector layer to the opposite side. By extending it to the surface of the channel layer to form a Brehner type structure, a reverse breakdown voltage is ensured. By forming a layer of the same conductivity type as the collector layer leading to the electrode, the injection into the channel layer is reduced and the latching phenomenon is prevented from occurring. This allows the reverse breakdown voltage to be higher than when a high impurity concentration layer is provided on the collector layer to prevent carrier injection, and because the amount of carrier injection from the collector side is increased, the voltage drop during conduction is reduced. It is also possible to do so.

[Brief explanation of the drawing]

FIG. 1 (al, (bl) is an IGBT of one embodiment of the present invention.
, ial is a cross-sectional view, mountain) is a plan view before forming an oxide film and an electrode, FIG. 2 is a cross-sectional view of a conventional IGBT, FIG. 3 (al, 11. Intermediate stages of the manufacturing process of the embodiment shown in the figures are sequentially shown, and fa+ (in the cross-sectional view) is a plan view. 1, 11.12: P" collector layer, 2.20: N
-layer, 3: P-type channel layer, 31.32 two P-layers, 4:
N emitter layer, 5: gate oxide film, 6: gate electrode,
Figure 4 Figure 1 Figure 2

Claims (1)

[Claims] 1) One and side surfaces of the layer of the first conductivity type with a low impurity concentration are surrounded by a collector layer of the second conductivity type, and a part of the surface layer on the other side of the layer of the first conductivity type is surrounded by a collector layer of the second conductivity type. A channel layer, an emitter layer of a first conductivity type is formed on the surface layer of the channel layer, and a gate insulating film is formed on the channel forming region between the emitter layer of the channel layer and the outer layer of the first conductivity type. A gate electrode is provided, the emitter electrode is in contact with the emitter layer and a high impurity concentration region of the same conductivity type as the channel layer interposed therebetween, and the emitter electrode is further disposed below the channel layer through the layer of the first conductivity type. an insulated gate connected by a second conductivity type high impurity concentration region having the same extent as a channel layer existing in the emitter layer and a second conductivity type high impurity concentration region interposed between the emitter layer. bipolar transistor.