JPH04180680A - Insulated-gate bipolar transistor - Google Patents

Abstract

PURPOSE:To shorten the switching time without raising an ON voltage by a method wherein a drain electrode which forms a Schottky barrier and which is composed of molybdenum is brought into contact with an n<+> layer and a p<+> layer. CONSTITUTION:An n<-> layer 3 (a first region) is laminated on an n<+> layer 4 (a fourth region) by, e.g. an epitaxial method; after that, a gate oxide film 6 and a gate electrode 7 are formed on its surface. Then, ions to form a p<+> layer 4 (a second region) are implanted by using a mask for patterning use at that time. Ions to form a p<+> layer 1 (a fifth region) are implanted from a face on the opposite side; the layer 1 and the layer 4 are formed simultaneously by a thermal diffusion operation and after that, an n<+> layer 5 (a third region) is formed. An insulating film 8 and a source electrode 9 are formed; after that, a drain electrode 11 which forms a Schottky barrier and which is composed of molybdenum is brought into contact with the layer 2 and the layer 1. Thereby, the switching time can be shortened without raising an ON current.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT) in which the base current of a wide base bipolar transistor is supplied by a built-in MOSFET.
Regarding.

[Conventional technology]

IGBTs are beginning to be commonly used as power switching elements that can be driven by voltage. The most commonly used type is the n-channel type IGBT1, which can be said to be an n-channel vertical MOS FET +;) with a p'' layer added to the drain electrode side of the drain region. It has a structure as shown in Fig. 2.This structure can be formed as follows: 2 layers of low resistivity are laminated on a p-substrate 21, and a high resistivity n layer is further layered on top of that. - layer 3 is laminated. A p layer 4 is selectively formed on the surface of this n- layer 3, and a D" layer is selectively formed on the surface of this p layer 4.
form 5. Then, the n− layer 3 of the p° layer 4 and the n
- The region sandwiched between the regions 5 is used as a channel region, and a gate electrode 7 connected to the gate terminal G via the gate insulating film 6 is formed thereon. A source electrode 9 is formed between the gate electrode 7 and the p'' layer 4 and the n'' layer 5 through an insulating film 8, and a drain electrode 1 is formed on the surface of the p'' substrate l.
Place 0. A source terminal S is connected to the source electrode 9, and a drain terminal S is connected to the drain electrode 10.

In this device, when the source electrode 9 is grounded and a positive voltage is applied to the gate electrode 7 and the drain electrode 0, the n' layer 2 is the drain, the n' layer 5 is the source, and the p' layer 4 is the drain.
A MOSFET configured by providing a gate electrode 7 on the gate insulating film 6 via the gate insulating film 6 is turned on, and electrons flow into the n- layer 3 via the channel region of the p° layer. In response to this inflow of electrons, the p-substrate 21 to the n-layer 3
Holes are injected into the n-layer 3, causing conductivity modulation in the n-layer 3, thereby lowering the resistance in this region.

[Problem to be solved by the invention]

However, in the above-mentioned conventional IGBT, although the on-voltage is small, even if electrons are swept toward the drain electrode lO side during off-state, holes are injected from the p layer 21, so that n
- There is a problem that the reduction of holes, which are minority carriers, existing in the layer 3 does not progress, and the switching time is long. To solve this problem, there are methods to increase the recombination rate of electrons and genuine bills by irradiating the element with an electron beam or by diffusing gold. However, when these methods are executed, IGBT
The on-voltage becomes higher. That is, there is a trade-off relationship between on-voltage and switching time, and it is extremely difficult to improve both characteristics at the same time.

SUMMARY OF THE INVENTION An object of the present invention is to provide an IGBT that can shorten the switching time without increasing the on-voltage in view of the problems of the prior art described above.

[Means to solve the problem]

In order to achieve the above objects, the present invention provides a first region of a first conductivity type, a second region of a second conductivity type selectively formed on the surface of one side of the first region, and a A third region of the first conductivity type with a high impurity concentration selectively formed on the surface portion, a fourth region of the first conductivity type with a high impurity concentration adjacent to the other side of the first region, and a surface portion of the fourth region. a fifth region of a second conductivity type selectively formed in the second conductivity type; a gate electrode provided on a portion of the surface of the second region sandwiched between the first region and the third region via a gate insulating film; A source electrode that simultaneously contacts the second region surface and the third region surface, and a drain electrode that simultaneously contacts the fourth region surface and the fifth region surface and forms a Schottky barrier between the fourth region. do.

[Effect]

The channel region is formed by using the portion of the second region of the first conductivity type sandwiched between the first region and the third region of the second conductivity type as a channel region, and providing a gate electrode thereon via a gate insulating film. The carriers supplied from the MOSFET enter the fourth region, but they are even cut off by the Nyoyoto key carrier between the drain electrode and flow along the junction between the fourth region and the fifth region. A potential difference occurs between the five regions,
Minority carrier injection occurs from the fifth region through the fourth region into the first region. As a result, conductivity modulation occurs as in conventional IGBTs, and the on-state voltage decreases. On the other hand, at turn-off, the junction between the first region and the second region is reverse biased, which expands the depletion layer, and the extruded majority carriers are directly transferred from the fourth region by a much higher voltage than the Nyoyotky barrier. It is swept out to the drain electrode.

At this time, minority carriers are not injected from the drain electrode, and the minority carriers that have been present are swept out of the source electrode, so the number of carriers in the first region decreases and the switching time becomes shorter.

〔Example〕

FIG. 1 shows the structure of an IGET according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. Second
Unlike the figure, the P' substrate 21 is not present, and the P' layer 1 is formed on the surface of the N4 layer 2.

This IGBT is manufactured in the following steps.

First, the n- layer 3 (first region) is laminated on the n° substrate 2 (fourth region) by, for example, the Evita Kinyal method.

Next, after forming an oxide film 6 (gate insulating film) on the upper surface, a gate electrode 7 is further formed, and a patterning mask is used at that time to form a p- layer 4 (second region). Perform ion implantation. Also, from the opposite surface, p layer 1
Ion implantation is performed to form a fifth region). Then, p' layer 1 and p' layer 4 are simultaneously formed by thermal diffusion. Further, by ion implantation and thermal diffusion using the gate electrode 7 as a mask, a third region of the n layer 5) is formed. Next, an insulating film 8 is formed, and a source electrode 9 is formed from the surface of the insulating film 8 to the surfaces of the p layer 4 and the n+ layer 5 using, for example, aluminum (A!).Finally, the n layer 2 and the Schottky barrier are formed. This device is completed by bringing the formed drain electrode 11 made of molybdenum (MO) into contact with the n° layer 2 and the p′ layer 1.

Note that the device of this example was irradiated with an electron beam for the purpose of increasing the recombination rate.

When the turn-off time of the IGBT manufactured in this way was measured, it was 07 μsec. On the other hand,
When the IGBT of the conventional structure shown in FIG. 2 was irradiated with an electron beam, the turn-off time was 079 μsec. The on-voltages of both were almost equal. Furthermore, the turn-off time of the IGBT of another embodiment in which gold is diffused in the structure shown in FIG. 1 is 0.
．． 67 μsec, whereas the I of the structure shown in Figure 2
Turn-off time of gold diffused into GBT is 0.82
It was μsec. There was no difference in on-voltage. Note that the turn-off time was defined as the time from when the gate became Ov when an inductive load was connected until the drain current decreased to 10% of the on steady state.

Although the above embodiment is an n-channel type IGBT, it can be implemented similarly to a p-channel type IGBT in which the n-type and p-type are completely replaced.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a layer of the second conductivity type is provided on the entire surface of the drain electrode side opposite to the side where the MO3 structure is provided in the layer of the first conductivity type of the conventional IGBT. By forming a Schottky barrier between the drain electrode and the first conductivity type layer instead, carriers that cause conductivity modulation are injected when on, but when off, the carriers are injected. We were able to prevent this injection from occurring. As a result, the IGB has shortened switching time without increasing on-voltage.
I was able to get T.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an IGBT according to an embodiment of the present invention, and FIG. 2 is a sectional view of an IGBT having a conventional structure. 1-P+ layer, 2-n'' layer, 3-n- layer, 4-P'' layer,
5-n+ layer, 6° gate oxide film, ? - gate electrode, 9
source electrode, l l-Mo electrode (drain electrode). Figure 1

Claims (1)

[Claims] 1) A first region of the first conductivity type, a second region of the second conductivity type selectively formed on the surface of one side of the first region, and a second region of the second conductivity type selectively formed on the surface of the second region. a third region of the first conductivity type with a high impurity concentration formed on the other side of the first region; a fourth region of the first conductivity type with a high impurity concentration adjacent to the other side of the first region; a fifth region of the second conductivity type formed, a gate electrode provided via a gate insulating film on a portion of the surface of the second region sandwiched between the first region and the third region, and a surface of the second region. and a drain electrode that simultaneously contacts the surfaces of the fourth region and the fifth region and forms a Schottky barrier between the fourth region and the fourth region. Gate type bipolar transistor. 2) The insulated gate bipolar transistor according to claim 1, wherein a molybdenum metal film is used as a drain electrode forming a Schottky barrier. 3) The insulated gate bipolar transistor according to claim 1 or 2, wherein electron beam irradiation is performed to increase the recombination rate of carriers in the first region of the first conductivity type. manufacturing method.