JP3247461B2 - Semiconductor device and manufacturing method thereof, MOS gate drive type thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MOS gate drive type thyristor which can be turned on and off by a MOS gate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A MOS gate drive type thyristor (hereinafter, referred to as a thyristor)
MCT (MOS gate Controlled Thyristor)
Is a thyristor that turns on when a voltage is applied to the gate electrode and the emitter and base having the same conductivity type are short-circuited by a MOS gate type transistor.
This operation requires little gate power because it is voltage controlled. Further, since the self-turn-off cannot be performed only by this configuration, a control electrode is provided on an emitter having a conductivity type opposite to that of the base, and a negative bias is applied to the control electrode to reduce the anodic current. MOS that self-turns off by discharging the part as a base current to the outside
Type thyristors are known. An example of a conventional MCT is shown in FIG. 34 (1991, IEEE 138 to 141).
page). The figure is a perspective view of the MCT. On the first main surface of the N ^- silicon semiconductor substrate 1, impurities are diffused to form a P-type base region 2 and a P ⁺ drain region 4, and the P-type base region 2 further includes an N-type base region. An emitter region 3 is formed.
On the second main surface of the semiconductor substrate 1, that is, on the back surface, semiconductor layers are sequentially stacked and grown to form an N ⁺ layer 5 and a P ⁺ layer 6.
These are a buffer region and a back surface P ⁺ emitter region, respectively. Then, an anode electrode 10 (A) is formed on the back surface P ⁺ emitter region 6. On the other hand, on the first main surface side, N
^A gate oxide film 7 is formed so as to cover the silicon semiconductor substrate 1, the P-type base region 2, the N-type emitter region 3 and the P ⁺ drain region 4; On this gate oxide film 7, a polysilicon gate electrode 8 (G) is formed. Then, the gate oxide film 7 and the gate electrode 8 are partially removed, and a cathode electrode 9 (K) is formed on the N emitter region 3 and the P ⁺ drain region 4 at the opened portions.

The operation principle (turn-off / turn-on) of such a conventional MCT will be described. First,
The turn-on operation will be described with reference to FIGS. A positive voltage is applied to the gate G with the anode A positively biased and the cathode K negatively biased, and the semiconductor substrate (N ^- base region) 1, the P-type base region 2 and the N-type emitter region 3 The inversion layer 11 is formed by operating the configured N-channel MOSFET, and the N ⁻
The electrons 12 are injected into the base region 1 (FIG. 35). N ^- N from the rear surface P ⁺ emitter region 6 by the injection of electrons into the base region 1 ^- hole 13 into the base region 1 are injected to turn on device by causing conductivity modulation, the main current 14
Flows (FIG. 36). Next, the turn-off operation will be described with reference to FIGS. The anode A is positive, the cathode K is negatively biased, a negative bias to the gate G in a state in which the main current 14 is flowing, N ^-
An inversion layer 15 is formed by operating a P-channel MOSFET comprising a base region 1, a P-type base region 2 and a P ⁺ drain region 4. Thereby, the P-type base region 2,
The P ⁺ drain region 4 and the cathode electrode 9 are short-circuited, and the holes 16 in the main current are discharged from this path. When holes in the main current are discharged, injection of electrons from the N-type emitter region 3 stops, and the main current 14 stops flowing. This completes the turn-off operation. The MCT is a self-extinguishing element capable of performing the above-described turn-on / turn-off operation.

[0004]

Since the MCT is an element which is turned on due to its operating characteristics, it has a problem that it is difficult to turn off the MCT. At present, the MCT is being developed to improve the turn-off characteristics. In this structure, it is necessary to increase the concentrations of the P-type base region 2 and the P ⁺ drain region 4 in order to improve the turn-off characteristics. That is, in the turn-off operation as shown in FIGS. 37 and 38, holes are generated from the main current by the inversion layer 15 formed by the operation of the P-channel MOSFET to the cathode electrode 9.
The hole discharge efficiency when discharging to the P-type base region 2
And the sheet resistance of the P ⁺ drain region 4. Therefore, in order to improve the hole discharge efficiency, it is necessary to increase the concentrations of the P-type base region 2 and the P ⁺ drain region 4 and reduce the sheet resistance. However, when the turn-off structure is prioritized and the concentration of the P-type base region 2 is increased, the turn-on characteristics are deteriorated. That is, in the turn-on operation shown in FIG. 35, the N-channel MOSFET is operated to form the inversion layer 11, electrons are injected from the N-type emitter region 3 to the N ⁻ base region 1, the conductivity is modulated, and the main current is reduced. When flowing
When the concentration of the P-type base region 2 increases, the N-channel MOS
This causes an increase in the threshold voltage of the FET, an increase in the on-voltage when the main current flows, and an increase in the turn-on loss. As described above, there is a reciprocal relation between the improvement of the turn-on and turn-off characteristics of the MCT, and if one of the characteristics is improved, the other characteristics are deteriorated, and the trade-off between the turn-on and the turn-off is difficult. There was a problem that it was difficult to improve. As a conventional MCT, there is a technique disclosed in JP-A-63-310171. This means that the conventional five-layer structure is pn
Although a pn four-layer structure is used to simplify the manufacturing process and reduce the short-circuit resistance of the emitter to enable high-speed turn-off, the turn-off and turn-on trade-offs described above are eliminated. The difficult problem has not been solved.

An object of the present invention is to provide a semiconductor device which improves the trade-off between the turn-on and turn-off characteristics and further improves the turn-off characteristics as compared with the conventional structure.

[0006]

According to the present invention, a second conductivity type base region having a lower impurity concentration than the second conductivity type base region is formed at an end of a second conductivity type base region of a unit element (unit cell) constituting an MCT. Thus, a turn-on initial operation region is provided, and the trade-off between the turn-on and turn-off characteristics is improved by increasing the turn-on efficiency. That is, the semiconductor device of the present invention comprises a first semiconductor region of a first conductivity type exposed on a first main surface of a semiconductor substrate, and a first semiconductor region formed on the first semiconductor region. A second semiconductor region of the second conductivity type exposed to the second semiconductor region; and a first semiconductor region formed in the second semiconductor region and exposed to the first main surface.
A third semiconductor region of a conductivity type, a fourth semiconductor region of a second conductivity type formed in the first semiconductor region and exposed on the first main surface, and formed in the first semiconductor region; And
A fifth semiconductor region of a second conductivity type exposed on a second main surface of the semiconductor substrate; and a first electrode electrically connected to the third semiconductor region and the fourth semiconductor region. And a gate oxide film formed on the first main surface of the semiconductor substrate via a gate oxide film, at least a boundary between the first and second semiconductor regions, a boundary between the first and fourth semiconductor regions, and An off-gate region which is a first region formed on the first semiconductor region sandwiched between these boundaries, and formed on the first main surface of the semiconductor substrate via the gate oxide film A boundary between the first and second semiconductor regions, a boundary between the third and second semiconductor regions, and a second region formed on the second semiconductor region sandwiched between these boundaries. A gate electrode having a gate region, and a second electrode formed on the fifth semiconductor region. Comprising a pole, said a second semiconductor region and the fourth semiconductor region, under the off-gate region, is characterized in that it is opposed through the first semiconductor region. The portion of the second semiconductor region formed under the second region of the gate electrode is a sixth semiconductor region, and the impurity concentration of the sixth semiconductor region is equal to the sixth semiconductor region of the second semiconductor region. It can be lower than the impurity concentration of a portion other than the semiconductor region. Of the sixth semiconductor region,
The depth from the first main surface of the semiconductor substrate may be substantially equal to or smaller than the depth of the third semiconductor region from the first main surface of the semiconductor substrate. The second semiconductor region surrounds an end of the third semiconductor region so that the sixth semiconductor region and the third semiconductor region are not in contact with each other except in an on-channel region. On the first main surface of the semiconductor substrate, the length of contact between the sixth semiconductor region and the third semiconductor region is determined by the distance between the other portion of the second semiconductor region and the third semiconductor region. It can be shorter than the contact length. In addition, a seventh semiconductor region of the first conductivity type, which is adjacent to the first semiconductor region and the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region, can be provided. The fifth semiconductor region exposed on the second main surface is formed only immediately below the second semiconductor region. The fifth semiconductor region exposed on the second main surface is formed immediately below a sixth semiconductor region.

In a method of manufacturing a semiconductor device according to the present invention, a step of forming a first semiconductor region of a first conductivity type exposed on a first main surface of a semiconductor substrate on the semiconductor substrate; Forming a second semiconductor region of the second conductivity type exposed on the first main surface of the first semiconductor region; and forming a second semiconductor region exposed on the first main surface of the semiconductor substrate. Forming a third semiconductor region of one conductivity type in the second semiconductor region, forming a fourth semiconductor region having a second conductivity type in the first semiconductor region, Forming a fifth semiconductor region of the second conductivity type exposed on the second main surface of the semiconductor substrate in the semiconductor region; and electrically connecting the third semiconductor region and the fourth semiconductor region to each other. Forming a first electrode that is electrically connected, the third semiconductor region and the Adjacent to the first semiconductor region, the second
Forming a sixth semiconductor region of the second conductivity type having an impurity concentration lower than the impurity concentration of the second semiconductor region in the semiconductor region, and forming a sixth semiconductor region on the first main surface of the semiconductor substrate. A gate insulating film interposed therebetween, at least a boundary between the first and second semiconductor regions, a boundary between the first and fourth semiconductor regions, and the second semiconductor region sandwiched between these boundaries; A boundary between the third semiconductor region and the sixth semiconductor region via a gate insulating film on an off-gate region which is a first region formed on the first main surface of the semiconductor substrate; Forming a gate electrode having a boundary between the semiconductor region No. 6 and the first semiconductor region and an on-gate region which is a second region formed on the sixth semiconductor region sandwiched between these boundaries; Formed on the fifth semiconductor substrate Forming a second electrode, wherein in the step of forming the sixth semiconductor region and the step of forming the third semiconductor region, the second semiconductor region is formed. First of semiconductor substrate
Forming a first conductivity type silicon epitaxial growth layer having a low impurity concentration on the main surface of the semiconductor substrate, selectively implanting impurities into the silicon epitaxial growth layer, and heat treating the semiconductor substrate. It is characterized by doing. Further, a MOS gate type thyristor according to the present invention comprises the above-described semiconductor device as one element, and integrates a plurality of the elements on one semiconductor substrate. Sides and
A second side face formed with an on-channel region adjacent to the first side face.

[0008]

Since the turn-on initial firing region is formed at a position separated from the turn-off initial operation region, the turn-on characteristics can be improved by partially changing the impurity concentration of the base region. . Further, since the low impurity concentration region of the base region is formed only in the surface region at the end, the turn-off characteristic is further improved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a schematic perspective view of a unit cell of the semiconductor device of this embodiment. The N ⁺ layer 5 and the P ⁺ layer 6 of the epitaxial growth layer formed on the back surface of the N ⁻ silicon semiconductor substrate 1, ie, the second main surface, are respectively defined as an N ⁺ buffer region 5 and a back surface P ⁺ emitter region 6.
On the back surface P ⁺ emitter region 6, an anode electrode 10
Since (A) is formed, the second main surface side of the semiconductor substrate has the same structure as the above-described conventional example (see FIG. 34).
On the other hand, on the first main surface side of the semiconductor substrate 1, the semiconductor substrate 1
A P-type base region 2, an N-type emitter region 3 formed in the base region, and a P-type drain region 4 formed in the N ^- base region 1 of the semiconductor substrate. Have been. These regions are N-type emitter region 3, P-type base region 2, N ^- base region 1 and P-type region 1, respectively.
The mold drain region 4 is exposed on the first main surface as third, second, first and fourth semiconductor regions. The second semiconductor region (P-type base region 2) includes a low-concentration region 17, and a third semiconductor region (N-type emitter region 3) near the portion exposed to the first main surface. And the first semiconductor region (N ^- base region 1). On the first main surface, a gate electrode 9 (K) and a gate electrode 8 (G) are formed via a gate oxide film 7. This game
Gate electrode 8, the first and includes a second two areas, the first area Goff (Ofuge - DOO region), N ^- base - source region 1 and the P-type base - source region 2, N ^- Each boundary between the base region 1 and the P-type drain region 4 and the N
^- base - is formed on the source region 1, the first region Goff
The second region Gon which is spaced apart from the (Onge - DOO region), N ^- base - source region 1 and the P ^- base - source region 17, P ^-
It is formed on each boundary between the base region 17 and the N-type emitter region 3 and on the P ^- base region 17 sandwiched between these boundaries.

Next, the manufacturing process of this semiconductor device will be described. An N ^- type silicon semiconductor substrate 1 is prepared and a second
An N ⁺ layer and a P ⁺ layer are sequentially grown on the main surface to form an N ⁺ buffer region 5 and a back surface P ⁺ emitter region 6. Next, a semiconductor substrate is used as an N ^- base region 1, a silicon oxide film and a polysilicon film are formed on the first main surface of the substrate by using a known technique, and selectively etched to form a gate.
An oxide film 7 and a gate electrode 8 are formed. Next, impurities are diffused from the first main surface to the N ^- base region to form P-type impurity.
^- forming a source region 17 - base. Then, the impurity is diffused into the other portion of the N ^- base region 1 and the P ^- base region 17 so that the N ^- base region 1 has the P-type drain region 4 and the P ^- base region 17 has the impurity. A P-type base region 2 is formed. further,
An N-type emitter region 3 is formed in the P-type base region 2. Usually, these diffusion regions are formed by ion-implanting impurities into the diffusion regions, but the gate electrode is used as a mask at that time. Therefore, when the N-type emitter region 3 is formed, this region slightly enters the inside of the first region Goff (off-gate region) of the gate electrode 8, so that the first region Goff is Region 3, P
It is formed over the mold base region 2, the N ^- base region 1 and the P-type drain region 4. However, in this part, the gate electrode 8 does not need to cover the N-type emitter region 3 because only the channel formed between these P-type regions is used. Therefore, as described above,
If the method using the gate electrode as a mask is not used, the first region Goff of the gate electrode is a P-type base region 2 and an N ^- base.
It is sufficient to cover only the source region 1 and the P-type drain region 4. Then, a part of the silicon oxide film is opened, and N
A cathode electrode 9 is formed on the type emitter region 3 and the P-type drain region 4, and an anode electrode 10 is formed on the back surface of the semiconductor substrate. N ⁺ buffer region 5 and back surface P
^{The +} emitter region 6 can also be formed by diffusing impurities into the semiconductor substrate. A feature of the structure of the present invention is that a low-concentration P ⁻ base region 17 is formed at an end of a P-type base region 2 in a vertical portion of a cell of a semiconductor device. In this embodiment, an N ⁻ type silicon substrate is used, but a method using a P ⁺ type silicon substrate can also be used in many cases. That is, the back surface P ⁺ -type emitter region 6 become P ⁺ -type silicon semiconductor substrate N ⁺ buffer region 5 and N ^- base - are sequentially grown the source region 1. Then, a P-type base region 2 and a P-type drain region 4 are respectively formed by diffusion on the surface of the N ^- base region 1, and an N-type emitter region 3 is formed in the P-type base region 2. Is formed by diffusion. The method of forming the other portions is the same as the method of this embodiment. This method is a common practice. This method can be used in the following embodiments.

Since the P ⁻ base region 17 is formed at the end of the P-type base region 2, even when the impurity concentration of the P-type base region 2 is increased to improve the turn-off characteristics, it can be used as a switch at the time of turn-on. Working N-channel MO
Since the SFET is always formed of the P ⁻ base region 17, the threshold voltage does not increase. In the turn-on operation, the N-type emitter region 3 near the P ⁻ base region operates as an initial operation region, and spreads to the center of the N-type emitter region 1. That is, even if the impurity concentration of the P-type base region is changed, the N-channel MOSFET that functions as a switch at the time of turn-on always operates at a constant threshold voltage, and the region where the turn-on is low also functions as an initial operation region, Since the turn-on region is expanded, the ON voltage can be suppressed. Thus, according to the present invention, it is possible to improve the trade-off between the turn-on and turn-off of the MCT. In addition, by adjusting the length of the cell in the vertical direction, adjusting the ratio of the length to the horizontal direction, and adjusting the base concentration, the trade-off between turn-on and turn-off is further improved, and the turn-off characteristics are also improved. Will be able to

The operation of the cell of the semiconductor device of this embodiment will be described with reference to FIGS. FIGS. 2 to 4 show the turn-on operation. FIG. 2 is a perspective view showing this operation, and FIGS. 3 and 4 are sectional views taken along the line YY 'of FIG. By inverting a positive voltage on the anode A and a negative voltage on the cathode K and positively biasing the gate, an inversion layer 18 is formed in the P ⁻ base region 17,
The N-channel MOSFET in this portion operates, and electrons are injected from N-type emitter region 3 to N ⁻ base region 1.
As a result, holes 13 are injected from the back surface P ⁺ emitter region 6 to cause conductivity modulation, so that the P ⁻ base region 17 becomes an initial ignition region 19 including turn-on, and then the turn-on region moves to the cell center portion. The spreading cell will be completely turned on.

FIGS. 5 and 9 are perspective views of a cell of a semiconductor device for explaining a turn-off operation. Anode A
By positively biasing the cathode K with a negative voltage and biasing the gate G negatively with the main current flowing, the P-channel MOSFET operates to form the inversion layer 20 and the P-type base region 2 , P-type drain region 4 and the cathode electrode are short-circuited, and holes 16 in the main current are discharged from cathode electrode 9. By this operation, injection of electrons from the N-type emitter region 3 is stopped, and the main current 14 (I) does not flow, thereby completing the turn-off.

FIGS. 6 and 8 are schematic plan views of an initial operation area when the semiconductor substrate is turned on and turned off. The turn-on initial operation region (initial ignition region) 21 is at both ends of the N-type emitter region 3 near the P ⁻ base region 17, and the turn-off initial operation region (initial arc-extinguishing region) 22 is the N-type emitter region 3. In contact with the P-type base region 2 of FIG. That is, the turn-on starts from both ends of the N-type emitter region and spreads to the center of the N-type emitter region.
4) is different from the operation mode starting from the N-type emitter region 3 in contact with the P base region 2 for both turn-on and turn-off. FIG 6, FIG. 7, N-type emitter region 3 and P-type base with reference to FIGS. 8 and 9 - source region 2 and the P ^- base -
The state of the boundary with the storage area 17 will be described. 6 and 8
As shown in the plan view of the semiconductor substrate, the P-type base region 2 and the N-type emitter region 3 formed therein are elongated in the same direction. That is, the initial firing region 21 at the time of turning on may be as short as possible, and the longer the initial operating region 22 at the time of turning off, the better the off characteristic. Therefore, by appropriately changing the ratio between these regions 21 and 22, that is, the ratio between the short side (h) and the long side (H) of the N-type emitter region 3, either the ON characteristic or the OFF characteristic is emphasized. Can be. Of course, it is necessary that H> h. H in this embodiment is about 5 μm, but can be about 1 to 10 μm at present. In this embodiment, h / H is about 1/5, but it can be reduced to about 1/10 in order to improve the off-characteristics. In
It can be reduced to about 1/3. P-type base region 2
, That is, a P ^- base region 17 is formed so as to surround the short side of the N-type emitter region 3, and the P-type base region 2 is formed at the end of the N-type emitter region 3. The portion is formed so as to surround the portion (see FIGS. 6 to 8), and is usually designed so that the N-type emitter region 3 and the P ^- base region 17 are not in contact with each other. Otherwise, the P ^- base region 1
7 contributes to the turn-off operation, so that the energized area where the hole discharged at the time of the turn-off is difficult to move tends to remain, thereby impairing the turn-off characteristics. FIG.
FIG. 17 is a sectional view showing a side surface of the gate electrode 8 of the MCT shown in FIG. 6 where the on-gate region is formed, and FIG.
FIG. FIG. 9 is a cross-sectional view showing a side surface on which an off-gate region is formed. The portion where the gate electrode 8 and the cathode electrode 9 overlap is insulated from each other by the interlayer insulating film 42.

The turn-on and turn-off characteristics of the present invention are as follows.
Although improved by the presence of the P ^- base region 17, MC
The current-voltage characteristic of T depends on the impurity concentration of the P ^- base region 17 as shown in FIG. In the figure, the horizontal axis represents the on-voltage (V), and the vertical axis represents the current (A / cm ² ). Curves A, B, C and D show that the impurity concentration of the N-type emitter region 3 is 2 × 10 ²⁰ / cm ² and the impurity concentration of the P-type base region 2 is 1.0 × 10 ¹⁷ / cm.
cm ² , 2.0 × 10 ¹⁸ / cm ² , 4.0 × 10 ¹⁸ / c
Current at m ² and 5.0 × 10 ¹⁸ / cm ² −
It is a curve which shows a voltage characteristic. The lower the impurity concentration of the P ^- base region 17 is, the higher the current-voltage is. That is, P
^{Since the} higher the impurity concentration of the base region 17 is, the higher the current can be obtained with a lower on-voltage, the provision of the on-gate region in the P-type base region 2 improves the on-characteristics. Will do.

FIG. 17 is a perspective view of an MCT chip which is a semiconductor device of the present invention formed from a semiconductor substrate having a plurality of cells. The first major surface of the semiconductor substrate, the elongated P-type drain region 4, P ^- base - source region 17 laden P-type base - in a pair and a source region 2 form a plurality in a matrix, electrodes of each cell To form a gate G and a cathode K of the chip on the surface of the semiconductor substrate. On one side of the drawing, an off-channel is formed in the N ^- base region 1 between the P-type base region 2 and the P-type drain region 4 below the off-gate region Goff of the gate electrode, and further adjacent thereto. the side surfaces, gate - the gate electrode Onge - DOO region Gon of N lower ^- base - P between the source region 1 and N type emitter region 3 ^- base - to form an on-channel in the source region 17. The chip size is about 2 to 4 mm square in this embodiment.

Next, a second embodiment will be described with reference to FIGS. FIG. 10 is a schematic perspective view of the MCT of this embodiment, and FIGS. 11 and 12 are perspective views of the MCT for explaining turn-on and turn-off operations, respectively. In this structure, the N ⁻ type silicon semiconductor substrate used in the first embodiment is changed to a P ⁻ type silicon semiconductor substrate. Similar to the previous embodiment, P ^- the second type silicon semiconductor substrate 23
, A P ⁺ buffer region 28 and a back N ⁺ emitter region 29 are formed on the main surface. Next, the gate oxide film 30 and the polysilicon gate electrode 31 are stacked on the first main surface of the semiconductor substrate, and then the N ⁻ base region 24, the N type base region 25, the P type emitter Region 26,
An N-type drain region 27 is formed. Then, a part of the gate oxide film is opened to form the anode electrode 32, and the cathode electrode 3 is formed on the back surface, that is, on the second main surface.
Form 3

Next, turn-on and turn-off operations will be described. The turn-on operation is performed when the anode 32 is positive,
By biasing the cathode 33 with a negative voltage and the gate 31 with a negative bias, the P-channel MOSFET operates and the inversion layer 36 is formed. Then, holes 34 are injected into the P ⁻ base region 23, and electrons 35 are injected from the back N ⁺ emitter region 29, so that conductivity modulation occurs in the P ⁻ base region 1, and the P ⁻ base region 1 is turned on and a main current starts to flow. . In the turn-off operation, the inversion layer 39 is formed by operating the N-channel MOSFET by biasing the anode 32 positive and the cathode 33 negative and biasing the gate 31 positive while the main current 37 is flowing.
Then, by short-circuiting the N-type base region 25, the N-type drain region 27, and the anode electrode 32, the electrons 38 are discharged from the main current, and the injection of holes from the P-type emitter region 26 is stopped. Will stop. That is, the second embodiment is similar to the first embodiment in the turn-on and turn-off operation characteristics, except that the injected and discharged carriers are reversed.

Next, referring to FIG. 13 to FIG.
An example will be described. FIG. 13 is a schematic perspective view of the MCT,
14 and 15 are schematic perspective views of the MCT for explaining the turn-on and turn-off operations. This structure is called an anode short structure, in which the anode and the back surface N ⁺ region are short-circuited. A back surface P ⁺ emitter region 40 and an N ⁺ region 41 are formed on the second main surface side of the N ⁻ silicon semiconductor substrate 1. Then, on the first main surface, the gate oxide film 7 and the polysilicon gate electrode are formed. 8 is formed. Then, impurities are diffused from the first main surface to the semiconductor substrate to form a P ^- base region 17, a P-type base region 2, an N-type emitter region 3 and a P-type drain region 4, and a part of the gate oxide film is formed. The holes are opened to form the cathode electrode 9 and the anode electrode 10 is formed on the back surface. The turn-on and turn-off operations are the same operation modes as in the first embodiment. However, since this structure is an anode short structure, at the time of turn-on P ^-
Holes are injected from the back surface P ⁺ emitter region 40 immediately below the base region 17 to turn on. At the time of turn-off, the back surface P ⁺ emitter region 40 is alternately provided with the N ⁺ region immediately below the N-type emitter region 3, and the back surface P ⁺ emitter region is not provided immediately below the P-type emitter region. The structure has a structure that makes it easy to turn off.

Next, a fourth embodiment will be described with reference to FIG. This is a schematic perspective view of the MCT, and its structure is the same as that of the first embodiment shown in FIG. 1 except that the first region Goff (off-gate region) of the gate electrode 8 is different. Same as MCT. In FIG. 1, the first region Gof
f was also formed on the N-type emitter region 3. This is because when the region 3 is formed by diffusion of impurities,
Since the gate is used as a mask, it is unavoidable that the emitter region 3 slightly enters under the gate as shown in FIG. However, in practice, this part
The gate on this region 3 is used only for
No off-channel is required (only off-channel formed in N ^- base region 1 is required). Therefore, in this embodiment, the gate on the N-type emitter region 3 is removed,
The oxide film 7 is exposed.

As described above, in the above embodiments, the MCT
Discloses a self-extinguishing element that separates an on-gate region from an off-gate region, increases the efficiency of the off-gate portion, and improves turn-off characteristics. However, even if the turn-off characteristic is improved by the above-described method, when the element is completely turned off and reaches a conductive state, the P-P at the time of the turn-off operation is reduced.
Even when the hole current component in the main current 14 is discharged from the path of the mold base region 2 to the P channel inversion layer 20 to the P-type drain region 4 to the cathode electrode 9, the hole current component is formed at a low concentration and becomes an on-gate region. In the P ⁻ base region 17, it is difficult to discharge the hole current component due to the high resistance of the discharge path, and the conduction state is maintained in this portion, and it is difficult to completely turn off the device (see FIG. 5).

Next, a fifth embodiment will be described with reference to FIG. This embodiment improves the turn-off characteristics by solving the problem that it is difficult to turn off because the conductive state is easily maintained in the P ⁻ base region in the first to fourth embodiments, and furthermore,
The trade-off between turn-on and turn-off characteristics is facilitated. That is, in the embodiments described above, the P ⁻ base region 17 serving as the on-gate region is formed over the entire end portion of the P base region 2, but in this embodiment, the P-type base region 2 is formed below the on-gate region. The P ⁻ base region 1 is formed only on the surface of the P type base region 2 immediately below the on-gate region.
7 is formed. This low impurity concentration P ⁻ base region 17
Is a part of the P-type base region 2 and is formed at an end thereof. The P ^- base region 17 is arranged under the second region (on-gate portion) Gon of the gate electrode 8, and its depth from the first main surface of the semiconductor substrate 1 is equal to this region. 1
The depth from the main surface of the N-type emitter region 3 adjacent to 7 is substantially equal to or smaller than this depth. Other configurations are the same as those in FIG. With this structure,
Only the surface portion forming the on-channel region becomes the P ⁻ base region 17, and the P-type base region 2 is also formed immediately below the on-channel region. Similarly, the current is easily cut off, and the turn-off characteristics can be improved.

Next, the operation principle (turn-on / turn-off) of the present invention will be described with reference to FIGS. First, the turn-on operation will be described. FIG.
FIG. 21 is a front view of a semiconductor substrate for explaining this operation.
Is a side view and FIG. 22 is a plan view thereof. When the anode A is biased positively, the cathode K is biased negatively, and the gate G is biased positively, the P ⁻ base region 17 on the surface of the semiconductor substrate 1 is exposed.
An N channel inversion layer 18 is formed on the very surface, and electrons 12 are injected from N type emitter region 3 to N ⁻ base region 1. Thereby, holes 13 are removed from back surface P ⁺ emitter region 6.
Is implanted into the N ⁻ base region 1. Thus, N ^- conductivity modulation occurs in the base region 1 through the P-type base region 2 from the N-type emitter region 3, N ^- direct electron 12 are injected into the base region 1, the turn-on is the P ^- base region 17 Starting from the initial ignition region 21 of the nearby N-type emitter region 3, the turn-on region further extends to the N-emitter center region, and the device is turned on.

Next, the turn-off operation will be described. FIG. 23 is a front view of the semiconductor substrate illustrating this operation, FIG. 24 is a side view, and FIG. 25 is a plan view thereof. When the anode A is positively biased, the cathode K is negatively biased, and the gate G is negatively biased while the main current 14 is flowing, the N-channel inversion layer 18 formed at turn-on disappears and the P-type base / P-type A P channel inversion layer 20 is formed on the surface of the N ⁻ base region 1 between the drain regions,
P-type base region 2 to P-type drain region 4 to cathode electrode 9 are short-circuited, and holes 16 in main current 14 are discharged from cathode electrode 9. By this operation, injection of electrons from the N-type emitter region 3 stops, and the main current 14 stops flowing. The turn-off region starts from the initial arc-extinguishing region 22 facing the P-type drain region 4 of the N-type emitter region 3 and finally spreads over the entire N-type emitter region 3 to turn off the device.

Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS. The figure shows P
FIG. 3 is a partial cross-sectional view of the semiconductor substrate centered on a mold base and a P-type drain region. As shown in FIG. 20, an N ⁺ buffer layer 5 and a back surface P ⁺ emitter layer 6 are formed on the second main surface of the N ⁻ semiconductor substrate 1, and a normal diffusion technique such as ion implantation or solid phase diffusion is used. Is used to form a P-type base region 2 and a P-type drain region 4 (FIG. 26). Then, this P
A low impurity concentration P ^- silicon epitaxial layer 43 having a thickness of about 1 μm is grown on the surface of the semiconductor substrate 1 including the mold base region 2 and the P-type drain region 4 (FIG. 27). Next, for example, impurities are ion-implanted into the epitaxial layer 43 to form the P-type drain region 4 and the P ⁻ base region 17.
Then, an N-type emitter region 3 is formed, and a gate oxide film 7 and a polysilicon gate electrode 8 are formed on the surface of the epitaxial layer 43. (FIG. 28). Next, the oxide film is selectively removed by etching to form the cathode electrode 9 thereon and the anode electrode 10 on the back surface.
As described above, by using the epitaxial growth layer, in the above-described embodiment, the P ⁻ base region 17 formed at the end of the P type base region 2 at the same diffusion depth as the P type base region is replaced with the P type base region. It can be formed only on the surface of the end in the region 2.

Next, another method of forming the P ^- base region 17 will be described with reference to FIG. Illustration of the P-type drain region 4 is omitted. The steps up to FIG. 26 in the above method are common to this method. Then, the P-type base region 2 and P
A low impurity concentration N ^- silicon epitaxial layer 44 having a thickness of about 1 μm is grown on the surface of the semiconductor substrate 1 including the type drain region 4 and the like (FIG. 29A). Next, the semiconductor substrate 1 is subjected to a heat treatment so that the P-type impurities in the P-type impurity
And the epitaxial layer 44 on the regions 2 and 4
Changes to the P ⁻ silicon epitaxial layer 43 (FIG. 29B). Therefore, this epitaxial layer 43
Then, impurities are selectively ion-implanted as appropriate to form a P ^- base region 17 as shown in FIG.

In another method, as shown in FIG. 29A, after the N ^- silicon epitaxial layer 44 is formed, the semiconductor substrate is directly ion-implanted without being subjected to a thermal diffusion process. A P ^- base region 17 shown in FIG. 28 is formed. In the formation of such a P ⁻ base region, a manufacturing method using an epitaxial growth layer has been described as an example, but it is also possible to form the P ⁻ base region by a method using buried diffusion or an adhesive wafer.

Next, a sixth embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. In this structure, the N ^- silicon semiconductor substrate used in the fifth embodiment is changed to a P ^- silicon semiconductor substrate 23. On the second main surface, a P ⁺ buffer region 28 and a back surface N ⁺ emitter region 29 are epitaxially grown. Next, an N-type base region 25, an N ^- base region 24 which is a part of this region, a P-type emitter region 26, and an N-type drain are formed on the first main surface of the semiconductor substrate 23 by impurity diffusion. A region 27 and the like are formed, and then a gate oxide film 30 and a polysilicon gate electrode 31 are laminated. An anode electrode (A) 32 is formed by opening a part of the oxide film, and a cathode electrode (K) 33 is formed on the back surface (second main surface).
To form In the turn-on operation, a positive voltage is applied to the anode 32, a negative voltage is applied to the cathode 33, and a negative bias is applied to the gate 31, so that the P-channel MOSFET operates to form an inversion layer. . And a P ^- base region 2
3, holes are injected, and electrons are injected from the back surface N ⁺ emitter region 29. As a result, conductivity modulation occurs in the P ^- base region 23, and the P ^- base region 23 is turned on and the main current starts to flow.
In the turn-off operation, when the main current flows by biasing the anode 32 with a positive voltage and the cathode 33 with a negative voltage, the gate 31 is positively biased, and the electron is converted from the main current. And the injection of holes from the P-type emitter region 26 is stopped to stop the main current. N ^- base - scan the area under the 24 N-type base - source region 25 is also data - so contributes to turnoff operation, its operation is improved than the first embodiment.

Next, a seventh embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. This structure is called an anode short structure similarly to FIG. 13, and has a structure in which an anode electrode and a back surface N ⁺ region are shorted. N ^- forming a backside P ⁺ emitter region 40 and the back surface N ⁺ region 41 to the second main surface of the silicon semiconductor substrate 1, and diffusing an impurity from the first major surface to the semiconductor substrate 1, P-type base - scan A region 2, an N-type emitter region 3, a P-type drain region 4, and a P ^- base region 17 having a diffusion depth substantially equal to that of the N-type emitter region 3 are formed. Then, a gate oxide film 7 and a polysilicon gate electrode 8 are laminated on the first main surface, and a part of the oxide film is opened to form a cathode electrode 9, and a back surface is formed on the back surface. An anode electrode is formed. The turn-on / turn-off operation is the same as the operation mode of the third embodiment shown in FIG. N ^- base - N-type base beneath the source region 17 - source region 2 even data - so contributes to turnoff operation, its operation is first
Is improved as compared with the embodiment.

Next, an eighth embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. This structure is the same as that of FIG. 18, except that the P ^- base region 17 is formed not on the entire end of the P-type base region 2 but only on the surface region of this end. P ^- base - P-type base beneath the source region 17 - source region 2, data - which acts as a turnoff region. Therefore, the turn-off operation is performed as shown in FIG.
Are improved over the fourth embodiment shown in FIG.

Next, a ninth embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. In the embodiments described above, the gate electrodes 8, 31 are the first electrodes.
Area Goff and the second area Gon, and these areas are integrated. However, in the present invention,
The gate electrode does not need to be integrated, and the first and second
May be separated. As shown in this figure, the gate electrode 8 is divided into an off-gate region as a first region Goff and an on-gate region as a second region Gon. This figure shows the structure of one cell.
When the CT is actually used, a plurality of the cells are arranged, for example, vertically and horizontally as shown in FIG. 17 and used as one semiconductor device. To combine cells into one,
For example, the second region Gon is integrated in each cell row, while the first region Goff is separated for each cell. Therefore, each first region must be connected to each row by a wiring such as Al while paying attention to insulation.

The fifth to ninth embodiments are to improve the turn-off characteristic which has been a problem in the first to fourth embodiments. In the first embodiment, the impurity concentration of the P-type base region 2 and the P-type drain region 4 is increased so that the P-type base region
The turn-off characteristic has been improved by a method of efficiently discharging holes by lowering the resistance of the hole current discharging path of the P channel inversion layer, the P-type drain region, and the cathode electrode. However, even if the turn-off characteristic is improved by this method, it is difficult to discharge the hole current component because the resistance of the discharge path is high in the P ⁻ base region 17 formed at a low concentration and serving as the on-gate region. Since the conduction state is maintained, current tends to remain at the time of turn-off. This was a factor that hindered the improvement of the turn-off characteristics. The second embodiment has a structure in which the P ⁻ base region 17 is formed only on the surface of the end portion of the P-type base region 2. That is, by forming the P ⁻ base region 17 only at the end surface of the P-type base region 2 where the N-channel inversion layer is formed at the time of turn-on, the resistance of the hole current discharge path at the time of turn-on is reduced, and the current is cut off. Making it easier.

FIGS. 20 to 25 show the operation and effect.
This will be described with reference to FIG. As shown in the figure, the P ⁻ base region 17 is formed at the connection portion between the N ⁻ emitter region 3 in the P type base region 2 and the surface portion up to the junction of the N ⁻ base region 1. Therefore, in this structure, the P ⁻ base region 17 is formed only in the portion where the N-channel inversion layer 18 is formed at the time of turn-on. Accordingly, the element is biased positively on the anode and negatively on the cathode at the time of turn-off, negatively biases the gate while the main current is flowing, and forms an N ⁻ base region between the P-type base region 2 and the P-type drain region 4. A P-channel inversion layer 20 is formed on one surface, the P-type base region-P-type drain region-cathode electrode 9 is short-circuited, and holes 16 in the main current are discharged from the cathode electrode 9.

By this operation, injection of electrons from N-type emitter region 3 stops. At this time, since the P ⁻ base region 17 is surrounded by the P-type base region 2 at the junction between the P-type base region 2 and the N-type emitter region 3 at the end, when the N-channel inversion layer 18 at the time of turn-on is closed. The injection of electrons is easily stopped, and the turn-off characteristics of the device are improved. As described above, since the P ⁻ base region 17 is only the surface portion at the end of the P-type base region 2 and its periphery is surrounded by the P-type base region 2, injection of electron current is suppressed and the turn-off characteristic is improved. improves. Regarding the turn-on characteristic, since the P ⁻ base region 17 is located in the region where the N-channel inversion layer 18 is formed, the characteristics of the N-channel MOSFET are the same as those of the first embodiment, and 18 is sufficiently injected into the N ⁻ base region 1, so that the turn-on characteristics are not changed.

The present invention can be applied to a double gate structure by using these embodiments in addition to the above-described embodiments. Further, in the above-described embodiment, silicon is used as the semiconductor material. However, this use is only an example, and other existing materials such as Ge and GaAs can be appropriately used. Incidentally, the impurity concentration of the P ^- base region formed in the surface region at the end of the P-type base region of the semiconductor device shown in the embodiment is 1.0 to maintain the turn-on characteristic. It is desirable that it be not more than × 10 ¹⁸ cm ⁻³ .

[0036]

As described above, according to the present invention, the MCT
Since the on-off and turn-on initial operation regions are separated from each other, the impurity concentration of the base region can be changed depending on the location, and the turn-off / turn-on characteristic which has been a problem in the prior art is reduced. -It is possible to improve the turn-off efficiency and improve the turn-off efficiency.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic perspective view illustrating a turn-on operation of the semiconductor device of FIG. 1;

FIG. 3 is a sectional view in the YY ′ direction illustrating a turn-on operation of the semiconductor device of FIG. 1;

FIG. 4 is a sectional view in the YY ′ direction illustrating a turn-on operation of the semiconductor device of FIG. 1;

FIG. 5 is a schematic perspective view of the semiconductor device for explaining a turn-off operation of the semiconductor device of FIG. 1;

FIG. 6 is a plan view of a semiconductor device illustrating a turn-on operation of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor device illustrating a turn-on operation of the present invention.

FIG. 8 is a plan view of a semiconductor device illustrating a turn-off operation of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor device illustrating a turn-off operation of the present invention.

FIG. 10 is a perspective view of a semiconductor device according to a second embodiment of the present invention.

FIG. 11 is a perspective view illustrating a turn-on operation of the semiconductor device of FIG. 10;

FIG. 12 is a perspective view illustrating a turn-off operation of the semiconductor device in FIG. 10;

FIG. 13 is a perspective view of a semiconductor device according to a third embodiment of the present invention.

FIG. 14 is a perspective view illustrating a turn-on operation of the semiconductor device in FIG. 13;

FIG. 15 is a perspective view illustrating a turn-off operation of the semiconductor device in FIG. 13;

FIG. 16 is a characteristic diagram showing the impurity concentration dependency of the turn-on operation of the semiconductor device of the present invention.

FIG. 17 is a perspective view of a semiconductor device (MCT) on which a plurality of cells of the present invention are mounted.

FIG. 18 is a perspective view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 19 is a perspective view of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 20 is a front view illustrating a turn-on operation of the semiconductor device of FIG. 19;

FIG. 21 is a side view illustrating a turn-on operation of the semiconductor device of FIG. 19;

FIG. 22 is a plan view illustrating a turn-on operation of the semiconductor device in FIG. 19;

FIG. 23 is a front view illustrating a turn-off operation of the semiconductor device of FIG. 19;

FIG. 24 is a side view illustrating a turn-off operation of the semiconductor device of FIG. 19;

FIG. 25 is a plan view illustrating a turn-off operation of the semiconductor device in FIG. 19;

FIG. 26 is a sectional view of the semiconductor device in FIG. 19 during a manufacturing step;

FIG. 27 is a sectional view showing the manufacturing process of the semiconductor device of FIG. 19;

FIG. 28 is a sectional view of the semiconductor device in FIG. 19 during a manufacturing step;

FIG. 29 is a sectional view of the semiconductor device in FIG. 19 during a manufacturing step;

FIG. 30 is a perspective view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 31 is a perspective view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 32 is a perspective view of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 33 is a perspective view of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 34 is a schematic perspective view of a conventional semiconductor device (MCT).

FIG. 35 is a cross-sectional view taken along the line XX ′ of FIG. 34, illustrating the turn-on operation;

FIG. 36 is a sectional view taken along the line XX ′ of FIG. 34, illustrating the turn-on operation;

FIG. 37 is a sectional view taken along the line XX ′ of FIG. 34, illustrating the turn-off operation;

FIG. 38 is a sectional view taken along the line XX ′ of FIG. 34, illustrating the turn-off operation;

[Explanation of symbols]

Reference Signs List 1 N ^- semiconductor substrate 2 P-type base region 3 N-type emitter region 4 P-type drain region 5 N ⁺ buffer region 6, 40 Back surface P ⁺ emitter region 7, 30 Gate oxide film 8, 31 Polysilicon gate electrode 9, 33 Cathode electrodes 10, 32 an anode electrode 11,18,39 N-type inversion layer 12,35,38 electron current 13,16,34 hole current 14, 37 main current 15,20,36 P type inversion layer 17 P ^- base - scan Region (sixth region) 21 Initial firing region 22 Initial arc extinguishing region 23 P ^- semiconductor substrate 24 N ^- base region 25 N-type base region 26 P-type emitter region 27 N-type drain region 28 P ⁺ buffer Region 29 back surface N ⁺ emitter region 41 back surface N ⁺ region 42 interlayer insulating film 43 P ^- silicon epitaxial layer 44 N ^- silicon epitaxial layer

Continuation of front page (56) References JP-A-63-310171 (JP, A) JP-A-2-110975 (JP, A) JP-A-4-99384 (JP, A) JP-A-4-284669 (JP) JP-A-4-207083 (JP, A) JP-A-4-207081 (JP, A) JP-A-3-204976 (JP, A) JP-A-63-53972 (JP, A) 62-252168 (JP, A) JP-A-6-177371 (JP, A) European Patent Application 438,700 (EP, A1) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/749 H01L 29/74

Claims (10)

(57) [Claims] A first semiconductor region of a first conductivity type exposed on a first main surface of a semiconductor substrate; and a first semiconductor region formed in the first semiconductor region and exposed on the first main surface. A second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type formed in the second semiconductor region and exposed on the first main surface; A fourth semiconductor region of a second conductivity type formed in a semiconductor region and exposed to the first main surface; and a fourth semiconductor region formed in the first semiconductor region and exposed to a second main surface of the semiconductor substrate. A fifth semiconductor region of a second conductivity type, a first electrode electrically connected to the third semiconductor region and the fourth semiconductor region, and a first main surface of the semiconductor substrate. A gate oxide film formed thereon, and at least a boundary between the first and second semiconductor regions, and the first and fourth semiconductor regions. A boundary between body regions, an off-gate region as a first region formed on the first semiconductor region sandwiched between the boundaries, and the semiconductor substrate
Formed on the first main surface via the gate oxide film.
Is the first boundary of the second semiconductor region, the third and second
A gate electrode having an on-gate region which is a second region formed on the second semiconductor region sandwiched between the boundaries of the semiconductor regions, and on the fifth semiconductor region; A second electrode formed , wherein the second semiconductor region and the fourth semiconductor region are in front of each other.
Under the off-gate region, the first semiconductor region is
Wherein a are opposed to each other with. 2. A portion of the second semiconductor region formed below the second region of the gate electrode is a sixth semiconductor region, the impurity concentration of which is equal to that of the second semiconductor region. 2. The semiconductor device according to claim 1, wherein the impurity concentration is lower than that of the portion other than the sixth semiconductor region. 3. The depth of the sixth semiconductor region from the first main surface of the semiconductor substrate is substantially equal to the depth of the third semiconductor region from the first main surface of the semiconductor substrate. Or shallower than it.
3. The semiconductor device according to claim 1. 4. The second semiconductor region surrounds an end of the third semiconductor region so that the sixth semiconductor region and the third semiconductor region are not in contact with each other except in an on-channel region. 4. The semiconductor device according to claim 2, wherein: 5. The semiconductor device according to claim 1, wherein:
The length of contact between the sixth semiconductor region and the third semiconductor region is shorter than the length of contact between the other portion of the second semiconductor region and the third semiconductor region. The semiconductor device according to claim 2. 6. A semiconductor device according to claim 1, further comprising a seventh semiconductor region of a first conductivity type, which is adjacent to the first semiconductor region and the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region. The semiconductor device according to claim 1, wherein: 7. The semiconductor device according to claim 1, wherein the fifth semiconductor region exposed on the second main surface is formed only immediately below the second semiconductor region. 13. A semiconductor device according to claim 1. 8. The semiconductor device according to claim 7, wherein the fifth semiconductor region exposed on the second main surface is formed immediately below a sixth semiconductor region. 9. A step of forming a first conductivity type first semiconductor region exposed on the first main surface of the semiconductor substrate on the semiconductor substrate; and exposing the first semiconductor region on the first main surface of the semiconductor substrate. Forming a second semiconductor region of the second conductivity type in the first semiconductor region, and a third semiconductor region of the first conductivity type exposed on the first main surface of the semiconductor substrate Forming in the second semiconductor region; forming a fourth semiconductor region having a second conductivity type in the first semiconductor region; and forming the fourth semiconductor region in the first semiconductor region. Forming a fifth semiconductor region of the second conductivity type exposed on the second main surface; and forming a first semiconductor region electrically connected to the third semiconductor region and the fourth semiconductor region. Forming an electrode; adjoining the third semiconductor region and the first semiconductor region; Forming a sixth semiconductor region of a second conductivity type having an impurity concentration lower than that of the second semiconductor region in the second semiconductor region; A gate insulating film on the surface, at least a boundary between the first and second semiconductor regions, a boundary between the first and fourth semiconductor regions, and the second region sandwiched between these boundaries. The first formed on the semiconductor region
An off-gate region, which is a region of
A boundary between the third semiconductor region and the sixth semiconductor region, a boundary between the sixth semiconductor region and the first semiconductor region, and a boundary between the third semiconductor region and the sixth semiconductor region on the main surface via a gate insulating film. Forming a gate electrode having an on-gate region that is a second region formed on the sandwiched sixth semiconductor region; and forming a second electrode formed on the fifth semiconductor substrate. Performing the step of forming the sixth semiconductor region and the step of forming the third semiconductor region in the first main portion of the semiconductor substrate on which the second semiconductor region is formed. Forming a first conductivity type silicon epitaxial growth layer having a low impurity concentration on a surface, selectively ion-implanting impurities into the silicon epitaxial growth layer, and adding an impurity to the silicon epitaxial growth layer. Performing a heat treatment on the substrate into which the ions have been implanted. 10. The semiconductor device according to claim 1, wherein the semiconductor device is one element, and a plurality of the elements are integrated on one semiconductor substrate, and the semiconductor substrate has an off-channel region formed therein. A thyristor having a first side surface and a second side surface adjacent to the first side surface and having an on-channel region formed therein.