JPH05218401A - Semiconductor device, manufacture thereof and mos gate driving type thyristor - Google Patents

Abstract

PURPOSE:To improve the trade off of turn-ON and turn-OFF characteristics, and to provide a MOS gate driving type thyristor having improved turn-OFF characteristics than the former ones. CONSTITUTION:A gate electrode 8 consists of the first region G-OFF provide an OFF-gate part and the second region G-ON provided on an ON-gate part. A P-channel part is formed on the OFF-gate part, an N-channel part is formed on the ON-gate part, and the ON and OFF gate parts are separated. As a low density P-channel region 17 is formed on the end part or the end face of a P-base region 2 where an N-channel will be formed, the impurity density of the P-base region can be formed high, and the turn-OFF characteristics can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MOS gate drive type thyristor which can be turned on and off by a MOS gate and a manufacturing method thereof.

[0002]

2. Description of the Related Art A MOS gate drive type thyristor (hereinafter, referred to as
MCT (MOS gate Controlled Thyristor)
Is a thyristor that turns on when a voltage is applied to the gate electrode and the same conductive type emitter and base are short-circuited by a MOS gate type transistor.
This operation requires a small gate power because it is voltage controlled. In addition, since self turn-off cannot be achieved with this structure alone, a control electrode is provided on the emitter having a conductivity type opposite to that of the base, and a negative bias is applied to this control electrode to reduce the anodic current. MOS that self-turns off by discharging the part as a base current to the outside
Type thyristors are known. FIG. 34 shows an example of a conventional MCT technology (1991, IEEE 138 to 141).
page). The figure is a perspective view of the MCT. Impurities are diffused on the first main surface of the N ⁻ silicon semiconductor substrate 1 to form a P type base region 2 and a P ⁺ drain region 4, and the P type base region 2 further has an N type. The emitter region 3 is formed.
On the second main surface of the semiconductor substrate 1, that is, on the back surface, semiconductor layers are sequentially grown to form an N ⁺ layer 5 and a P ⁺ layer 6,
These are a buffer region and a back surface P ⁺ emitter region, respectively. Then, an anode electrode 10 (A) is formed on the back surface P ⁺ emitter region 6. On the other hand, N on the first main surface side
^A gate oxide film 7 is formed so as to cover the silicon semiconductor substrate 1, the P-type base region 2, the N-type emitter region 3 and the P ⁺ drain region 4. A polysilicon gate electrode 8 (G) is formed on the gate oxide film 7. Then, the gate oxide film 7 and the gate electrode 8 are partially removed, and a cathode electrode 9 (K) is formed on the opened N emitter region 3 and P ⁺ drain region 4.

The operation principle (turn-off / turn-on) of such a conventional MCT will be described. First,
The turn-on operation will be described with reference to FIGS. 35 and 36. A positive voltage is applied to the gate G while the anode A is positively biased and the cathode K is negatively biased, and the semiconductor substrate (N ^- base region) 1, the P-type base region 2 and the N-type emitter region 3 are The configured N-channel MOSFET is operated to form the inversion layer 11, and the N-type emitter region 3 to N ⁻
Electrons 12 are injected into the base region 1 (FIG. 35). N ^- N from the rear surface P ⁺ emitter region 6 by the injection of electrons into the base region 1 ^- hole 13 into the base region 1 are injected to turn on device by causing conductivity modulation, the main current 14
Will flow (Fig. 36). Next, the turn-off operation will be described with reference to FIGS. 37 and 38. With the anode A being positively biased and the cathode K being negatively biased, the gate G is negatively biased while the main current 14 is flowing, and N ⁻
An inversion layer 15 is formed by operating a P-channel MOSFET composed of the base region 1, the P-type base region 2 and the P ⁺ drain region 4. Thereby, the P-type base region 2,
The P ⁺ drain region 4 and the cathode electrode 9 are short-circuited, and the holes 16 in the main current are discharged through this path. The holes in the main current are discharged, so that the injection of electrons from the N-type emitter region 3 is stopped and the main current 14 stops flowing. This completes the turn-off operation. The MCT is a self-extinguishing element capable of performing the turn-on / turn-off operation as described above.

[0004]

Since the MCT is an element that turns on due to its operating characteristics, it has a problem that it is difficult to turn off. Currently, development is underway to improve the turnoff characteristics. Further, in this structure, in order to improve the turn-off characteristics, it was necessary to increase the concentrations of the P-type base region 2 and the P ⁺ drain region 4. That is, in the turn-off operation as shown in FIGS. 37 and 38, holes are generated from the main current by the inversion layer 15 formed by the operation of the P-channel MOSFET to the cathode electrode 9.
The hole discharge efficiency when discharged to the P-type base region 2 is
And is affected by the sheet resistance of the P ⁺ drain region 4. Therefore, in order to improve the hole discharge efficiency, it is necessary to increase the concentrations of the P-type base region 2 and the P ⁺ drain region 4 and reduce the sheet resistance. However, if the turn-off structure is prioritized and the concentration of the P-type base region 2 is increased as described above, the turn-on characteristics are deteriorated. That is, in the turn-on operation shown in FIG. 35, the N-channel MOSFET is operated to form the inversion layer 11, and electrons are injected from the N-type emitter region 3 to the N ⁻ base region 1 to cause conductivity modulation and generate a main current. When shedding,
When the concentration of the P-type base region 2 increases, the N-channel MOS
In addition to increasing the threshold voltage of the FET, the on-voltage increases when the main current flows, and the loss at turn-on increases. As described above, there is a reciprocal relationship between the improvement of the turn-on and turn-off characteristics of the MCT. If one of the characteristics is improved, the other characteristics deteriorate, and it is difficult to make a trade-off between the turn-on and the turn-off. There was a problem that it was difficult to improve. As a conventional MCT, there is a technique disclosed in JP-A-63-310171. This is a conventional 5-layer structure with pn
The four-layer pn structure simplifies the manufacturing process and reduces the short-circuit resistance of the emitter to enable high-speed turn-off, but the turn-off and turn-on trade-off described above are eliminated. The problem of difficulty has not been solved.

An object of the present invention is to provide a semiconductor device that improves the trade-off between turn-on and turn-off characteristics and further improves the turn-off characteristics as compared with the conventional structure.

[0006]

According to the present invention, a second conductivity type base region having a lower impurity concentration than that of the second conductivity type base region of a unit element (unit cell) constituting an MCT is formed. Thus, a turn-on initial operation region is provided, and the turn-on efficiency is improved to improve the trade-off of turn-on / turn-off characteristics. That is, the semiconductor device of the present invention includes a first semiconductor region of the first conductivity type exposed on a first main surface of a semiconductor substrate, and the first semiconductor region formed on the first semiconductor region. A second semiconductor region of the second conductivity type exposed on the first semiconductor layer, and a first semiconductor region formed on the second semiconductor region and exposed on the first main surface.
Formed in a third semiconductor region of conductivity type, a fourth semiconductor region of second conductivity type formed in the first semiconductor region and exposed to the first main surface, and in the first semiconductor region. Was
A fifth semiconductor region of the second conductivity type exposed on the second main surface of the semiconductor substrate, and a first electrode electrically connected to the third semiconductor region and the fourth semiconductor region. And a gate oxide film formed on the first main surface of the semiconductor substrate with at least a boundary between the first and second semiconductor regions, a boundary between the first and fourth semiconductor regions, and An off-gate region, which is a first region formed on the first semiconductor region sandwiched between these boundaries, a boundary between the first and second semiconductor regions, and a third and second semiconductor regions. A gate electrode having a second region-on-gate region formed on the boundary of the regions and the second semiconductor region sandwiched between these boundaries, and a gate electrode formed on the fifth semiconductor region. Two
It is characterized by including the electrode of. A portion of the second semiconductor region formed below the second region of the gate electrode is a sixth semiconductor region, and the impurity concentration thereof is the sixth semiconductor region of the second semiconductor region. The impurity concentration can be made lower than that of the portion other than the semiconductor region. The depth of the sixth semiconductor region from the first main surface of the semiconductor substrate is equal to the depth of the first semiconductor substrate of the third semiconductor region.
The depth can be almost equal to or shallower than the depth from the main surface of. The second semiconductor region surrounds the end of the third semiconductor region so that the sixth semiconductor region and the third semiconductor region do not contact each other except in the on-channel region. In the first main surface of the semiconductor substrate, the length of contact between the sixth semiconductor region and the third semiconductor region is the same as that of the other portion of the second semiconductor region and the third semiconductor region. It can be shorter than the contact length. The first semiconductor region and the fifth semiconductor region are respectively adjacent to the first semiconductor region and the first semiconductor region.
It is possible to have a seventh semiconductor region of the first conductivity type having an impurity concentration higher than that of the second semiconductor region. The fifth semiconductor region exposed on the second main surface is formed only directly below the second semiconductor region. The fifth semiconductor region exposed on the second main surface is formed immediately below the sixth semiconductor region.

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a first semiconductor region of a first conductivity type exposed on a first main surface of a semiconductor substrate in the semiconductor substrate, and the semiconductor substrate. Forming a second semiconductor region of the second conductivity type exposed on the first main surface of the first semiconductor region on the first main surface, and exposing the first main surface of the semiconductor substrate on the first main surface of the semiconductor substrate. Forming a third semiconductor region of one conductivity type in the second semiconductor region; forming a fourth semiconductor region having a second conductivity type in the first semiconductor region; Forming a fifth semiconductor region of the second conductivity type exposed on the second main surface of the semiconductor substrate in the semiconductor region; and electrically connecting the third semiconductor region and the fourth semiconductor region to each other. Forming a first electrode that is electrically connected, the third semiconductor region, and Adjacent to the first semiconductor region, the second
Forming a second conductivity type sixth semiconductor region having an impurity concentration lower than that of the second semiconductor region in the semiconductor region, and forming on the first main surface of the semiconductor substrate. A gate insulating film is formed, and at least the boundary between the first and second semiconductor regions, the boundary between the first and fourth semiconductor regions, and the second semiconductor region sandwiched between these boundaries. Formed on the first main surface of the semiconductor substrate and an off-gate region which is a first region, and a boundary between the third semiconductor region and the sixth semiconductor region via the gate insulating film; Forming a gate electrode having a boundary between the sixth semiconductor region and the first semiconductor region and an on-gate region, which is a second region formed on the sixth semiconductor region and sandwiched between these boundaries. And formed on the fifth semiconductor substrate A step of forming a second electrode, wherein in the step of forming the sixth semiconductor region and the step of forming the third semiconductor region, the second semiconductor region is formed. First of semiconductor substrate
Further comprising a step of forming a first conductivity type silicon epitaxial growth layer having a low impurity concentration on the main surface of the substrate, a step of selectively implanting impurities into the silicon epitaxial growth layer, and a step of heat-treating the semiconductor substrate. It is characterized by doing. Further, the MOS gate type thyristor of the present invention has the above semiconductor device as one element, and a plurality of the elements are integrated on one semiconductor substrate. This semiconductor substrate has a first off-channel region formed therein. Side and
And a second side surface adjacent to the first side surface and having an on-channel region formed therein.

[0008]

Since the initial turn-on region of the turn-on is formed away from the turn-off initial operation region, the impurity concentration in the base region can be partially changed to improve the turn-on characteristic. .. Further, since the low impurity concentration region of the base region is formed only in the surface region of the end portion, the turn-off characteristic is further improved.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a schematic perspective view of a unit cell of the semiconductor device of this embodiment. The back surface of the N ⁻ silicon semiconductor substrate 1, that is, the N ⁺ layer 5 and the P ⁺ layer 6 of the epitaxial growth layer formed on the second main surface are used as the N ⁺ buffer region 5 and the back surface P ⁺ emitter region 6, respectively.
An anode electrode 10 is formed on the back surface P ⁺ emitter region 6.
Since (A) is formed, the second main surface side of the semiconductor substrate has the same structure as the above-described conventional example (see FIG. 34).
On the other hand, on the first main surface side of the semiconductor substrate 1, the semiconductor substrate 1
A P-type base region 2 formed in the base region, an N-type emitter region 3 formed in the base region, and a P-type drain region 4 formed in the N ^- base region 1 of the semiconductor substrate. Has been done. These regions are N-type emitter region 3, P-type base region 2, N ^- base region 1 and P-type, respectively.
The type drain region 4 is exposed on the first main surface as third, second, first and fourth semiconductor regions. The second semiconductor region (P-type base region 2) includes the low-concentration region 17, and the third semiconductor region (N-type emitter region 3) is provided near the region exposed to the first main surface. And the first semiconductor region (N ^- base region 1). A gate electrode 9 (K) and a gate electrode 8 (G) are formed on the first main surface with a gate oxide film 7 interposed therebetween. This game
Gate electrode 8, the first and includes a second two areas, the first area Goff (Ofuge - DOO region), N ^- base - source region 1 and the P-type base - source region 2, N ^- The boundaries between the base region 1 and the P-type drain region 4 and the N sandwiched between these boundaries.
^- base - is formed on the source region 1, the first region Goff
The second region Gon which is spaced apart from the (Onge - DOO region), N ^- base - source region 1 and the P ^- base - source region 17, P ^-
It is formed on each boundary between the base region 17 and the N-type emitter region 3 and on the P ^- base region 17 sandwiched between these boundaries.

Next, the manufacturing process of this semiconductor device will be described. The N ⁻ type silicon semiconductor substrate 1 is prepared, and the second
Then, an N ⁺ layer and a P ⁺ layer are sequentially grown on the main surface of, to form an N ⁺ buffer region 5 and a back surface P ⁺ emitter region 6. Next, the semiconductor substrate is set as the N ^- base region 1, a silicon oxide film and a polysilicon film are formed on the first main surface of this substrate by a well-known technique, and the gate is selectively etched.
The oxide film 7 and the gate electrode 8 are formed. Then, impurities are diffused from the first main surface to the N ^- base region to form P.
^- forming a source region 17 - base. Then, N ^- base - other parts of the source region 1 and P ^- base - by diffusing impurity into source region 17, N ^- base - P-type drain region 4 in the source region 1, P ^- base - the source region 17 A P-type base region 2 is formed. further,
An N-type emitter region 3 is formed in the P-type base region 2. These diffusion regions are usually formed by ion-implanting impurities into the regions, and the gate electrode is used as a mask at that time. Therefore, when the N-type emitter region 3 is formed, this region is somewhat intruded into the inside of the first region Goff (off-gate region) of the gate electrode 8, so that the first region Goff is formed into the N-type emitter region. Area 3, P
Type base - source region 2, N ^- base - to be formed straddling source region 1 and the P-type drain region 4. However, the gate electrode 8 does not need to cover the N-type emitter region 3 since only the channel formed between these P-type regions is utilized in this portion. Therefore, as described above,
If the method using the gate electrode as a mask is not used, the first region Goff of the gate electrode is the P-type base region 2 and the N ^- base region.
It is sufficient to cover the drain region 1 and the P-type drain region 4. Then, a part of the silicon oxide film is opened and N
A cathode electrode 9 is formed on the type emitter region 3 and the P type drain region 4, and an anode electrode 10 is formed on the back surface of the semiconductor substrate. N ⁺ buffer area 5 and back surface P
^{The +} emitter region 6 can also be formed by diffusing impurities in the semiconductor substrate. The feature of the structure of the present invention is that the low concentration P ⁻ base region 17 is formed at the end of the P type base region 2 in the vertical portion of the cell of the semiconductor device. In this embodiment, the N ⁻ type silicon substrate is used, but the method of using the P ⁺ type silicon substrate can also be widely used. That is, the N ⁺ buffer region 5 and the N ⁻ base region 1 are sequentially grown on the P ⁺ type silicon semiconductor substrate to be the back surface P ⁺ type emitter region 6. Then, a P-type base region 2 and a P-type drain region 4 are formed on the surface of the N ^- base region 1 by diffusion, and an N-type emitter region 3 is formed in the P-type base region 2. Are formed by diffusion. The method of forming the other portions is the same as the method of this embodiment. This method is a common method. This method can also be used in the following examples.

Since the P ^- base region 17 is formed at the end of the P-type base region 2, even when the impurity concentration of the P-type base region 2 is increased to improve the turn-off characteristic, the P-type base region 2 is used as a switch at turn-on. Working N channel MO
Since the SFET is always formed in the P ⁻ base region 17, it does not raise the threshold voltage. Then, the turn-on operation operates with the N-type emitter region 3 near the P ⁻ base region as an initial operation region and spreads to the central portion of the N-type emitter region 1. That is, even if the impurity concentration of the P-type base region is changed, the N-channel MOSFET that works as a switch at the time of turn-on always operates at a constant threshold voltage, and the region of low turn-on and turn-on functions as an initial operation region The turn-on region expands and the on-voltage can be suppressed. As described above, according to the present invention, it is possible to improve the trade-off between turn-on and turn-off of MCT. Also, by adjusting the length of the cell in the vertical direction, the ratio of the length to the horizontal direction is adjusted, and by adjusting the base concentration, the trade-off between turn-on and turn-off is further improved, and the turn-off characteristic is also improved. Will be able to

The operation of the cell of the semiconductor device of this embodiment will be described with reference to FIGS. 2 to 4 show the turn-on operation. 2 is a perspective view showing this operation, and FIGS. 3 and 4 are sectional views of the cell in the YY 'direction of FIG. By biasing the anode A with a positive voltage and the cathode K with a negative voltage, and biasing the gate with a positive voltage, an inversion layer 18 is formed in the P ⁻ base region 17,
The N-channel MOSFET in this portion operates and electrons are injected from the N-type emitter region 3 to the N ⁻ base region 1.
As a result, holes 13 are injected from the back surface P ⁺ emitter region 6 to cause conductivity modulation, so that the P ⁻ base region 17 first turns on and then becomes an initial ignition region 19, and the turn on region goes to the cell center portion. The spreading cell will be completely turned on.

5 and 9 are perspective views of the cell of the semiconductor device for explaining the turn-off operation. Anode A
Biasing a positive voltage to the cathode K and negative voltage to the cathode K, and biasing the gate G negatively while the main current is flowing, the P-channel MOSFET operates to form the inversion layer 20, and the P-type base region 2 , P-type drain region 4 and the cathode electrode are short-circuited, and holes 16 in the main current are discharged from the cathode electrode 9. By this operation, the injection of electrons from the N-type emitter region 3 is stopped, the main current 14 (I) stops flowing, and the turn-off is completed.

FIGS. 6 and 8 are schematic plan views of the initial operation region when the semiconductor substrate is turned on and turned off. The turn-on initial operating region (initial firing region) 21 is both ends of the N-type emitter region 3 in the vicinity of the P ⁻ base region 17, and the turn-off initial operating region (initial arc extinguishing region) 22 is the N-type emitter region 3. Is a region in contact with the P-type base region 2. In other words, turn-on starts from both ends of the N-type emitter region and spreads to the center of the N-type emitter region.
4) is different from the operation mode starting from the N-type emitter region 3 which is in contact with the P base region 2 in both turn-on and turn-off. Referring to FIGS. 6, 7, 8 and 9, N-type emitter region 3 and P-type base region 2 and P ^- base are shown.
The state of the boundary with the scan area 17 will be described. 6 and 8
As shown in the plan view of the semiconductor substrate, the P-type base region 2 and the N-type emitter region 3 formed therein are elongated in the same direction. That is, the initial ignition region 21 at turn-on may be as short as possible, and the longer the initial operation region 22 at turn-off, the better the off characteristic. Therefore, by appropriately changing the ratio of these regions 21, 22, that is, the ratio of the short side (h) and the long side (H) of the N-type emitter region 3, either the ON characteristic or the OFF characteristic is emphasized. You can Of course, it is necessary that H> h. Although h in this embodiment is about 5 μm, it can be about 1 to 10 μm at present. In this embodiment, h / H is about ⅕, but it can be set to about 1/10 to improve the off characteristic, and the on characteristic is maintained even if the off characteristic is sacrificed to some extent. Has
It can be reduced to about 1/3. P-type base area 2
Ends, i.e., P so as to surround the short sides of the N-type emitter region 3 ^- base - source region 17 is formed, further, P-type base - source region 2, the end of the N-type emitter region 3 It is formed so as to surround the portion (see FIGS. 6 to 8) and is usually devised so that the N-type emitter region 3 and the P ^- base region 17 are not in contact with each other. Failure to do so, P ^- base - source region 1
7 contributes to the turn-off operation, and the energized region in which the holes discharged during the turn-off are hard to move easily remains, resulting in impairing the turn-off characteristic. Figure 7
FIG. 17 is a cross-sectional view showing a side surface of the gate electrode 8 of the MCT shown in FIG. 6 on which an on-gate region is formed.
FIG. FIG. 9 is a cross-sectional view showing the side surface on which the off-gate region is formed. The portion where the gate electrode 8 and the cathode electrode 9 overlap is insulated from each other by the interlayer insulating film 42.

The turn-on and turn-off characteristics of the present invention are as follows.
P ^- base - but is improved by the presence of the source region 17, MC
The current-voltage characteristic of T depends on the impurity concentration of the P ^- base region 17, as shown in FIG. The figure is a characteristic diagram in which the horizontal axis represents the on-voltage (V) and the vertical axis represents the current (A / cm ² ). Curves A, B, C and D show that the impurity concentration of the N-type emitter region 3 is 2 × 10 ²⁰ / cm ² and the impurity concentration of the P-type base region 2 is 1.0 × 10 ¹⁷ / cm ² , respectively.
cm ² , 2.0 × 10 ¹⁸ / cm ² , 4.0 × 10 ¹⁸ / c
Current when m ² and 5.0 × 10 ¹⁸ / cm ² −
It is a curve which shows a voltage characteristic. The lower the impurity concentration of the P ^- base region 17, the higher the current-voltage. That is, P
^{Since the} higher the impurity concentration of the base region 17 is, the higher the current can be obtained at the lower ON voltage, the provision of the P-type base region 2 as the on-gate region improves the ON characteristics. Will be done.

FIG. 17 is a perspective view of an MCT chip which is a semiconductor device of the present invention formed from a semiconductor substrate having a plurality of cells. The first major surface of the semiconductor substrate, the elongated P-type drain region 4, P ^- base - source region 17 laden P-type base - in a pair and a source region 2 form a plurality in a matrix, electrodes of each cell Are connected to each other to form a gate G and a cathode K of the chip on the surface of the semiconductor substrate. On one side of the figure, an off channel is formed in the N ^- base region 1 between the P-type base region 2 and the P-type drain region 4 below the off-gate region Goff of the gate electrode, and further adjacent to it. the side surfaces, gate - the gate electrode Onge - DOO region Gon of N lower ^- base - P between the source region 1 and N type emitter region 3 ^- base - to form an on-channel in the source region 17. The chip size is about 2 to 4 mm square in this embodiment.

Next, a second embodiment will be described with reference to FIGS. FIG. 10 is a schematic perspective view of the MCT of this embodiment, and FIGS. 11 and 12 are perspective views of the MCT for explaining turn-on and turn-off operations, respectively. In this structure, the N ⁻ type silicon semiconductor substrate used in the first embodiment is replaced with a P ⁻ type silicon semiconductor substrate. As in the previous embodiment, the second layer of the P ^-- type silicon semiconductor substrate 23 is formed.
A P ⁺ buffer region 28 and a back face N ⁺ emitter region 29 are formed on the main surface of the. Next, the gate oxide film 30 and the polysilicon gate electrode 31 are stacked on the first main surface of the semiconductor substrate, and then the impurities are diffused to form the N ⁻ base region 24, the N type base region 25, and the P type emitter. Area 26,
The N-type drain region 27 is formed. Then, a part of the gate oxide film is opened to form the anode electrode 32, and the cathode electrode 3 is formed on the back surface, that is, the second main surface.
3 is formed.

Next, the turn-on and turn-off operations will be described. The turn-on operation is positive for the anode 32,
By biasing the cathode 33 with a negative voltage and the gate 31 with a negative bias, the P-channel MOSFET operates and the inversion layer 36 is formed. Then, holes 34 are injected into the P ⁻ base region 23, and electrons 35 are injected from the back surface N ⁺ emitter region 29, so that conductivity modulation occurs in the P ⁻ base region 1 and it is turned on and a main current starts to flow. .. In the turn-off operation, the anode 32 is positively biased and the cathode 33 is negatively biased, and the gate 31 is positively biased while the main current 37 is flowing, thereby operating the N-channel MOSFET and forming the inversion layer 39.
Then, by short-circuiting the N-type base region 25, the N-type drain region 27 and the anode electrode 32, electrons 38 are discharged from the main current, the injection of holes from the P-type emitter region 26 is stopped, and the main current 37 becomes It will stop. That is, in the second embodiment, the carriers injected and discharged are opposite to those in the first embodiment, and the turn-on and turn-off operation characteristics are the same as those in the first embodiment.

Next, referring to FIGS. 13 to 15, the third
An example will be described. FIG. 13 is a schematic perspective view of the MCT,
14 and 15 are schematic perspective views of the MCT for explaining the turn-on and turn-off operations thereof. This structure is called an anode short structure, and is a structure in which the anode and the back surface N ⁺ region are short-circuited. A back surface P ⁺ emitter region 40 and an N ⁺ region 41 are formed on the second main surface side of the N ⁻ silicon semiconductor substrate 1, and then the gate oxide film 7 and the polysilicon gate electrode are formed on the first main surface. 8 is formed. Then, impurities are diffused from the first main surface into the semiconductor substrate to form the P ⁻ base region 17, the P type base region 2, the N type emitter region 3 and the P type drain region 4, and a part of the gate oxide film is formed. A hole is formed to form the cathode electrode 9, and the anode electrode 10 is formed on the back surface. The turn-on and turn-off operations are the same as in the first embodiment. However, since this structure is an anode short structure, at the time of turn-on P ^-
Holes are injected from the back surface P ⁺ emitter region 40 immediately below the base region 17 and turned on. And at the time of turn-off, because the back surface P ⁺ emitter region 40 directly beneath the N-type emitter region 3 are entered alternately and N ⁺ region, which is immediately below the P-type emitter region, contains no backside P ⁺ emitter region, a hole Disappears faster, and the structure makes it easier to turn off.

Next, a fourth embodiment will be described with reference to FIG. This is a schematic perspective view of the MCT, and the structure thereof is the same as that of the first embodiment of FIG. 1 except that the first region Goff (off gate region) of the gate electrode 8 is different. Same as MCT. In FIG. 1, the first area Gof
f was also formed on the N-type emitter region 3. This is because when the region 3 is formed by impurity diffusion,
Since the mask region is used as a mask, it is unavoidable that the emitter region 3 slightly goes under the gate as shown in FIG. However, in reality, this part is
Since it is only used for off
Is unnecessary (only the off channel formed in the N ^- base region 1 is required). Therefore, in this embodiment, the gate on the N-type emitter region 3 is removed and the gate is removed.
The oxide film 7 is exposed.

As described above, in the above embodiments, the MCT
As a self-arc-extinguishing device, the on-gate region and the off-gate region are separated, the efficiency of the off-gate portion is increased, and the turn-off characteristic is improved. However, even if an attempt is made to improve the turn-off characteristics by the above-mentioned method, if the element is completely turned off and reaches the conductive state, P
Even if the hole current component in the main current 14 is discharged to the cathode electrode 9 from the path of the type base region 2 to the P-channel inversion layer 20 to the P-type drain region 4, it is formed at a low concentration and becomes an on-gate region. In the P ⁻ base region 17, it is difficult to discharge the hole current component because of the high resistance of the discharge path, and it is difficult to completely turn off the element because the conduction state is maintained in this part.

Next, a fifth embodiment will be described with reference to FIG. This embodiment improves the turn-off characteristics by solving the problem in the first to fourth embodiments that it is difficult to turn off because the conductive state is easily maintained in the P ⁻ base region, and further,
This makes it easier to make a trade-off between turn-on and turn-off characteristics. That is, in the above-described embodiments, the P ⁻ base region 17 serving as the on-gate region is formed over the entire end portion of the P base region 2, but in this embodiment, the P-type base region 2 is formed below the on-gate region. However, the P ⁻ base region 1 is formed only on the surface of the P type base region 2 immediately below the on-gate region.
Form 7. This low impurity concentration P ⁻ base region 17
Is a part of the P-type base region 2 and is formed at the end thereof. The P ^- base region 17 is arranged below the second region (on-gate portion) Gon of the gate electrode 8, and the depth from the first main surface of the semiconductor substrate 1 is this region. 1
7 is almost equal to or shallower than the depth from the main surface of the N-type emitter region 3 adjacent to 7. The configuration of the other parts is the same as in FIG. This structure allows
Only the surface portion forming the on-channel region becomes the P ⁻ base region 17, and the P-type base region 2 is also formed immediately below the on-channel region. Therefore, at the time of turn-off, this portion also forms a part of the P-base region 2. Similarly, the current is easily cut off, and the turn-off characteristic can be improved.

Next, the operating principle (turn-on / turn-off) of the present invention will be described with reference to FIGS. First, the turn-on operation will be described. Figure 20
21 is a front view of the semiconductor substrate for explaining this operation.
22 is a side view and FIG. 22 is a plan view thereof. When the anode A is positively biased, the cathode K is negatively biased, and the gate G is positively biased, the P ⁻ base region 17 on the surface of the semiconductor substrate 1 is formed.
An N-channel inversion layer 18 is formed on the very surface, and electrons 12 are injected from the N-type emitter region 3 to the N ⁻ base region 1. As a result, holes 13 are formed from the back surface P ⁺ emitter region 6
Are implanted into the N ⁻ base region 1. Thus, N ^- conductivity modulation occurs in the base region 1 through the P-type base region 2 from the N-type emitter region 3, N ^- direct electron 12 are injected into the base region 1, the turn-on is the P ^- base region 17 Starting from the initial firing region 21 of the near N-type emitter region 3, the turn-on region spreads to the N-emitter center region, and the device turns on.

Next, the turn-off operation will be described. FIG. 23 is a front view of a semiconductor substrate for explaining this operation, FIG. 24 is a side view, and FIG. 25 is a plan view thereof. When the anode A is positively biased, the cathode K is negatively biased, and the gate G is negatively biased while the main current 14 is flowing, the N-channel inversion layer 18 formed at turn-on disappears, and the P-type base / P-type A P-channel inversion layer 20 is formed on the surface of the N ⁻ base region 1 between the drain regions,
The P-type base region 2 to the P-type drain region 4 to the cathode electrode 9 are short-circuited, and the holes 16 in the main current 14 are discharged from the cathode electrode 9. By this operation, the injection of electrons from the N-type emitter region 3 is stopped and the main current 14 stops flowing. The turn-off region starts from the initial arc extinguishing region 22 facing the P-type drain region 4 of the N-type emitter region 3, and finally spreads over the entire N-type emitter region 3 to turn off the device.

Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS. The figure shows P
FIG. 3 is a partial cross-sectional view of the semiconductor substrate centering on the type base and the P type drain region. As shown in FIG. 20, an N ⁺ buffer layer 5 and a back surface P ⁺ emitter layer 6 are formed on the second main surface of the N ⁻ semiconductor substrate 1, and further a normal diffusion technique such as ion implantation or solid phase diffusion is performed. Is used to form the P-type base region 2 and the P-type drain region 4 (FIG. 26). Then this P
A low impurity concentration P ⁻ silicon epitaxial layer 43 having a thickness of about 1 μm is grown on the surface of the semiconductor substrate 1 including the type base region 2 and the P type drain region 4 (FIG. 27). Next, for example, impurities are ion-implanted into the epitaxial layer 43 to form the P-type drain region 4 and the P ⁻ base region 17.
Then, the N-type emitter region 3 is formed, and the gate oxide film 7 and the polysilicon gate electrode 8 are further formed on the surface of the epitaxial layer 43. (FIG. 28). Then, the oxide film is selectively removed by etching to form the cathode electrode 9 thereon and the anode electrode 10 on the back surface.
As described above, by using the epitaxial growth layer, the P ⁻ base region 17 formed in the end portion of the P type base region 2 with the same diffusion depth as the P type base region in the above-described embodiment is replaced with the P type base region. Only the surface of the end portion in the region 2 can be formed.

Next, another method of forming the P ^- base area 17 will be described with reference to FIG. Illustration of the P-type drain region 4 is omitted. The steps up to FIG. 26 of the above method are common to this method. Then, the P-type base region 2 and P
A low impurity concentration N ⁻ silicon epitaxial layer 44 having a thickness of about 1 μm is grown on the surface of the semiconductor substrate 1 including the type drain region 4 and the like (FIG. 29A). Then, the semiconductor substrate 1 is heat-treated, so that the P-type impurities in the P-type impurity diffusion regions 2 and 4 are thermally diffused and the epitaxial layer 44.
And the epitaxial layer 44 on these regions 2, 4
Changes to the P ⁻ silicon epitaxial layer 43 (FIG. 29B). Therefore, this epitaxial layer 43
Then, impurities are selectively and selectively ion-implanted to form a P ^- base region 17, as shown in FIG.

Further, in another method, as shown in FIG. 29 (a), after the N ^-- silicon epitaxial layer 44 is formed, the semiconductor substrate is directly subjected to ion implantation without thermal diffusion treatment, A P ^- base region 17 shown in FIG. 28 is formed. In forming such a P ⁻ base region, a manufacturing method using an epitaxial growth layer has been described as an example, but it is also possible to form it by a method using buried diffusion or an adhesive wafer.

Next, a sixth embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. In this structure, the N ^- silicon semiconductor substrate used in the fifth embodiment is replaced with a P ^- silicon semiconductor substrate 23. A P ⁺ buffer region 28 and a back surface N ⁺ emitter region 29 are epitaxially grown on the second main surface. The next, by an impurity diffusion to the first main surface of the semiconductor substrate 23, N-type base - source region 25, which is a part of this region N ^- base - source region 24, P-type emitter region 26, N-type drain A region 27 is formed, and then a gate oxide film 30 and a polysilicon gate electrode 31 are laminated. Then, a part of the oxide film is opened to form an anode electrode (A) 32, and a cathode electrode (K) 33 is formed on the back surface (second main surface).
To form. In the turn-on operation, a positive voltage is applied to the anode 32, a negative voltage is applied to the cathode 33, and a negative voltage is applied to the gate 31, whereby the P-channel MOSFET operates and an inversion layer is formed. .. Then, P ^- base - source region 2
By injecting holes into 3 and injecting electrons from the back surface N ⁺ emitter region 29, conductivity modulation occurs in the P ^- base region 23, turning on and turning on the main current.
In the turn-off operation, the gate 31 is positively biased while the main current is flowing by biasing the anode 32 with a positive voltage and the cathode 33 with a negative voltage. Are discharged, and the injection of holes from the P-type emitter region 26 is stopped to stop the main current. N ^- base - scan the area under the 24 N-type base - source region 25 is also data - so contributes to turnoff operation, its operation is improved than the first embodiment.

Next, a seventh embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. This structure is called an anodic short structure as in FIG. 13, and has a structure in which the anodic electrode and the back surface N ⁺ region are shorted. A back surface P ⁺ emitter region 40 and a back surface N ⁺ region 41 are formed on the second main surface of the N ⁻ silicon semiconductor substrate 1, impurities are diffused from the first main surface to the semiconductor substrate 1, and a P type base is formed. Region 2, N-type emitter region 3, P-type drain region 4, and N-type emitter region 3 are formed to form a P ^- base region 17 having substantially the same diffusion depth. Then, a gate oxide film 7 and a polysilicon gate electrode 8 are laminated on the first main surface, and further, a part of the oxide film is opened to form a cathode electrode 9, and a back surface is formed on the back surface. An anode electrode is formed. The turn-on / turn-off operation is the same operation mode as that of the third embodiment shown in FIG. N ^- base - N-type base beneath the source region 17 - source region 2 even data - so contributes to turnoff operation, its operation is first
It is improved compared with the embodiment.

Next, an eighth embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. This structure is the same as that of FIG. 18, but the P ^- base region 17 is not formed on the entire end of the P-type base region 2, but only on the surface region of this end, P ^- base - P-type base beneath the source region 17 - source region 2, data - which acts as a turnoff region. Therefore, the turn-off operation is as shown in FIG.
It is improved from the fourth embodiment shown in FIG.

Next, a ninth embodiment will be described with reference to FIG. The figure is a schematic perspective view of the MCT of this embodiment. In the above embodiments, the gate electrodes 8 and 31 are the first electrodes.
Area Goff and the second area Gon, and these areas were integrated. However, in the present invention,
It is not necessary for the gate electrodes to be integrated;
The areas may be separated. As shown in this figure, the gate electrode 8 is separated into an off-gate region which is the first region Goff and an on-gate region which is the second region Gon. Although the structure of one cell is shown in this figure, this M
When the CT is actually used, a plurality of these cells, for example, arranged vertically and horizontally as shown in FIG. 17, are used as one semiconductor device. If you want to combine cells into one,
For example, the second region Gon is integrated in each cell row, but the first region Goff is separated for each cell. Therefore, each first region must be connected to each row by wiring such as Al while paying attention to insulation.

The fifth to ninth embodiments are intended to improve the turn-off characteristic which has been a problem in the first to fourth embodiments. In the first half of the embodiment, the impurity concentration of the P-type base region 2 and the P-type drain region 4 is increased, and the P-type base region formed at the time of turn-off.
The turn-off characteristics have been improved by a method of efficiently discharging holes by lowering the resistance of the hole current discharging path of the P-channel inversion layer-P-type drain region-cathode electrode. However, even if an attempt is made to improve the turn-off characteristics by this method, it is difficult to discharge the hole current component in the P ⁻ base region 17 which is formed at a low concentration and serves as an on-gate region, because the resistance of the discharge route is high, and in this portion. Since the conductive state is maintained, current tends to remain at turn-off. This has been a factor impeding the improvement of the turn-off characteristics. In the latter half of the embodiment, the P ⁻ base region 17 is formed only on the surface of the end of the P type base region 2. That is, by forming the P ⁻ base region 17 only on the surface of the end portion of the P-type base region 2 where the N-channel inversion layer is formed at the time of turn-on, the resistance of the hole current discharge path at the time of turn-on is reduced and the current is cut off. Making it easier.

Regarding its function and effect, FIG. 20 to FIG.
Will be described. As shown in the figure, the P ⁻ base region 17 is formed in the surface portion of the P type base region 2 up to the connection with the N type emitter region 3 and the junction of the N ⁻ base region 1. Therefore, in this structure, the P ⁻ base region 17 is formed only in the portion where the N-channel inversion layer 18 is formed at turn-on. Therefore, the element is biased positively to the anode and negatively to the cathode at turn-off, biases the gate negatively while the main current is flowing, and the N ⁻ base region between the P-type base region 2 and the P-type drain region 4 is The P-channel inversion layer 20 is formed on one surface, the P-type base region-P-type drain region-cathode electrode 9 is short-circuited, and the holes 16 in the main current are discharged from the cathode electrode 9.

By this operation, the injection of electrons from the N-type emitter region 3 is stopped. At this time, since the P ⁻ base region 17 is surrounded by the P type base region 2 at the junction with the N type emitter region 3 at the end of the P type base region 2, if the N channel inversion layer 18 at turn-on is closed. It is easy to stop the injection of electrons and the turn-off characteristic of the device is improved. Thus, since the P ⁻ base region 17 is only the surface portion of the end portion of the P type base region 2 and the periphery thereof is surrounded by the P type base region 2, the injection of the electron current is suppressed and the turn-off characteristic is improves. Regarding the turn-on characteristics, since the P ⁻ base region 17 is in the region where the N-channel inversion layer 18 is formed, the characteristics of the N-channel MOSFET are the same as in the first embodiment, and the electrons are generated in this N-channel inversion layer. The turn-on characteristic does not change because the N ^- base region 1 is sufficiently injected from 18.

The present invention can be applied to a double gate structure by using these embodiments other than the above-mentioned embodiments. Further, although silicon is used as the semiconductor material in the above-described embodiments, this use is one example, and other existing materials such as Ge and GaAs can be appropriately used. The impurity concentration of the P ^- base region formed in the surface region at the end of the P-type base region of the semiconductor device shown in the embodiment is 1.0 in order to maintain the turn-on characteristic. It is preferably × 10 ¹⁸ cm ^-3 or less.

[0036]

INDUSTRIAL APPLICABILITY As described above, the present invention provides the MCT target.
Since the initial operation regions of turn-off and turn-on are separated from each other, the impurity concentration of the base region can be changed depending on the location, and the turn-off / turn-on characteristic trace problem that has been a problem in the prior art can be obtained. It is possible to improve the turn-off efficiency while improving the turn-off efficiency.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic perspective view illustrating a turn-on operation of the semiconductor device of FIG.

3 is a cross-sectional view in the YY 'direction for explaining the turn-on operation of the semiconductor device of FIG.

4 is a cross-sectional view in the YY 'direction for explaining the turn-on operation of the semiconductor device of FIG.

5 is a schematic perspective view of a semiconductor device for explaining a turn-off operation of the semiconductor device of FIG.

FIG. 6 is a plan view of a semiconductor device for explaining the turn-on operation of the present invention.

FIG. 7 is a cross-sectional view of a semiconductor device illustrating a turn-on operation of the present invention.

FIG. 8 is a plan view of a semiconductor device illustrating a turn-off operation of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor device illustrating a turn-off operation of the present invention.

FIG. 10 is a perspective view of a semiconductor device according to a second embodiment of the present invention.

11 is a perspective view illustrating a turn-on operation of the semiconductor device of FIG.

12 is a perspective view illustrating a turn-off operation of the semiconductor device of FIG.

FIG. 13 is a perspective view of a semiconductor device according to a third embodiment of the present invention.

14 is a perspective view illustrating a turn-on operation of the semiconductor device of FIG.

15 is a perspective view illustrating a turn-off operation of the semiconductor device of FIG.

FIG. 16 is a characteristic diagram showing the impurity concentration dependence of the turn-on operation of the semiconductor device of the present invention.

FIG. 17 is a perspective view of a semiconductor device (MCT) having a plurality of cells according to the present invention mounted therein.

FIG. 18 is a perspective view of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 19 is a perspective view of a semiconductor device according to a fifth embodiment of the present invention.

20 is a front view illustrating a turn-on operation of the semiconductor device of FIG.

21 is a side view illustrating a turn-on operation of the semiconductor device of FIG.

22 is a plan view illustrating a turn-on operation of the semiconductor device of FIG.

23 is a front view illustrating the turn-off operation of the semiconductor device of FIG.

24 is a side view illustrating a turn-off operation of the semiconductor device of FIG.

25 is a plan view illustrating a turn-off operation of the semiconductor device of FIG.

FIG. 26 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 27 is a sectional view of a step of manufacturing the semiconductor device of FIG. 19.

28 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 29 is a sectional view of a step of manufacturing the semiconductor device of FIG.

FIG. 30 is a perspective view of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 31 is a perspective view of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 32 is a perspective view of a semiconductor device according to an eighth embodiment of the present invention.

FIG. 33 is a perspective view of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 34 is a schematic perspective view of a conventional semiconductor device (MCT).

FIG. 35 is a sectional view taken along the line XX ′ in FIG. 34, which is an explanatory view of the turn-on operation.

36 is a sectional view taken along line XX ′ in FIG. 34, which is an explanatory view of a turn-on operation.

FIG. 37 is a sectional view taken along the line XX ′ in FIG. 34, which is an explanatory view of the turn-off operation.

38 is a sectional view taken along the line XX ′ in FIG. 34, which is an explanatory view of the turn-off operation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 N ^- Semiconductor substrate 2 P-type base region 3 N-type emitter region 4 P-type drain region 5 N ⁺ buffer region 6 and 40 Back surface P ⁺ emitter region 7 and 30 Gate oxide film 8 and 31 Polysilicon gate electrode 9 and 33 Cathode electrodes 10, 32 an anode electrode 11,18,39 N-type inversion layer 12,35,38 electron current 13,16,34 hole current 14, 37 main current 15,20,36 P type inversion layer 17 P ^- base - scan Region (sixth region) 21 Initial ignition region 22 Initial arc extinguishing region 23 P ^- Semiconductor substrate 24 N ^- Base region 25 N-type base region 26 P-type emitter region 27 N-type drain region 28 P ⁺ buffer Region 29 Backside N ⁺ Emitter Region 41 Backside N ⁺ Region 42 Interlayer Insulating Film 43 P ^- Silicon Epitaxy Layer 44 N ^- Silicon Epitaxial Layer

Claims (10)

[Claims] 1. A first semiconductor region of a first conductivity type exposed on a first main surface of a semiconductor substrate, and a first semiconductor region formed on the first semiconductor region and exposed on the first main surface. A second semiconductor region of the second conductivity type, a third semiconductor region of the first conductivity type formed in the second semiconductor region and exposed to the first main surface, and the first semiconductor region of the first conductivity type. A second conductive type fourth semiconductor region formed in a semiconductor region and exposed on the first main surface; and a second conductive type fourth semiconductor region formed on the first semiconductor region and exposed on the second main surface of the semiconductor substrate. A second conductive type fifth semiconductor region, a first electrode electrically connected to the third semiconductor region and the fourth semiconductor region, and the first main surface of the semiconductor substrate. Is formed over the gate oxide film, at least the boundary between the first and second semiconductor regions, and the first and fourth semiconductor regions. A boundary between body regions and an off-gate region which is a first region formed on the first semiconductor region sandwiched by these boundaries, and the first and second regions.
A semiconductor region boundary, a boundary between the third and second semiconductor regions, and an on-gate region that is a second region formed on the second semiconductor region and sandwiched between these boundaries. A semiconductor electrode, and a second electrode formed on the fifth semiconductor region. 2. A portion of the second semiconductor region formed below the second region of the gate electrode is a sixth semiconductor region, and the impurity concentration thereof is the second semiconductor region. 2. The semiconductor device according to claim 1, wherein the impurity concentration is lower than the impurity concentration of the portion other than the sixth semiconductor region. 3. The depth of the sixth semiconductor region from the first main surface of the semiconductor substrate is substantially equal to the depth of the third semiconductor region from the first main surface of the semiconductor substrate. Or, it is shallower than that.
The semiconductor device according to. 4. The second semiconductor region surrounds an end of the third semiconductor region so that the sixth semiconductor region and the third semiconductor region are not in contact with each other except in an on-channel region. The semiconductor device according to claim 2 or 3, wherein 5. The first major surface of the semiconductor substrate,
The length of contact between the sixth semiconductor region and the third semiconductor region is shorter than the length of contact between the other portion of the second semiconductor region and the third semiconductor region. The semiconductor device according to any one of claims 2 to 4. 6. A seventh semiconductor region of a first conductivity type, which is adjacent to the first semiconductor region and the fifth semiconductor region and has a higher impurity concentration than the first semiconductor region. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device. 7. The fifth semiconductor region exposed on the second main surface is formed only directly under the second semiconductor region, according to any one of claims 1 to 5. The semiconductor device according to item 1. 8. The semiconductor device according to claim 7, wherein the fifth semiconductor region exposed on the second main surface is formed immediately below the sixth semiconductor region. 9. A step of forming a first conductivity type first semiconductor region exposed on a first main surface of a semiconductor substrate on the semiconductor substrate, and exposing the first main surface of the semiconductor substrate on the first main surface. Forming a second semiconductor region of the second conductivity type in the first semiconductor region, and a third semiconductor region of the first conductivity type exposed on the first main surface of the semiconductor substrate. Forming in the second semiconductor region, forming a fourth semiconductor region having a second conductivity type in the first semiconductor region, forming a semiconductor substrate of the semiconductor substrate in the first semiconductor region. A step of forming a fifth semiconductor region of the second conductivity type exposed on the second main surface; and a first electrically connected to the third semiconductor region and the fourth semiconductor region. Forming an electrode, adjoining the third semiconductor region and the first semiconductor region, and Forming a second semiconductor type sixth semiconductor region having an impurity concentration lower than the impurity concentration of the second semiconductor region in the second semiconductor region; Is formed on the surface through a gate insulating film, at least the boundary between the first and second semiconductor regions, the boundary between the first and fourth semiconductor regions, and the second sandwiched between these boundaries. First formed on the semiconductor region
An off-gate region, which is a region of the semiconductor substrate, and the first of the semiconductor substrate.
A boundary between the third semiconductor region and the sixth semiconductor region, a boundary between the sixth semiconductor region and the first semiconductor region, and a boundary between them are provided on the main surface with a gate insulating film interposed therebetween. Forming a gate electrode having an on-gate region which is a second region formed on the sandwiched sixth semiconductor region; and forming a second electrode formed on the fifth semiconductor substrate. In the step of forming the sixth semiconductor region and the step of forming the third semiconductor region, the first main part of the semiconductor substrate having the second semiconductor region formed therein. On the surface, a step of forming a first conductivity type silicon epitaxial growth layer having a low impurity concentration, a step of selectively implanting impurities into the silicon epitaxial growth layer, and an impurity in the silicon epitaxial growth layer. And a step of heat treating the ion-implanted substrate. 10. The semiconductor device according to claim 1 is used as one element, and a plurality of the elements are integrated on one semiconductor substrate, and this semiconductor substrate has an off-channel region formed therein. A MOS gate drive type thyristor comprising a first side surface and a second side surface adjacent to the first side surface and having an on-channel region formed therein.