JPS58151061A - Semiconductor device turned on or off - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

BACKGROUND OF THE INVENTION This invention relates to thyristors, and more particularly to thyristors that can be both turned on and turned off.

Thyristors are well-known semiconductor devices typically used as current switches to allow current to flow through a circuit and to interrupt this current. A thyristor "turns on" when it creates a high conductance path between its two terminals (ie, anode and cathode), and "turns off" when it creates a high resistance path between those two terminals.

A conventional conventional thyristor 10 is shown in the figure.

The thyristor 10 has q regions/2 where the conductivity type changes alternately.
．． /4. 1g, an anode 20 and a cathode 22, and a metal-oxide-semiconductor (MOS) turn-on structure 24, or more broadly, a conductor-insulator-semiconductor turn-on structure 24.

A MOS turn-on structure 24 includes a gate 26 and an insulating layer 2 separating the gate 26 from the semiconductor body of the thyristor 10.
8. Biasing gate 26 with a positive voltage above the threshold (with respect to cathode 22) causes the portion of P-type region 16 adjacent to insulating layer 28 to "invert" creating an inversion channel 30 that allows electrons to pass through. I can do it. For this reason,
Electrons from the cathode 22 can flow through an electron current path 32 from the N-type region 1-8 through the inversion channel 30 to the 1'UN-type region 14.

As is known, the thyristor 10 has an NPN transistor structure formed by an N-type region 14, a P-type region 16, and a QN-type region 18, and an NPN transistor structure formed by a P-type region 12, an N-type region 14, and a P-type region 16. It can be modeled as a PNP transistor structure and a λ transistor structure. These transistor structures are recombined with each other. That is, the collector of the NPN transistor structure (
Region 14) is coupled to the base of the PNP transistor structure (region 14), so that this base can be driven. The collector (region 16) of the PNP transistor structure is connected to the base (region 16) of the NPN transistor structure.
region 16), so that this base can be driven. Therefore, for this reason, the N-type region 14 (PN
P) When electrons are supplied to the transistor structure no pace),
Both the NPN and PNP transistor structures turn on regeneratively, thus turning on the thyristor 10.

It can operate as a thyristor and has a MOS on its top surface.
It is desirable to provide a semiconductor device having a turn-on structure and a turn-off structure on its F-plane. Although such a device has turn-off capability, it is simple to fabricate because each side of the device has only one electrode: the gate and the anode or cathode for the MOS turn-on or turn-off structure.

(Object of the Invention) Therefore, an object of the present invention is to provide a semiconductor device having a MOS turn-on structure on one surface and a MOS turn-off structure on the other surface.

Another object of the invention is to provide a semiconductor device that can act as either a thyristor or a field effect transistor (FET), thereby providing important advantages as described below.

(Summary of the invention) When realizing the object of this invention, a semiconductor material body 1, 1
A semiconductor device having a plurality of electrodes and a plurality of cells.

The semiconductor body includes regions of chin/, ot, tusk 3 and tusk q coupled one after another. The fang/fang 3 regions are of one conductivity type, and the oni and fang q regions are of the opposite conductivity type. The oni region is doped to a predetermined concentration at least in a portion adjacent to the fang 3 region.

The region of the fang 3 is doped to a substantially higher concentration than this predetermined doping concentration. What is the area of Sai/and Fang q?
3. The respective portions are doped to a substantially higher concentration than the doping concentration of the regions of No. 3.

The sai/and oni electrodes are electrically connected to the tusk/and oq regions, respectively.

The plurality of cells of the cell are constructed of conductor-insulator-semiconductor type means for transporting the majority carriers between the region of the column and the electrode of the cell. Each of the plurality of OFF cells is comprised of a conductor-insulator-semiconductor type means for transporting majority carriers between the yoke region and the on region.

In certain embodiments of the invention, the cell repeat distance of the plurality of cells of the fang is less than about the minimum thickness of the region of the semiconductor body.

The novel features of this invention are specifically described in the claims, but the structure, operation, and other objects and advantages of this invention will be better understood from the following description of the drawings. Good morning.

(Detailed Description of Specific Embodiments of the Invention) FIG. 12 schematically shows a semiconductor device 40 embodying the invention. Apparatus 40 includes turn-on cells 42,44.

It is appropriate to do these in the same way. Historically, device 40 includes turn-off cells 46, 48, which are also suitably implemented in the same manner. Therefore, cells 42, 46 on the left
Only this will be explained in detail below.

The semiconductor device 40 includes a region 5o, a region 52, a region 54, and a region 56. O/'s region 50 is separated from Fang 3 and Fang q regions 54, 56 by a spear region 52, and Spear q region 56 is separated from Fang/and Oni's region 5 by a third region 54.
0,52. Furthermore, the device 4o may be arranged to provide for other areas such as area 53 of area 53 of turn-off cell 48, area 3 of area 3 such as area 55 of 'A-3' of evening-on cell 44, and area 53 of area 53 of turn-off cell 48; It includes other areas such as area 57 of turn-on 1 cell 44. It is possible to interconnect the regions of the fang/tooth as shown at 5o and 53, and similarly it is possible to interconnect the regions of the fang/3 such as 54 and 55.

An NPN transistor structure is formed by the N-type cross region 52, the P-type 1.:3 region 54, and the N-type cross region 58. A PNP transistor structure is formed by the P-type spear region 5Q, the N-type tooth region 52, and the P-type spear region 54.

Typical doping concentrations (ie, number of dopant atoms per cubic centimeter) for various regions of semiconductor device 40 are of the following order:

Area 50 of tusk/(P+10 parts): 1018 or more Off area 52: / 0'6 or less Area 54 of fang 3: lO''7 or less Oq area 56: lO or more therefore For example, it can be said that the third region 54 has a doping concentration that is substantially higher than the doping concentration of the third region 52. "Substantially higher" or "substantially lower" means at least one digit.

It refers to a higher or lower degree.

The cathode 58, suitably in the form of a comb, is placed on the top surface of the device 40 and is in contact with the area 56 of the fangs t.

The anode 60, suitably in the form of a comb on the underside of the device 40, abuts the comb region 50.

Turn-on cell 42 connects gate 60 to gate 6
0 from the semiconductor body of device 40. The gate 60 is located at the location 62 where the junction 63 (between the areas 52 and 54 of the spear and fang 3) terminates near the insulating layer 61.
From the vicinity of (between areas 54 and 56 of spear 3 and fang q)
It overlaps above the region 54 of the fang 3 up to a point 64 where the bond 65 terminates near the insulating layer 61 .

Similar to the operation of the conventional turn-on structure 24 shown in FIG.
The third region 54 of the mold is inverted to create an inversion channel 66, which allows electrons to pass through.

The inversion channel 66 thus creates an ``electronic current path 67'' between the active region 56 and the off region 52. therefore,
Electrons from the cathode 58 can swamp into the passageway 67 and flow to the N-type counter region 52 that forms the base of the PNP transistor structure, regeneratively turning on both the PNP and NPN transistor structures. , thus turning on the dazzling port.

gate 60, insulating layer 61. and the portion of region 54 of t-3 that includes the reversal channel 66 constitutes what one skilled in the art would consider to be an MO8-type means for transporting multiple carriers between region 56 of fang q and region 52 of off. . This means is normally off.

The turn-on cell 42 can be made in various shapes when viewed from above, such as elongated, q-angled or rounded.

Turn-off cell 46 is comprised of a gate 68 , an insulating layer 70 , and preferably an N-type region 12 . Region 72 is in contact with fang region 50 and anode 60 . gate 68
is separated from the semiconductor body of device 40 by an insulating layer 70. The gate 68 is (jF/ and the off region 50
.
The area 50 of the fang l extends over the area 50 of the tooth l.

When gate 68 is biased with a positive voltage above the threshold (with respect to cathode 5B), insulating layer 70 in region 50 of
The portion immediately adjacent to is inverted, creating an inversion channel 78, which allows electrons to pass through.

Therefore, electrons from the off region 52 can flow into the distributed electron current path 80 through the inversion channel T8 and another region 72 to the anode 60.

For turn-off cell 46 to function properly, the electrical resistance of electron current path 80 must maintain a forward bias of junction 63 due to the flow of electrons in current path 80 within the energy band of the semiconductor material forming junction 63. It must be smaller than the value that limits it to about half of the gap voltage. This removes base drive from the PNP transistor structure, thereby turning off the NPN transistor structure, thereby allowing device 40 to be turned off. Generally, the lower the resistance of current path 80, the greater the current at which turn-off cell 46 can be turned off. Therefore, the appropriate value of the resistance of current path 80 is related in part to how much current the turn-off cell 46 needs to turn off.

The resistance of electron current path 80 is related in part to the resistance of inversion channel 78. The resistance value of channel 78 is
22 portions of the area 50 of the fang/containing the inversion channel are treated with dopant atomic number i o+ 7 per 7 cubic centimeters.
It can be reduced by doping to a lower concentration. Furthermore, the following design points contribute to the purpose of reducing the resistance of current path 80.

(1) As seen in the oni diagram, by shortening the horizontal dimension of the oni region 50, the total length of the current path 80 can be shortened.

(2) The overall length of the current path 80 can also be shortened by reducing the horizontal dimension of the reversing channel 78 when viewed from the oni diagram.

(3) By reducing the size 82 and making the shape of the cell 46 round or q-angled instead of elongated when viewed from below in the oni diagram, the size of the cell 46 is reduced. The resistance of the inversion channel 78 can be reduced by increasing the dimension of the channel 78 in the direction normal to the oni diagram compared to the area of the inversion channel 78 .

(4) By heavily doping the onion region 50 and the other region 72, the resistance value of these regions can be reduced. However, the doping concentration of region 50 should not be too large so that the forward drop of device 40 is not excessive.

From the above explanation, a person skilled in the art would understand that the turn-off cell 4
It would be possible to realize a semiconductor device having an electron current path 80 having an appropriate resistance value such that 6 can function properly.

Those skilled in the art will understand that the gate 68, the insulating layer 70, and the portion of the active region 50 that includes the inversion channel 78 are located between the active region 52 and the anode 60 (via another region 72).
It will be appreciated that it constitutes a MO8 type structure that transports electrons. This structure is normally off.

If the cell repeat distance (or cell width) 82.84 of turn-off cell 46 and turn-on cell 42, respectively, is approximately equal to or less than the minimum thickness 86 of N-type region 52, semiconductor device 40 operates as a thyristor. and FET
It can have two modes of operation. Therefore,
Inversion channel 66.781 between cathode 58 and anode 60
The electron current path of the device 40 (not shown in the figure, hereinafter referred to as the FET current path) through the 1% N-type polar region 52 allows a significant electron current to flow between the cathode 58 and the anode 60. It has a sufficient electrical conductivity to allow it to flow. Additionally, the turn-on cell 42 is aligned with the turn-off cell 46 to the male region 52 as shown to improve the conductivity of the FET current path in the male region 52, e.g., between the inverting channels 66, 78. It is desirable to maximize. Furthermore, over a distance of about IO to 50% of the cell repeat distance 84 of cell 42, gate 60 overlaps insulating layer 61 and insulating layer 61 is overlaid, as shown in region 88 between locations 62 and 90. It is desirable that the contact area 52 be in contact with the area 52 of .

The most preferable value for the above distance is 20%. In this way, the spreading resistance value in the upper region 52 of the FET current path is minimized. It is not necessary that the aforementioned distance between locations 62 and 90 be in a straight path. Conventional MO8 with a distance that falls within the range mentioned above.
An O8-on thyristor structure is created.

As will be appreciated by those skilled in the art, gates 60.68 are biased with positive voltages greater than their respective thresholds (thus creating an inverting channel 66.68) so that gates 60 and 68
By changing the magnitude of one or both of the voltages applied to FE
The conductivity of the T current path varies from a minimum value determined primarily by the resistance of the onion region 52 to substantially infinity (except in the case of low voltage devices 40). FET
When operating in this mode, the semiconductor device 40 is oriented in one direction (i.e., with the anode 6
current can be passed in either direction between the cathode 58 and the anode 60 (in contrast to the case where the cathode 58 is biased positively with respect to the cathode 58).

Figure 3 shows a graph of the current of the device versus time. This illustrates the various features that allow the thyristor and FET devices 40 to be turned on and turned off. To simplify the explanation of Figure 3, we will use the following definition.

fil "FET style" means that both gates 6o, 6
biased above the respective threshold pressures (ie, both inversion channels 66, 78 are present).

(2) "Thyristor turn-on style" means gate 6
0 is biased above its threshold voltage (inversion channel 66 is present).

+31 I-thyristor turn-off regime means that gate 68 is biased above its threshold voltage (inversion channel 78 is present).

Turn-on of the semiconductor device 40 proceeds in three stages. Period 11
At this stage, device 40 is in FET mode and device 4
The zero current rises to a maximum value of FET current determined by the resistance of the FET current path. As mentioned before,
This can be changed by changing the magnitude of one or both of the voltages. FE′
In the r mode, the device 40 acts as a multi-carrier device so that the period 1. can be very short. In the oni phase of period t2, the device 40 is still in FET mode, but
This step can be deleted if desired. In the third phase 1 of period t3, the device 40 turns on in a thyristor turn-on manner.

In this manner, the current in device 40 is initially small during the delay time and then increases rapidly during the rise time. Device 4
A zero current reaches the maximum current of the device in the thyristor turn-on state. This maximum value is highly dependent on the state of external circuitry (not shown) to which device 40 is connected.

Turn-off of device 40 proceeds in three stages.

The fang/phase occurs during periods t4 and t5. The length of period t4 can be adjusted by varying the magnitude of the voltage applied to gate 68. At the beginning of period t, the NPN and PNP transistor structures of device 40 are no longer operating in a regenerative manner, the current in device 40 drops rapidly during the fall time, and the holes in device 40 fall into the oni region. By recombining with electrons at 52, etc., it annihilates with a tail while it substantially disappears. During the turn-off phase during period 6, device 40 is kept in F'ET mode, but this phase can be eliminated if desired. period t
In the fang 3 stage of 7, the current in device 40 rapidly decreases to zero because device 40 operates in thyristor turn-off mode and the device acts as a majority carrier device when in F''ET mode.

A very important advantage in turning off a bimodal (both FET and thyristor type operation) device 40 is that it relaxes the design constraints on turn-off cells such as those shown at 46. That's true. This design constraint is that each turn-off cell is substantially identical to each other, requiring each to turn off the same amount of current at the same time during the thyristor turn-off regime. 7
If one turn-off cell operates more slowly than the other turn-off cells, it will conduct more current at a higher voltage and may overheat and be destroyed.

Upon turn-off, the device 4ofJ (operated in FET mode, all FET current paths C, not shown in the diagram) conducts electron current reliably and the aforementioned problems do not occur. When device 40 is then operated in a thyristor mode, its turn-off cell need only turn off a much reduced current, thus significantly reducing the aforementioned problem. The device 40 is the device 4
When first operated in FET mode (during turn-off) for a period sufficient to ensure that the holes in the device 40 are substantially exhausted, the turn-off cell ensures that the electron current in device 40 is turned off substantially simultaneously. , the above-mentioned problem does not occur.

Additionally, the bimodal (just described) turn-on and turn-off device 4o is particularly useful in current switching applications. This means that the turn-on and turn-off of a conventional thyristor is
In contrast to the rapid changes in device current whenever a PNP transistor begins (turns on) or ends (turns off) a regeneration action, device 40 has a more gradual or controlled This is because it can be turned on or off depending on the shape. Accordingly, the voltage transients generated across device 40 during bimodal turn-on or turn-off are significantly reduced. This reduces the need for expensive noise filters or snubbers.

When manufacturing semiconductor device 40, regions of fang/toe 3, such as regions 50, 52, 54, are removed using conventional techniques for manufacturing thyristors, where junctions 63 and 74 constitute the main voltage blocking junctions of device 40. Make it properly. Gates 60, 68 and their associated insulating layers and further regions 72 are suitably fabricated using conventional techniques for making FETs. Regions A-q, such as region 56, are suitably manufactured using either thyristor technology or FET technology.

In the best mode contemplated for carrying out the invention, the semiconductor device 40 includes an electrical short (not shown) between the cathode 58 and the region 54 forming the base of the NPN transistor structure. . This short circuit reduces the susceptibility of device 40 to being turned on by noise or thermal currents within the semiconductor body, and increases the turn-off speed of device 40.

This is because the short circuit redirects a portion of the hole current for driving the base of the NPN transistor structure and transfers it to the cathode 5.
8, where it recombines with the electrons from the cathode 58. Electrical short-circuits of this type are known per se. Furthermore, in the best mode, the semiconductor body of device 40 is comprised of silicon wafer.

Further details regarding Naturn-Off e-cells such as cell 46 are contained in United States patent application Ser. This patent application also describes a turn-off cell located in the upper portion of the semiconductor device. This is device 4
0, the turn-off speed can be further increased.

Although the invention has been described by way of example with respect to specific embodiments,
Many modifications will occur to those skilled in the art. For example, N
Applying the previous description of this invention, by using a P-type material instead of a mold material, changing the P-type material to an N-type material, and using an electron instead of an electron and an electron instead of an electron, the complementary It is possible to make shaped semiconductor devices. Additionally, although the device 40 can be fabricated by a Brenna diffusion process as illustrated in FIG. I can do it. These grooves can have different shapes, depending on whether selective or isotropic etching is used, as well as depending on the crystallographic orientation of the semiconductor body. . Those skilled in the art will also recognize the range of possible forms for g. As an example, suitable groove shapes can be found in V, A, F, F, and P in International Electro Devices Meeting Glue Print/Q79, 72, pp. gg to 92. V, Riv-no paper “D
As described in "Theoretical Comparison of Voltage and On-Resistance of MO8 and VMO8 Structures", it has a square shape with a flat bottom. Additionally, the onion region 52 is fabricated by doping the portion of the onion region 52 that contacts the fang/on region 50 to a substantially higher concentration than the other portions of the onion region 52 (as described above). can be made to become what is known by the name of the asymmetric device. It is, therefore, to be understood that the appended claims are intended to cover all such modifications that are possible within the scope of this invention.

[Brief explanation of the drawing]

The figure above is a simplified cross-sectional view of a conventional thyristor, showing a MOS turn-on structure on one side. Figure 3 is a simplified cross-sectional view of a semiconductor structure embodying the invention, and Figure 3 shows the current flow of the device versus time illustrating the controlled turn-on and turn-off of a semiconductor device according to an embodiment of the invention. FIG. Explanation of main symbols

Claims (1)

[Claims] l a) Fang /, Fang λ, Spear 3 and O.q that are combined one after another
, the region of the above-mentioned/and spear 3 is of one conductivity type, and the regions of the fang 2 and i4Z are of the opposite conductivity type, and the region of the fang 2 is adjacent to at least the region of the above-mentioned 3. The doped portion is doped to a predetermined concentration, the region 3 above is doped to a substantially higher concentration than the predetermined doping concentration, and the regions 1 and q are both doped to a predetermined doping concentration. a body of semiconductor material such as to include a respective portion doped to a substantially higher concentration than the concentration;
b) fangs/tooths electrically connected to the areas of the spear l and the spear q, respectively;
C) each cell of which is comprised of conductor-insulator-semiconductor type means for transporting multiple carriers between the +2 region and the +2 electrodes; d) a plurality of cells, each cell comprising a male conductor-insulator-semiconductor type means for transporting a plurality of carriers between the region of the preceding paragraph 9 and the region of the shaft. multiple σ)
A semiconductor device having a cell. (c) In the semiconductor device according to claim 1, the cell repetition distance of the plurality of cells of the first part is smaller than approximately the minimum thickness of the second part of the second part, and A semiconductor device in which the cell repeat distance of the cells is less than about the minimum thickness of the second region. 3. In the semiconductor device according to the claims, the plurality of cells described in the preceding paragraph are aligned with the plurality of cells of the second part with respect to the region of the second part. Device. q A semiconductor device according to claim 1, in which the conductor-insulator-semiconductor means described above constitutes a normal means. 5. In the semiconductor device set forth in claim q, the conductor-insulator-semiconductor type means of
and another region of an opposite conductivity type provided in the main body adjacent to the ten regions. 18. The semiconductor device according to claim 17, wherein the male conductor-insulator-semiconductor type means constitutes normally off means. 7. In the semiconductor device according to claim 1, the conductor-insulator-semiconductor type means has an insulating layer adjacent to the region mentioned above, and in the vicinity of the insulating layer. A semiconductor device in which a portion of the region has a substantially lower doping concentration than the remainder of the region. g. In the semiconductor device as set forth in claim (e)/(e), the conductor-insulator-semiconductor type means of said unit is composed of an electrode and an insulating layer separating said electrode from said main body, and A semiconductor device in which the electrodes are stacked on top of each other, and the insulating layer is in contact with the region of the spear λ over a distance of about 10 to 5θ% of the cell repetition distance of the plurality of cells. 9. In the semiconductor device according to claim 17, an electrode of the conductor-insulator-semiconductor type means of the tooth piece overlaps an insulating layer of the conductor-insulator-semiconductor type means of the tooth piece. and the insulating layer is approximately equal to the cell repeat distance of the plurality of male cells. The semiconductor device is in contact with the region of the fang over a distance of 1. A semiconductor device according to claim 1, wherein the body of semiconductor material is comprised of a silicon wafer. // The semiconductor device according to claim 2, wherein the - conductivity type is P type and the opposite conductivity type is f) SN type. /2. In a method for turning on a semiconductor device according to claim 2 or 3, both of the conductor-insulator-semiconductor means described above are used for a predetermined period of time. and then deactivating at least said conductor-to-semiconductor means. /31% In the method for turning off a semiconductor device as set forth in claim 3, the method comprises activating both the on/off conductor-insulator-semiconductor means for a predetermined period of time. , and then deactivating said conductor-insulator-semiconductor type means. /da Claims: In the method described in Clause 3,
A method in which the predetermined period is long enough to substantially remove carriers of one conductivity type within a semiconductor device.