KR100309136B1 - Method for manufacturing transistor of semiconductor device - Google Patents
Method for manufacturing transistor of semiconductor device Download PDFInfo
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- KR100309136B1 KR100309136B1 KR1019950065725A KR19950065725A KR100309136B1 KR 100309136 B1 KR100309136 B1 KR 100309136B1 KR 1019950065725 A KR1019950065725 A KR 1019950065725A KR 19950065725 A KR19950065725 A KR 19950065725A KR 100309136 B1 KR100309136 B1 KR 100309136B1
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- South Korea
- Prior art keywords
- layer
- film
- silicon
- photoresist film
- silicon nitride
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- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims 2
- 238000009792 diffusion process Methods 0.000 claims 1
- 108091008695 photoreceptors Proteins 0.000 claims 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
- H01L29/66856—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET with an active layer made of a group 13/15 material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
Abstract
Description
본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 특히 MES(Metal Semiconductor)FET의 제조 공정에서 게이트 전극의 폭을 감소시킬 수 있도록 한 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly, to a transistor manufacturing method of a semiconductor device capable of reducing the width of a gate electrode in a manufacturing process of a metal semiconductor (MES) FET.
일반적으로 MESFET는 초고주파 전력용 소자에 이용되며, 높은 주파수 특성,큰 이득 및 저 잡음 특성을 얻기 위하여 게이트 전극을 T 형으로 형성한다. 이는 기판에 접촉되는 게이트 전극의 폭이 감소될수록 높은 주파수 특성을 얻을 수 있으며. 상부층과의 접속(Contact)이 용이하기 때문이다. 그러나 현재의 사진 장비를 이용하여 형성할 수 있는 패턴의 임계 치수는 0.5 μm 정도이기 때문에 상기 특성들을 향상시 킬 수 있는 게이트 전극을 형성하기 어렵다.In general, MESFETs are used in ultra-high frequency power devices, and the gate electrodes are formed in a T-shape to obtain high frequency characteristics, large gain, and low noise characteristics. This results in high frequency characteristics as the width of the gate electrode in contact with the substrate is reduced. This is because the contact with the upper layer is easy. However, since the critical dimension of the pattern that can be formed using current photographic equipment is about 0.5 μm, it is difficult to form a gate electrode that can improve the above characteristics.
따라서 본 발명은 패터닝된 감광막의 측벽에서 균일한 층덮힘을 이루는 실리콘 질화막 및 실리콘 산화막을 이용하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 트랜지스터 제조 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a transistor of a semiconductor device which can solve the above disadvantages by using a silicon nitride film and a silicon oxide film having a uniform layer covering on the sidewalls of the patterned photosensitive film.
상기한 목적을 달성하기 위한 본 발명은 반절연성 갈륨 아세나이드층, 활성화층 및 저항성 접촉층이 순차적으로 적층된 구조의 기판상에 제 1 감광막, 실리콘층 및 제 2 감광막을 순차적으로 형성한 후 상기 제 2 감광막을 패터닝하는 단계와, 상기 단계로부터 전체 상부면에 실리콘 질화막 및 실리콘 산화막을 순차적으로 형성하는 단계와, 상기 단계로부터 상기 제 2 감광막의 표면이 노출되는 시점까지 상기 실리콘 산화막 및 실리콘 질화막을 전면 식각하는 단계와, 상기 단계로부터 상기 패터닝된 제 2 감광막 및 상기 제 2 감광막의 측벽에 잔류된 상기 실리콘 산화막 및 실리콘 질화막을 식각 방지층으로 이용한 식각 공정으로 노출된 부분의 상기 실리콘층, 제 1 감광막 및 소정 두께의 저항성 접촉층을 순차적으로 식각하여 콘택 홀을 형성하는 단계와, 상기 단계로부터 잔류된 상기 실리콘 산화막 및 실리콘 질화막을 제거하는 단계와, 상기 단계로부터 상기 콘택 홀이 매립되도록 금속을 증착하여 T형 구조를 갖는 게이트 전극을 형성하는 단계와, 상기 단계로부터 잔류된 상기 제 2 감광막, 실리콘층 및 제 1 감광막을 제거하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is formed by sequentially forming a first photosensitive film, a silicon layer and a second photosensitive film on a substrate having a structure in which a semi-insulating gallium arsenide layer, an activation layer and an ohmic contact layer are sequentially stacked. Patterning a second photoresist film; sequentially forming a silicon nitride film and a silicon oxide film on the entire upper surface from the step; and from the step until the surface of the second photoresist film is exposed, the silicon oxide film and the silicon nitride film are formed. Etching the entire surface and the silicon photosensitive layer and the first photosensitive layer of the portion exposed by the etching process using the silicon oxide film and the silicon nitride film remaining on the sidewalls of the patterned second photoresist film and the second photoresist film as an etch stop layer. And sequentially etching the ohmic contact layer having a predetermined thickness to form a contact hole. Removing the remaining silicon oxide film and silicon nitride film from the step; depositing a metal so as to fill the contact hole from the step; forming a gate electrode having a T-type structure; And removing the second photosensitive film, the silicon layer, and the first photosensitive film.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제 1A 내지 제 1F 도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도로서,1A to 1F are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
제 1A 도는 반절연성 갈륨 아세나이드(GaAs)층(1), 활성화(Active)층(2) 및 저항성 접촉(Ohmic Contact)층(3)이 순차적으로 적층된 구조의 기판(4)상에 제 1 감광막(5), 실리콘층(6) 및 제 2 감광막(7)을 순차적으로 형성한 후 상기 제 2 감광막(7)을 패터닝한 상태의 단면도로서, 상기 실리콘층(6)은 상기 제 2 감광막(7)을 패터닝하기 위한 현상(Develope) 공정시 상기 제 1 감광막(5)이 손실되는 것을 방지하기 위한 층이며, 상기 제 1 감광막(5)의 두께는 게이트 전극의 높이를 제어하는데 이용된다. 또한 상기 활성화층(2) 및 저항성 접촉층(3)은 상기 갈륨 아세나이드층(1)을 애피택셜(Epitaxial) 성장시켜 형성 하며, 상기 저항성 접촉층(3)에는 예를들어 N+형의 불순물 도핑 농도를 갖고, 상기 활성화층(2)에는 N형의 불순물 도핑 농도를 갖는다.1A or 1st on a substrate 4 having a structure in which a semi-insulating gallium arsenide (GaAs) layer 1, an active layer 2, and an ohmic contact layer 3 are sequentially stacked. A cross-sectional view of a state in which the second photoresist film 7 is patterned after the photoresist film 5, the silicon layer 6, and the second photoresist film 7 are sequentially formed, and the silicon layer 6 is the second photoresist film ( A layer for preventing the first photoresist film 5 from being lost during the development process for patterning 7), and the thickness of the first photoresist film 5 is used to control the height of the gate electrode. In addition, the active layer 2 and the ohmic contact layer 3 are formed by epitaxially growing the gallium arsenide layer 1, and the ohmic contact layer 3 is, for example, doped with an N + type impurity. Concentration, and the activation layer 2 has an N-type impurity doping concentration.
제 1B 도는 전체 상부면에 실리콘 질화막(8) 및 실리콘 산화막(9)을 순차적으로 형성한 상태의 단면도로서, 이때 상기 패터닝된 제 2 감광막(7)의 측벽에서 상기 실리콘 질화막(8) 및 실리콘 산화막(9)은 균일한 층덮힘을 가진다.1B is a cross-sectional view of a silicon nitride film 8 and a silicon oxide film 9 sequentially formed on the entire upper surface thereof, wherein the silicon nitride film 8 and the silicon oxide film are formed on sidewalls of the patterned second photosensitive film 7. (9) has a uniform layer covering.
제 1C 도는 반응성 이온 식각(RIE) 방법으로 상기 제 2 감광막(7)의 표면이 노출되는 시점까지 상기 실리콘 산화막(9) 및 실리콘 질화막(8)을 전면 식각한 후상기 패터닝된 제 2 감광막(7) 및 상기 제 2 감광막(7)의 측벽에 잔류된 상기 실리콘 산화막(9) 및 실리콘 질화막(8)을 식각 방지층으로 이용하여 노출된 부분의 상기 실리콘층(6) 및 제 1 감광막(5)을 식각하므로써 콘택 홀(11)이 형성된 상태의 단면도로서, 이때 상기 노출된 부분의 상기 저항성 접촉층(3)도 소정 두께 식각된다. 여기서 상기 패터닝된 제 2 감광막(7)의 측벽에 잔류된 상기 실리콘 질화막(8) 및 실리콘 산화막(9)의 두께가 균일하기 때문에 상기 콘택홀(11)의 넓이가 정확하게 조절될 수 있다.After etching the silicon oxide film 9 and the silicon nitride film 8 until the surface of the second photoresist film 7 is exposed by 1C or reactive ion etching (RIE), the patterned second photoresist film 7 And the silicon oxide film 9 and the first photosensitive film 5 of the exposed portion using the silicon oxide film 9 and the silicon nitride film 8 remaining on the sidewalls of the second photosensitive film 7 as an etch stop layer. A sectional view of the contact hole 11 formed by etching, wherein the ohmic contact layer 3 of the exposed portion is also etched by a predetermined thickness. In this case, since the thicknesses of the silicon nitride film 8 and the silicon oxide film 9 remaining on the sidewalls of the patterned second photoresist film 7 are uniform, the width of the contact hole 11 can be accurately adjusted.
제 1D 도는 잔류된 상기 실리콘 산화막(9) 및 실리콘 질화막(8)을 제거한 상태의 단면도이고, 제 1E 도는 상기 콘택 홀(11)이 매립되도록 금속을 증착하여 T 형 구조를 갖는 게이트 전극(10)을 형성한 상태의 단면도로서 상기 증착된 금속과 노출된 상기 활성화층(2)의 계면에서는 쇼트키(Shottky Contact) 접촉이 발생되며, 상기 패터닝된 저항성 접촉층(3)은 소오스 및 드레인 영역으로 이용된다.1D is a cross-sectional view of the remaining silicon oxide film 9 and silicon nitride film 8 removed, and FIG. 1E is a gate electrode 10 having a T-type structure by depositing a metal so that the contact hole 11 is buried. Is a cross-sectional view of forming a Schottky contact at the interface between the deposited metal and the exposed activation layer 2, and the patterned ohmic contact layer 3 serves as a source and a drain region. do.
제 1F 도는 잔류된 상기 제 2 감광막(7), 실리콘층(6) 및 제 1 감광막(5)을 제거한 상태의 단면도이다. 상기 이와 같은 방법을 이용하면 0.6 μm 이상의 임계 치수를 갖는 마스크를 이용하여 0.34 μm 이하의 선폭을 갖는 게이트 전극(10)을 형성할 수 있다.FIG. 1F is a cross-sectional view of a state in which the second photosensitive film 7, the silicon layer 6, and the first photosensitive film 5 are removed. Using this method, the gate electrode 10 having a line width of 0.34 μm or less may be formed using a mask having a critical dimension of 0.6 μm or more.
상술한 바와 같이 본 발명에 의하면 패터닝된 감광막의 측벽에서 균일한 층덮힘이 이루어지도록 실리콘 질화막 및 실리론 산화막을 이용하므로써 집속 이온 빔 묘사 장치, 전자선 묘사 장치와 같은 고가의 장비를 사용하지 않고 임계 치수보다 작은 폭을 갖는 게이트 전극을 형성할 수 있다. 그러므로 높은 주파수 특성, 큰이득 및 저 잡음 특성을 갖는 트랜지스터를 제조할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the silicon nitride film and the silon oxide film are used to uniformly cover the sidewalls of the patterned photoresist layer, thereby avoiding the use of expensive equipment such as a focused ion beam description device and an electron beam description device. It is possible to form a gate electrode having a smaller width. Therefore, there is an excellent effect of manufacturing a transistor having high frequency characteristics, large gain and low noise characteristics.
제 1A 내지 제 1F 도는 본 발명에 따른 반도체 소자의 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도.1A to 1F are cross-sectional views of a device for explaining a transistor manufacturing method of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols on the main parts of the drawings
1: 갈륨 아세나이드층 2: 활성화층1: gallium arsenide layer 2: active layer
3: 저항성 접촉층 4: 기판3: resistive contact layer 4: substrate
5: 제 1 감광막 6: 실리콘층5: 1st photosensitive film 6: silicon layer
7: 제 2 감광막 8: 실리콘 질화막7: 2nd photosensitive film 8: silicon nitride film
9: 실리콘 산화막 10: 게이트 전극9: silicon oxide film 10: gate electrode
11: 콘택 홀11: contact hall
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950065725A KR100309136B1 (en) | 1995-12-29 | 1995-12-29 | Method for manufacturing transistor of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950065725A KR100309136B1 (en) | 1995-12-29 | 1995-12-29 | Method for manufacturing transistor of semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| KR970053058A KR970053058A (en) | 1997-07-29 |
| KR100309136B1 true KR100309136B1 (en) | 2003-07-12 |
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| KR1019950065725A KR100309136B1 (en) | 1995-12-29 | 1995-12-29 | Method for manufacturing transistor of semiconductor device |
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| KR100323694B1 (en) * | 1999-05-28 | 2002-02-07 | 구자홍 | method for fabricating a T-gate |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4341850A (en) * | 1979-07-19 | 1982-07-27 | Hughes Aircraft Company | Mask structure for forming semiconductor devices, comprising electron-sensitive resist patterns with controlled line profiles |
| JPS60145673A (en) * | 1984-01-09 | 1985-08-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH03165526A (en) * | 1989-11-24 | 1991-07-17 | Toshiba Corp | Manufacture of field effect transistor |
| JPH05136179A (en) * | 1991-11-12 | 1993-06-01 | Toshiba Corp | Manufacture of field-effect transistor |
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1995
- 1995-12-29 KR KR1019950065725A patent/KR100309136B1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4341850A (en) * | 1979-07-19 | 1982-07-27 | Hughes Aircraft Company | Mask structure for forming semiconductor devices, comprising electron-sensitive resist patterns with controlled line profiles |
| JPS60145673A (en) * | 1984-01-09 | 1985-08-01 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH03165526A (en) * | 1989-11-24 | 1991-07-17 | Toshiba Corp | Manufacture of field effect transistor |
| JPH05136179A (en) * | 1991-11-12 | 1993-06-01 | Toshiba Corp | Manufacture of field-effect transistor |
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| Publication number | Publication date |
|---|---|
| KR970053058A (en) | 1997-07-29 |
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