JPH11345962A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, wherein the leakage current from the electrode such as a gate electrode is suppressed. SOLUTION: This is the semiconductor device wherein a channel layer 2 comprising undoped In0.2 Ga0.8 As and having large electron affinity, and electron supply layer 4 comprising Al0.2 Ga0.8 As wherein Si, whose electron affinity is smaller than the channel layer 2, are formed. In this case, a contact preventing layer 5 which protrudes sideward than the channel layer 2 and electron supply layer and comprises Al0.4 Ga0.6 As that is undraped or doped at the concentration lower than the electron supply layer, is formed. A gate electrode 6 is formed on this contact preventing layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as a field effect transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A heterojunction field effect transistor using a compound semiconductor has a high electron mobility and has been applied in various fields as a device used for signals in a microwave or millimeter wave band in recent years.

In general, a heterojunction transistor uses an epitaxial growth substrate, and a doping layer is formed during epitaxial growth. When a field-effect transistor is manufactured using such a substrate, it is necessary to separate elements between the transistors. As a method for separating the elements, a method using mesa etching is generally used.

FIG. 7 is a sectional view showing a structure of a gate electrode portion of a conventional field effect transistor. Note that the cross-sectional view shown in FIG. 7 is a cross-sectional view of the field-effect transistor when the gate electrode G is cut along the broken line AA ′ in FIG. 8 when viewed from above. In FIG. 8, S is a source electrode, and D is a drain electrode.

[0005] This conventional field-effect transistor is composed of a semiconductor substrate (not shown) made of InP or the like.
A buffer layer 11 such as an lAs layer, a channel layer 12 such as an InGaAs layer, and an electron supply layer 13 such as an n-type InAlAs layer.
Are sequentially formed in a high electron mobility transistor (HEM).
T) and after element isolation by mesa etching,
This is a structure in which a gate electrode 14 is formed on the electron supply layer 13.

However, in the field-effect transistor shown in FIG. 7, the wiring portion 14a to the gate electrode 14 comes into contact with the side wall of the highly doped electron supply layer 13 and the side wall of the channel layer 12 having a narrow band gap. Therefore, there is a problem in that the gate leakage current increases, and as a result, the gate breakdown voltage deteriorates and the operating characteristics of the transistor deteriorate.

On the other hand, in a device such as a high electron mobility transistor comprising an electron supply layer and a channel layer, as shown in Japanese Patent Application Laid-Open No. 4-321237, a band gap is narrow at a mesa step. There has been proposed a method of suppressing an increase in gate leak current by side-etching a channel layer so as to cause overhang.

FIG. 9 is a sectional view showing a structure of a gate electrode portion of the high electron mobility transistor. Note that FIG.
In the cross-sectional view shown in FIG.
It is sectional drawing at the time of dividing along A '.

[0009] The high electron mobility transistor shown in FIG. 9 is obtained by forming InA on a semi-insulating substrate (not shown) of InP or the like.
A buffer layer 15 such as an lAs layer, a channel layer 16 such as an InGaAs layer, and an electron supply layer 17 such as an n-type InAlAs layer.
Are sequentially formed, and after the elements are separated by mesa etching, the channel layer 16 is side-etched, and then the gate electrode 18 is formed on the electron supply layer 17.

However, also in the structure shown in FIG. 9, as shown in FIG. 10, a region where electrons remain, that is, depletion occurs in a portion of the electron supply layer 17 above the side-etched region 161 of the channel layer 16. There is a problem that a region 171 where the operation is not performed occurs, and as a result, the gate breakdown voltage, especially the breakdown voltage does not become sufficiently large.

[0011]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and has as its object to provide a semiconductor device in which leakage current from an electrode such as a gate electrode is suppressed and a method of manufacturing the same. It is the purpose.

It is a further object of the present invention to provide a semiconductor device having a structure in which the generation of an undepleted region in the electron supply layer is suppressed, and a method of manufacturing the same.

[0013]

According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device having a channel layer having a high electron affinity on a semiconductor substrate and an electron supply layer having a lower electron affinity than the channel layer, an upper portion of the channel layer projects laterally from the channel layer and is undoped or A contact prevention layer doped at a lower concentration than the electron supply layer is formed, and an electrode is formed on the contact prevention layer.

In the semiconductor device having such a configuration, the electrode wiring portion extending from the electrode to the upper surface of the substrate is prevented from coming into contact with the channel layer due to the projection of the contact prevention layer, and the leakage current from the electrode to the channel layer is reduced. .

Further, according to the present invention, in a semiconductor device having a channel layer having a high electron affinity on a semiconductor substrate and an electron supply layer having an electron affinity lower than the channel layer, the channel layer and the electron supply layer At the top of
A contact prevention layer projecting laterally from the channel layer and the electron supply layer, undoped or doped at a lower concentration than the electron supply layer is formed, and an electrode is formed on the contact prevention layer. I do.

In the semiconductor device having such a structure, the electrode wiring portion extending from the electrode to the upper surface of the substrate is prevented from coming into contact with the channel layer and the electron supply layer due to the projection of the contact prevention layer. Leakage current to the layer is reduced.

Further, according to the semiconductor device of the present invention, a channel layer having a high electron affinity is formed on a semiconductor substrate, and an electron supply layer having a lower electron affinity than the channel layer is formed on the channel layer. In the above, on the electron supply layer, a contact prevention layer protruding laterally than the channel layer and the electron supply layer, undoped or doped at a lower concentration than the electron supply layer is formed, and on the contact prevention layer An electrode is formed.

In the semiconductor device having such a configuration, the electrode wiring portion extending from the electrode to the upper surface of the substrate is prevented from coming into contact with the channel layer and the electron supply layer due to the protrusion of the contact prevention layer. Leakage current to the layer is reduced.

In the semiconductor device according to the present invention, a channel layer having a higher electron affinity is formed on a semiconductor substrate, and a channel layer having a lower electron affinity than the channel layer is formed on the channel layer.
(1) In a semiconductor device having an electron supply layer formed thereon, the semiconductor layer protrudes laterally from the channel layer and the first electron supply layer on the first electron supply layer, and is undoped or doped at a lower concentration than the electron supply layer. A contact prevention layer formed thereon, a second electron supply layer having a smaller electron affinity than the channel layer is formed on the contact prevention layer, and an electrode is formed on the second electron supply layer. And

In the semiconductor device having such a configuration, the electrode wiring portion extending from the electrode to the upper surface of the substrate is prevented from coming into contact with the channel layer and the first electron supply layer due to the protrusion of the contact prevention layer. Leakage current to the first electron supply layer is reduced. Moreover, in the second electron supply layer located closer to the electrode than the contact prevention layer, the area that is not depleted is reduced. Further, since the electron supply layer has a two-layer structure of the first electron supply layer and the second electron supply layer, the thickness of each of the first and second electron supply layers can be reduced, and the electron supply layer is depleted. It will be easier.

Further, in the semiconductor device according to the present invention, the contact prevention layer is a semiconductor layer having a lower etching rate than the channel layer.

In such a semiconductor device, the contact preventing layer can be made to protrude more easily than the channel layer by selecting an etching solution.

In the semiconductor device according to the present invention, the contact prevention layer is a semiconductor layer having an etching rate lower than that of the channel layer and the electron supply layer.

In such a semiconductor device, the contact prevention layer can be made to protrude more easily than the channel layer and the electron supply layer by selecting an etching solution.

Further, in the semiconductor device according to the present invention, the contact prevention layer is a semiconductor layer having a wider band gap than the channel layer.

In such a semiconductor device, transmission of electrons from the electron supply layer to the contact prevention layer is prevented.

In the semiconductor device of the present invention, the channel layer is made of GaAs or InGaAs having a composition ratio of In of 0.3 or less, and the electron supply layer is made of Al _x Ga.
_1-x consists As (0 ≦ x ≦ 0.3) , wherein the contact prevention layer is _{Al y Ga 1-y As (} 0 <y <0.45: x <y) , or In _z Ga _1-z P ( 0.4 ≦ z ≦ 1).

In the semiconductor device according to the present invention, the channel layer may be made of InGaAs having an In composition ratio of 0.53 or more.
s, and the electron supply layer is made of Al _x In _1-x As (0.
45 ≦ x ≦ 0.5), and the contact prevention layer is made of Al _y
In _1-y As (0.45 <y <1: x <y) or In _z
Ga _1-z P (0.85 ≦ z ≦ 1) is exemplified.

In the semiconductor device according to the present invention, the electrode is a gate electrode.

In this case, the gate leakage current from the gate electrode can be reduced.

Further, in the semiconductor device according to the present invention, the contact prevention layer is made of InGaP or InP.

In this case, since the contact prevention layer having a low surface recombination speed is disposed near the semiconductor surface, generation and recombination of electrons and holes on the semiconductor surface can be suppressed.

Further, in the semiconductor device according to the present invention, a source electrode and a drain electrode are formed on a semiconductor wafer including a channel layer, an electron supply layer, and a contact prevention layer on the semiconductor substrate. A gate electrode is formed between the gate electrode and the drain electrode.

Thus, it is possible to form a field effect transistor in which generation and recombination of electrons and holes on the semiconductor surface are suppressed.

Further, in the semiconductor device according to the present invention, the gate electrode has a buried structure reaching the electron supply layer.

In this case, since the gate electrode penetrates the contact prevention layer, the contact portion between the gate electrode and the contact prevention layer comes into contact with the semiconductor in a direction parallel to the semiconductor substrate,
The band gap appears to be substantially increased, and the gate breakdown voltage does not decrease.

Further, the method of manufacturing a semiconductor device according to the present invention
A first semiconductor layer serving as a channel layer having a large electron affinity on a semiconductor substrate, a second semiconductor layer serving as an electron supply layer having a smaller electron affinity than the channel layer, and at least an upper portion of the first semiconductor layer. Forming a third semiconductor layer, which is to be a contact prevention layer, which is undoped or doped at a lower concentration than the second semiconductor layer;
Forming a mesa portion by etching the second and third semiconductor layers, and projecting the third semiconductor layer laterally beyond the first semiconductor layer by side-etching the side walls of the mesa portion. And forming an electrode on the mesa.

According to such a method of manufacturing a semiconductor device,
The above-described semiconductor device of the present invention can be manufactured.

Further, the method of manufacturing a semiconductor device according to the present invention comprises:
A first semiconductor layer serving as a channel layer having a high electron affinity on a semiconductor substrate, a second semiconductor layer serving as an electron supply layer having an electron affinity lower than the first semiconductor layer, and at least the first semiconductor layer A third semiconductor layer located above the first semiconductor layer and serving as a contact preventing layer undoped or doped at a lower concentration than the second semiconductor layer; and the first semiconductor layer located on the third semiconductor layer. Forming a fourth semiconductor layer serving as an electron supply layer having a smaller electron affinity than the first semiconductor layer;
Forming a mesa portion by etching the first, second, third, and fourth semiconductor layers; and side-etching a side wall of the mesa portion to form the third semiconductor layer into the first semiconductor layer. A step of projecting laterally from the layer and the second semiconductor layer; and a step of forming an electrode on the mesa portion.

According to this method of manufacturing a semiconductor device, a contact prevention layer projecting laterally from the channel layer and the first electron supply layer and undoped or doped at a lower concentration than the electron supply layer is formed on the first electron supply layer. A semiconductor device having a structure in which a second electron supply layer having a smaller electron affinity than the channel layer is formed on the contact prevention layer can be manufactured.

Further, the method for manufacturing a semiconductor device according to the present invention
The side etching is performed by using an etching solution having an etching rate for the first semiconductor layer higher than that for the third semiconductor layer.

According to such a method of manufacturing a semiconductor device, the third semiconductor layer can be more easily protruded than the first semiconductor layer.

The method of manufacturing a semiconductor device according to the present invention
In the side etching, the etching rate of the first semiconductor layer and the second semiconductor layer is higher than the third semiconductor layer.
The etching is performed using an etching solution faster than the etching rate for the semiconductor layer.

According to such a method of manufacturing a semiconductor device, the third semiconductor layer can be made to protrude more easily than the first semiconductor layer and the second semiconductor layer.

[0045]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a structure of a gate electrode portion of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a portion of the gate electrode G in FIG. 8 cut along a broken line AA ′.

The semiconductor device according to the first embodiment is composed of GaAs.
A field effect transistor using a substrate, GaAs
A buffer layer 1 made of undoped GaAs is formed on a substrate (not shown), and a channel layer 2 made of undoped In _0.2 Ga _0.8 As and having a high electron affinity is formed on the buffer layer 1. A spacer layer 3 made of undoped Al _0.2 Ga _0.8 As is formed thereon, and an Al _0.2 G doped with Si is formed on the spacer layer 3.
An electron supply layer 4 made of a _0.8 As and having a low electron affinity is formed, and undoped Al _0.4 G is formed on the electron supply layer 4.
The contact prevention layer 5 made of a _0.6 As is formed. The thickness of each layer is 800 nm for the buffer layer 1, 10 nm for the channel layer 2, 2 nm for the spacer layer 3, and 2 nm for the electron supply layer 4.
Is 30 nm, and the contact prevention layer 5 is 15 nm. The electron supply layer 4 is formed by doping Si at 2 × 10 ¹⁸ cm ⁻³ . Note that the spacer layer 3 is a layer for separating the channel layer 2 and the electron supply layer 4 by a predetermined distance to improve the mobility of electrons in the channel layer 2. Further, a gate electrode 6 is formed on the contact preventing layer 5, and a gate wiring portion 6a extends toward a GaAs substrate (not shown).

In the semiconductor device of the first embodiment, the first side wall a inclined by the side wall of the buffer layer 1 on the side of the gate wiring section 6a and the side wall of the channel layer 2 on the side of the gate wiring section 6a.
Is formed, and a second side wall b inclined by the side wall of the spacer layer 3 on the side of the gate wiring section 6a and the side wall of the electron supply layer 4 on the side of the gate wiring section 6a is formed. A third side wall c inclined by the side wall on the side of the gate wiring portion 6a is formed. The second side wall b is the third side wall c
The first side wall a is inwardly recessed from the second side wall b.
Recessed inward. That is, the buffer layer 1, the channel layer 2, the spacer layer 3, and the contact prevention layer 5 projecting laterally (toward the gate wiring portion 6 a) from the electron supply layer 4 are formed on the electron supply layer 4. The gate wiring portion 6a is in contact with the third side wall c, but a gap 7 is formed between the first side wall a and the second side wall b. No contact is made with the second side wall b.

FIG. 2 is a sectional view showing a method of manufacturing the gate electrode portion of the semiconductor device according to the first embodiment.

First, as shown in FIG. 2A, a buffer layer 1, a channel layer (first semiconductor layer) 2, a spacer layer 3, and an electron supply layer (second semiconductor layer) are formed on a GaAs substrate (not shown). A layer 4) and a contact prevention layer (third semiconductor layer) 5 are sequentially deposited and formed, and then a photoresist 8 is patterned and formed at a predetermined position on the contact prevention layer 5.

Next, mesa etching is performed using a tartaric acid-based etchant to form a mesa portion 9 whose side walls are inclined flush with each other as shown in FIG. 2B.

Next, a citric acid-based etchant (citric acid
Using acid: hydrogen peroxide = 5: 2), etch the sidewalls of the mesa 9
Switch. Buffer layer 1, channel layer 2, spacer
Each semiconductor used for the layer 3, the electron supply layer 4, and the contact prevention layer 5
Etching of body layer with citric acid etchant
Are as shown in Table 1. That is, the contact prevention layer 5 is formed.
Al_0.4Ga_0.6Electron supply layer 4 rather than As layer, spacer
Al to be layer 3_0.2Ga_{0 .8}Et layer is better for As layer
A, which is high in the electron supply layer 4 and the spacer layer 3
l_0.2Ga_0.8Channel layer 2 and buffer layer 1 rather than As layer
GaAs has a higher etching rate. others
Therefore, as shown in FIG.
Also, the side walls of the electron supply layer 4 and the spacer layer 3 are etched.
And the electron supply layer 4 and the spacer layer
3 is closer to the side wall of the channel layer 2 and the side wall of the buffer layer 1 than the side wall of
Is increased by etching, and the side wall of the mesa 9
The first side wall a, the second side wall b, and the third side wall
c is formed.

[0053]

[Table 1]

The channel layer 2 is made of In _0.3 Ga _0.7 As.
It is also possible to form from
In _0.4 Ga _0.6 P, In _0.49 Ga ₀ . ₅₁ P, In _0.6 Ga
_0.4 P, In _0.85 Ga _0.15 P or InP can also be used.
Also described in the inside.

After performing the above steps, the photoresist 8
Is removed and the gate electrode 6 is formed, whereby the gate electrode structure shown in FIG. 1 is formed.

In the semiconductor device of the first embodiment,
The wiring portion 6a drawn out from the gate electrode 6 contacts the undoped contact prevention layer 5, but does not contact the electron supply layer 4 and further does not contact the channel layer 2, so that the gate leakage current is reduced. In addition, the gate breakdown voltage is improved. The same effect can be obtained even if the contact prevention layer 5 is a layer doped at a lower concentration than the electron supply layer 4.

FIG. 3 is a graph showing the characteristics of the gate electrodes of the field effect transistor formed of the semiconductor device of the first embodiment and the field effect transistor formed of the conventional semiconductor device. As can be seen from FIG. 3, in the field-effect transistor of the first embodiment, the gate leakage current is reduced as compared with the conventional one, and the gate breakdown voltage is -7 of the conventional structure.
It can be seen that the voltage was improved from V to -11V. The conventional semiconductor device is different from the semiconductor device of the first embodiment in that an undoped Al is used instead of the contact prevention layer 5 on the surface.
It was formed in the same manner as in the first embodiment, except that the _0.2 Ga _0.8 As layer was arranged to have a thickness of 15 nm.

Next, a semiconductor device according to a second embodiment of the present invention will be described.

FIG. 4 is a sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention. The same parts as those in FIG. 1 are denoted by the same reference numerals, and a description thereof will be omitted. In the semiconductor device according to the second embodiment, Si doped A
A first electron supply layer 41 made of l _0.2 Ga _0.8 As and having a small electron affinity is formed, and a contact prevention layer 51 made of undoped Al _0.4 Ga _0.6 As is formed on the first electron supply layer 41. A on which Si doped A
A second electron supply layer 42 made of l _0.2 Ga _0.8 As and having a small electron affinity is formed. The layer thickness of each layer is the first
12 nm for the electron supply layer 41 and 10 n for the contact prevention layer 51
m, the second electron supply layer 42 is 12 nm. Also, the first
The electron supply layers 41 and 42 are formed by doping Si at 2 × 10 ¹⁸ cm ⁻³ .

In the semiconductor device of the second embodiment, the first side wall a inclined by the side wall of the buffer layer 1 on the side of the gate wiring section 6a and the side wall of the channel layer 2 on the side of the gate wiring section 6a.
Is formed, and a second side wall b inclined by the side wall of the spacer layer 3 on the side of the gate wiring section 6a and the side wall of the first electron supply layer 41 on the side of the gate wiring section 6a is formed. A third sidewall c is formed by the sidewall of the gate electrode portion 51 on the side of the gate wiring portion 6a.
A fourth side wall d inclined by the side wall on the side of the gate wiring portion 6a is formed. The second side wall b is recessed inward from the third side wall c, and the first side wall a is recessed inward from the second side wall b. Further, the fourth side wall d is recessed inward from the third side wall c. That is, the first electron supply layer 41
Between the buffer layer 1, the channel layer 2, the spacer layer 3, and the first and second electron supply layers 41 and 4.
Since the contact prevention layer 51 is formed so as to protrude sideward (toward the gate wiring portion 6a) from the gate wiring portion 6a.
Is in contact with the third side wall c and the fourth side wall d,
A gap 7 is formed between the first side wall a and the second side wall b, and is not in contact with the first side wall a and the second side wall b.

FIGS. 5A to 5C are cross-sectional views showing a method of manufacturing a gate electrode portion in the semiconductor device according to the second embodiment. This manufacturing method is different from that of the first embodiment except that a first electron supply layer 41, a contact prevention layer 51, and a second electron supply layer 42 are formed on the spacer layer 3 in FIG. As in the first embodiment, a mesa portion is formed by etching using a tartaric acid-based etchant as shown in FIG. 5B, and then using a citric acid-based etchant as shown in FIG. 5C. First, second, third, and fourth end faces a, b, c, and d are formed by etching the sidewalls of the mesa portion, and then the photoresist is removed to form a gate electrode.

In the semiconductor device according to the second embodiment,
The wiring portion 6a drawn out from the gate electrode 6 has a depleted second electron supply layer 42 and an undoped contact prevention layer 51.
, But does not contact the first electron supply layer 41 and further does not contact the channel layer 2, so that the gate leakage current is reduced and the gate breakdown voltage is improved. In addition, since the second electron supply layer 42 is surely depleted by the gate electrode 6, the gate breakdown voltage, particularly the breakdown voltage, is sufficiently high. Further, the electron supply layer is formed of the first electron supply layer 41 and the second electron supply layer 41.
Since it has a two-layer structure with the electron supply layer 42, each of the first and second electron supply layers 41 and 42 has a thin thickness of 12 nm and is easily depleted. The same effect can be obtained even if the contact prevention layer 51 is a layer doped at a lower concentration than the first and second electron supply layers 41 and 42.

FIG. 6 is a diagram showing the characteristics of the gate electrodes of the field effect transistor formed of the semiconductor device of the second embodiment and the field effect transistor formed of the conventional semiconductor device. As can be seen from FIG. 6, in the field-effect transistor of the first embodiment, the gate leakage current is reduced as compared with the conventional one, and the gate breakdown voltage is -7 in the conventional structure.
It can be seen that the voltage was improved from V to -10V. The conventional semiconductor device has the same structure as the conventional semiconductor device used in FIG. 3 of the first embodiment.

In the second embodiment, the first contact prevention layer 41
Although the second contact prevention layer 42 and the second contact prevention layer 42 are formed with the same semiconductor material and the same thickness, they may be formed with different semiconductor materials and different thicknesses.

In the first and second embodiments, Al ₀ is used as the electron supply layer 2. ₂ Ga ₀ . ₈ As was used, and Al ₀ was used as the contact prevention layers 5 and 51. ₄ Ga ₀ . ₆ As was used, but as the electron supply layer 2, Al _x with less DX center was used.
Ga _1-x As with (0 ≦ x ≦ 0.3), Al y Ga 1-y As (0 as a contact-preventing layer 5,51 <y <0.45:
x <y) or In _z Ga _1-z P (0.4 ≦ z ≦ 1) may be used. However, as the contact prevention layers 5 and 51, In _z G
When a _1-z P is used, it is necessary to use an HCl-based etchant to mesa-etch the contact prevention layers 5 and 51. Note that Table 1 shows that z = z as an example when In _z Ga _1-z P is used as the contact prevention layers 5 and 51.
The etching rates of citric acid-based etchants of 0.4, 0.49, 0.6, 0.85 and 1 are shown. However, when an In _z Ga _{1 -z} P layer other than z = 0.49 is used as a contact prevention layer, lattice matching with GaAs or AlGaAs is not performed, so that the film thickness needs to be controlled within a critical film thickness range. There is.

In the first and second embodiments described above, In ₀ is used as the channel layer 2. ₂ Ga ₀ . ₈ As was used, but GaAs
InGaAs having a composition ratio of s or In of 0.3 or less may be used. However, it is necessary to control the thickness of the channel layer within the range of the critical thickness.

In the first and second embodiments described above, Ga
The field effect transistor using a wafer structure deposited on an As substrate has been described as an example, but the present invention is also applicable to a field effect transistor using a wafer structure deposited on an InP substrate. In this case, A as the electron supply layer
l _x In _1-x As (0.45 ≦ x ≦ 0.5), and _Aly In _1-y As (0.45 <y <1: x) as a contact prevention layer
<Y) or In _z Ga _1-z P (0.85 ≦ z ≦ 1), and the channel layer is made of I with an In composition ratio of 0.53 or more.
Even if nGaAs is used, the same effects as those of the first and second embodiments can be obtained. Incidentally, a citric acid-based etchant (citric acid: hydrogen peroxide = 5: 2) in these semiconductor materials.
Table 2 shows the etching rates with respect to.

[0068]

[Table 2]

The channel layer 2 is made of In _0.65 Ga
It is also possible to use _0.35 As, and its etching rate is also shown in Table 2.

However, In _z Ga _{1 -z} P is used as the contact prevention layer.
When (0.85 ≦ z ≦ 1) is used, it is necessary to use an HCl-based etchant to mesa-etch these layers. Further, it is necessary to control the thicknesses of the contact prevention layer, the electron supply layer and the channel layer within the range of the critical thickness.

The present invention is not limited to the above embodiment,
Claims that do not depart from the spirit of the invention as set forth in the claims.
Various modifications can be made in the box. For example,
In the semiconductor device of the first embodiment or the second embodiment,
Stop layers 5 and 51 are made of In._0.49Ga _0.51P, In_0.4Ga
_0.6P, In_0.6Ga_0.4P, In_0.85Ga_0.15P or
If formed by InP, the spacer layer 3 and the electron supply layer
4 is a semiconductor layer having a high surface recombination speed, and is a contact prevention layer.
5 and 51 are more surface-rear than the spacer layer 3 and the electron supply layer 4.
The semiconductor layer has a low bonding speed. In this case, the semiconductor substrate
The upper channel layer 2, electron supply layer 4, and contact prevention layer 5
A source electrode and a drain on a semiconductor wafer
A source electrode and a gate electrode between the source and drain electrodes.
A gate electrode is formed. Here, the gate electrode is
A buried structure that reaches the layer 4 is preferable.

In such a semiconductor device, the spacer layer 3
In addition, since the contact prevention layers 5 and 51 having a lower surface recombination speed are arranged in a portion closer to the semiconductor surface than the electron supply layers 4 and 41, generation and recombination of electrons and holes on the semiconductor surface are suppressed. And a structure in which phase noise hardly occurs.

In the first and second embodiments described above, a semiconductor device having a single hetero structure has been described. However, the present invention is directed to a double hetero structure or a structure in which the positional relationship between the channel layer and the electron supply layer is reversed. The present invention is applicable to a semiconductor device having a heterojunction structure having another structure.

Further, in the above-described embodiment, an example in which the present invention is applied to the gate electrode portion of a field effect transistor has been described. The current can be reduced.

[0075]

According to the present invention, it is possible to provide a semiconductor device in which a leak current from an electrode such as a gate electrode is suppressed.

Further, according to the present invention, it is possible to provide a semiconductor device having a structure in which the region where the electron supply layer is not depleted is reduced.

Further, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device having the above-described effects.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 3 is a view showing characteristics of gate electrodes of the semiconductor device according to the first embodiment of the present invention and a semiconductor device having a conventional structure.

FIG. 4 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention;

FIG. 5 is a view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating characteristics of gate electrodes of a semiconductor device according to a second embodiment of the present invention and a semiconductor device having a conventional structure.

FIG. 7 is a cross-sectional view of a main part of a conventional semiconductor device.

FIG. 8 is a schematic view of the semiconductor device as viewed from above.

FIG. 9 is a sectional view of a main part of a conventional semiconductor device.

FIG. 10 is a diagram showing a defect of a conventional semiconductor device.

[Explanation of symbols]

 2 channel layer 4 electron supply layer 5 contact prevention layer 6 gate electrode 9 mesa section 41 first electron supply layer 42 second electron supply layer

Claims (17)

[Claims] 1. A semiconductor device having, on a semiconductor substrate, a channel layer having a high electron affinity and an electron supply layer having a lower electron affinity than the channel layer. A contact preventing layer that protrudes from the substrate and is undoped or doped at a lower concentration than the electron supply layer, and an electrode is formed on the contact preventing layer. 2. A semiconductor device having a channel layer having a high electron affinity on a semiconductor substrate and an electron supply layer having a lower electron affinity than the channel layer, wherein the channel layer is provided above the channel layer and the electron supply layer. And a contact prevention layer protruding laterally from the electron supply layer, undoped or doped at a lower concentration than the electron supply layer, and an electrode formed on the contact prevention layer. . 3. A semiconductor device in which a channel layer having a high electron affinity is formed on a semiconductor substrate and an electron supply layer having an electron affinity lower than the channel layer is formed on the channel layer. A contact prevention layer that projects laterally from the channel layer and the electron supply layer and is undoped or doped at a lower concentration than the electron supply layer, and an electrode is formed on the contact prevention layer. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, wherein a channel layer having a high electron affinity is formed on a semiconductor substrate, and a first electron supply layer having a lower electron affinity than the channel layer is formed on the channel layer. On the electron supply layer, a contact prevention layer projecting laterally from the channel layer and the first electron supply layer and undoped or doped at a lower concentration than the electron supply layer is formed, and the contact prevention layer is formed on the contact prevention layer. A semiconductor device, comprising: a second electron supply layer having a smaller electron affinity than a channel layer; and an electrode formed on the second electron supply layer. 5. The semiconductor device according to claim 1, wherein the contact prevention layer is a semiconductor layer having a lower etching rate than the channel layer. 6. The semiconductor device according to claim 2, wherein said contact preventing layer is a semiconductor layer having a lower etching rate than said channel layer and said electron supply layer. 7. The semiconductor device according to claim 1, wherein said contact prevention layer is a semiconductor layer having a wider band gap than said channel layer. 8. The method according to claim 1, wherein the channel layer is made of GaAs or InGaAs having a composition ratio of In of 0.3 or less, and the electron supply layer is made of Al _x Ga _{1 -x} As (0 ≦ x ≦ 0.3). The contact prevention layer is made of Al _y Ga _1-y As (0 <y <0.
45: x <y) or In _z Ga _1-z P (0.4 ≦ z ≦
The method according to claim 1, 2, 3, 4, or 1, wherein
8. The semiconductor device according to 5, 6, or 7. 9. The method according to claim 1, wherein the channel layer has an In composition ratio of 0.5.
3 or more InGaAs, and the electron supply layer is made of Al
_{x In 1-x As (0.45} ≦ x ≦ 0.5) consists, said contact preventing layer _{Al y In 1-y As (} 0.45 <y <1: x
<Y), or _{In z Ga 1-z P (} 0.85 ≦ z ≦ 1) that consists of a semiconductor device according to claim 1,2,3,4,5,6 or 7 wherein. 10. The method according to claim 1, wherein the electrode is a gate electrode.
13. The semiconductor device according to claim 1. 11. The method according to claim 1, wherein said contact prevention layer is made of InGaP or InP.
The semiconductor device according to 4, 5, 6, 7, 8, 9, or 10. 12. A source electrode and a drain electrode are formed on a semiconductor wafer including a channel layer, an electron supply layer, and a contact prevention layer on the semiconductor substrate, and a gate is provided between the source electrode and the drain electrode. The semiconductor device according to claim 11, wherein an electrode is formed. 13. The semiconductor device according to claim 12, wherein the gate electrode has a buried structure reaching the electron supply layer. 14. A semiconductor device comprising: a first semiconductor layer serving as a channel layer having a higher electron affinity on a semiconductor substrate; a second semiconductor layer serving as an electron supply layer having a lower electron affinity than the first semiconductor layer; Located on top of the first semiconductor layer,
Forming a third semiconductor layer to be a contact prevention layer undoped or doped at a lower concentration than the second semiconductor layer; and etching the first, second, and third semiconductor layers to form a mesa. Forming a portion, forming a third semiconductor layer laterally beyond the first semiconductor layer by side-etching a sidewall of the mesa portion, and forming an electrode on the mesa portion. A method of manufacturing a semiconductor device. 15. A semiconductor device comprising: a first semiconductor layer serving as a channel layer having a high electron affinity on a semiconductor substrate; a second semiconductor layer serving as an electron supply layer having a lower electron affinity than the first semiconductor layer; Located on top of the first semiconductor layer,
A third semiconductor layer serving as a contact prevention layer undoped or doped at a lower concentration than the second semiconductor layer; and a third semiconductor layer located on the third semiconductor layer and having a lower electron affinity than the first semiconductor layer. A step of forming a fourth semiconductor layer to be an electron supply layer; a step of forming a mesa by etching the first, second, third, and fourth semiconductor layers; A step of projecting the third semiconductor layer laterally beyond the first semiconductor layer and the second semiconductor layer by side-etching a side wall; and a step of forming an electrode on the mesa portion. A method for manufacturing a semiconductor device, comprising: 16. The method according to claim 14, wherein the side etching is performed by using an etching solution having an etching rate for the first semiconductor layer higher than that for the third semiconductor layer. Of manufacturing a semiconductor device. 17. The method according to claim 17, wherein the side etching is performed by using an etching solution in which an etching rate for the first semiconductor layer and the second semiconductor layer is higher than an etching rate for the third semiconductor layer. The method for manufacturing a semiconductor device according to claim 14, wherein: