US20020187623A1 - Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof - Google Patents

Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof Download PDF

Info

Publication number
US20020187623A1
US20020187623A1 US10/191,435 US19143502A US2002187623A1 US 20020187623 A1 US20020187623 A1 US 20020187623A1 US 19143502 A US19143502 A US 19143502A US 2002187623 A1 US2002187623 A1 US 2002187623A1
Authority
US
United States
Prior art keywords
layer
doped
layers
compound semiconductor
plural
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/191,435
Inventor
Hirokazu Oikawa
Hitoshi Negishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to US10/191,435 priority Critical patent/US20020187623A1/en
Publication of US20020187623A1 publication Critical patent/US20020187623A1/en
Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer

Definitions

  • This invention relates to a compound semiconductor and, more particularly, to a compound semiconductor device having an etching stopper layer between an active layer and an ohmic electrode.
  • a heterojunction metal-semiconductor field effect transistor is a typical example of the compound semiconductor device.
  • the high electron mobility transistor is a kind of heterojunction metal- semiconductor field effect transistor, and is featured by an inversion layer at the boundary between an electron supply layer and a channel layer.
  • the heterojunction metal-semiconductor field effect transistor finds a wide variety of application such as, for example, a DBS (Direct Broadcasting Satellite).
  • the compound semiconductor device is expected to have low- noise characteristics and achieve a high-gain.
  • a stepped doping concentration structure has been proposed.
  • the electron supply layer has a relatively heavy dopant concentration close to the channel layer and a relatively light dopant concentration close to the gate electrode.
  • FIG. 1 illustrates the prior art high electron mobility transistor with the stepped dopant concentration structure.
  • the prior art high electron mobility transistor is fabricated on a semi-insulating substrate 1 , which is formed of gallium arsenide.
  • the prior art high electron mobility transistor comprises a buffer layer 2 , a channel layer 3 , an electron supply layer 4 / 5 , cap layers 8 , ohmic electrodes 9 and a gate electrode 10 .
  • Gallium arsenide is epitaxially grown on the semi-insulating substrate 1 , and forms a gallium arsenide layer.
  • the gallium arsenide layer serves as the buffer layer 2 .
  • gallium arsenide layer On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer 3 .
  • Heavily-doped n-type aluminum gallium arsenide, i.e., n + Al 0.2 Ga 0.8 As and lightly-doped n-type aluminum gallium arsenide, i.e., n ⁇ Al 0.2 Ga 0.8 As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly doped n-type aluminum gallium arsenide layer 5 .
  • the dopant concentration is 4 ⁇ 10 18 /cm 3 (4× 10 ⁇ 18 /cm 3 ) in the heavily-doped n-type aluminum gallium arsenide layer 4 and 1 ⁇ 10 17 /cm 3 in the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5 form in combination the electron supply layer 4 / 5 .
  • the heavily-doped n-type aluminum gallium arsenide layer 4 is contiguous to the channel layer 3 , and the gate electrode 10 is held in contact with the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the electron supply layer 4 / 5 has the stepped dopant concentration structure.
  • the lightly-doped aluminum gallium arsenide layer 5 is epitaxially grown heavily-doped n-type gallium arsenide from which forms the cap layers 8 of 80 nanometers thick are formed.
  • the dopant concentration is 3 ⁇ 10 18 /cm 3 in the heavily-doped n-type gallium arsenide layer.
  • the heavily-doped n-type gallium arsenide layer is partially etched so as to expose the electron supply layer 4 / 5 to a recess between the cap layers 8 .
  • the gate electrode 10 is held in contact with the exposed portion of the electron supply layer 5 .
  • the ohmic electrodes 9 are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
  • the prior art high electron mobility transistor achieves a large mutual conductance by virtue of the heavily-doped n-type aluminum gallium arsenide layer 4 as well as a high withstand voltage by virtue of the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the threshold voltage and, accordingly, the amount of channel current are liable to fluctuate among the products. This is because of the fact that the etchant is liable to partially remove the lightly-doped n-type aluminum gallium arsenide layer 5 during the formation of the recess.
  • etching stopper has been proposed as a countermeasure against the problem.
  • the recess is formed by using mixture of citric acid and H 2 O 2 as wet etchant.
  • the prior art high electron mobility transistor has the structure shown in FIG. 2.
  • the prior art high electron mobility transistor is fabricated on a semi-insulating substrate 1 , which is formed of gallium arsenide.
  • the prior art high electron mobility transistor comprises a buffer layer 2 , a channel layer 3 , an electron supply layer 4 / 5 , etching stopper layers 7 , cap layers 8 , ohmic electrodes 9 and a gate electrode 10 .
  • Gallium arsenide is epitaxially grown on the semi-insulating substrate 1 , and forms a gallium arsenide layer.
  • the gallium arsenide layer serves as the buffer layer 2 .
  • On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer 3 .
  • Heavily-doped n-type aluminum gallium arsenide i.e., n + Al 0.2 Ga 0 8 As and lightly-doped n-type aluminum gallium arsenide, i.e., n ⁇ Al 0.2 Ga 0.8 As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the dopant concentration is 4 ⁇ 10 18 /cm 3 in the heavily-doped n-type aluminum gallium arsenide layer 4 and 1 ⁇ 10 17 /cm 3 in the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n- type aluminum gallium arsenide layer 5 form in combination the electron supply layer 4 / 5 .
  • the heavily-doped n-type aluminum gallium arsenide layer 4 is contiguous to the channel layer 3 , and the gate electrode 10 is held in contact with the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the electron supply layer 4 / 5 has the stepped dopant concentration structure.
  • lightly-doped aluminum gallium arsenide layer 5 is grown lightly-doped n-type aluminum gallium arsenide n ⁇ Al 0.7 Ga 0.3 As which forms a lightly-doped n-type aluminum gallium arsenide layer.
  • the etching stopper layers 7 are formed from the lightly-doped n-type aluminum gallium arsenide layer.
  • Heavily-doped n-type gallium arsenide is epitaxially grown to 80 nanometers thick on the lightly-doped n-type aluminum gallium arsenide layer 7 , and forms a heavily-doped n-type gallium arsenide layer.
  • the cap layers 8 are formed from the heavily-doped n-type gallium arsenide layer.
  • the dopant concentration is 3 ⁇ 10 18 /cm 3 in the heavily-doped n-type gallium arsenide layer.
  • the heavily-doped n-type gallium arsenide layer 8 and the lightly-doped aluminum gallium arsenide layer 7 are partially etched so as to expose the electron supply layer 4 / 5 to a recess between the cap layers 8 .
  • the gate electrode 10 is held in contact with the exposed portion of the electron supply layer 5 .
  • the ohmic electrodes 9 are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
  • the lightly-doped n-type Al 0.7 Ga 0.3 As layer 7 gives an end point to the wet etchant in the formation of the recess, and prevents the lightly doped Al 0.8 Ga 0 2 As layer 5 from the wet etchant.
  • the electron supply layer 4 / 5 is constant in thickness, and the electron supply layer 4 / 5 keeps the threshold constant among products.
  • Aluminum had the large composition ratio in the n ⁇ Al 0.7 Ga 0.3 As.
  • the aluminum was a large amount of dx center, and the dx centers were not activated with the n-type dopant impurity, i.e., silicon. Even though the silicon was doped in the Al 0.7 Ga 0.3 As, a non-ignoreable amount of n-type dopant impurities were invalid, and the lightly-doped Al 0.7 Ga 0.3 As layer exhibited high resistivity.
  • the present inventors replaced the lightly-doped n ⁇ Al 0.7 Ga 0.3 As etching stopper layers 7 with non-doped etching stopper layers.
  • the high electron mobility transistor also exhibited large source resistance.
  • the present inventors concluded that the resistance was to be reduced without deleting the etching stopper layer was required.
  • the present invention proposes to reduce the potential barrier between cap layers and an active layer by using delta-doped layers.
  • a compound semiconductor device fabricated on a substrate comprising a multiple-layered structure including an active layer, plural cap layers respectively located over plural portions of the active layer, plural highly-resistive layers formed between the multiple-layered structure and the plural cap layers so as to form a recess located over a part of the multiple- layered structure and between the plural cap layers, plural delta-doped layers formed between the plural highly-resistive layers and the multiple- layered structure for decreasing potential barriers of the plural highly-resistive layers, a first electrode held in contact with the part of the multiple- layered structure for controlling the amount of current flowing through the active layer, and second electrodes respectively formed on the plural cap layers for providing current paths from and to the active layer through the plural cap layers, the plural highly-resistive layers and the plural delta-doped layers.
  • a process for fabricating a compound semiconductor device comprising the steps of a) producing a multiple-layered structure having an active layer, a delta-doped layer over the active layer, a highly resistive layer over the delta-doped layer and a highly conductive layer over the delta-doped layer on a semi-insulating substrate, b) removing a part of the highly conductive layer so as to expose a part of the highly resistive layer to a first opening formed between remaining portions of the highly conductive layer serving as plural cap layers, c) removing the part of the highly resistive layer and a part of the delta-doped layer thereunder so as to expose a part of the active layer to a second opening formed between plural delta doped layers respectively overlain by highly resistive layers and d) completing a compound semiconductor device having a first electrode held in contact with the part of the active layer and second electrodes respectively held in contact with the plural cap layers.
  • FIG. 1 is a cross sectional view showing the prior art high electron mobility transistor with the stepped dopant concentration structure
  • FIG. 2 is a cross sectional view showing the prior art high electron mobility transistor with the etching stopper between the electron supply layer and the cap layers;
  • FIG. 3 is a cross sectional view showing the structure of a high electron mobility transistor according to the present invention.
  • FIGS. 4 is an energy band diagram showing the energy band created in the high electron mobility transistor
  • FIGS. 5A to 5 C are cross sectional views showing a process for fabricating the high electron mobility transistor according to the present invention.
  • FIG. 6 is a cross sectional view showing the structure of a heterojunction metal-semiconductor field effect transistor according to the present invention.
  • FIGS. 7A to 7 D are cross sectional views showing a process for fabricating the heterojunction metal-semiconductor field effect transistor according to the present invention.
  • a high electron mobility transistor embodying the present invention is fabricated on a semi- insulating substrate 1 of gallium arsenide.
  • the high electron mobility transistor comprises a buffer layer 2 , a channel layer 3 , an electron supply layer 4 / 5 , delta doped layers 6 , etching stopper layers 7 , cap layers 8 , ohmic electrodes 9 and a gate electrode 10 .
  • the delta doped layers are referred to as “planar dope layer” or “pulse dope layer” in several articles.
  • the term “delta doped layer” is synonymous with the term “planar dope layer” and the term “pulse dope layer”.
  • the delta doped layers 6 are hereinlater described in detail.
  • the buffer layer 2 is formed of gallium arsenide epitaxially grown on the semi-insulating substrate 1 of gallium arsenide.
  • the channel layer 3 is formed of indium gallium arsenide epitaxially grown on the gallium arsenide buffer layer 2 .
  • the electron supply layer 4 / 5 has the stepped dopant concentration structure, and the stepped dopant concentration structure is implemented by a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the heavily-doped n- type aluminum gallium arsenide and the lightly-doped n-type aluminum gallium arsenide have the composition expressed as Al 0.2 Ga 0.8 As.
  • the heavily-doped n-type aluminum gallium arsenide layer 4 is 10 nanometers thick, and the dopant concentration is 4 ⁇ 10 18 /cm 3 in the heavily-doped n-type aluminum gallium arsenide layer 4 .
  • the lightly-doped n-type aluminum gallium arsenide layer 5 is 20 nanometers thick, and the dopant concentration is 1 ⁇ 10 17 /cm 3 in the lightly-doped n-type aluminum gallium arsenide layer 5 .
  • the delta doped layers 6 are formed by supplying Group-V element, i.e., arsenic (As) and silicon, only, and are as thin as a single atom to several atoms.
  • the silicon is delta doped.
  • the dopant impurity, i.e., silicon is heavily contained in the delta doped layer 6 .
  • the dopant impurity concentration of the delta-doped layers 6 are heavier than that of the electron supply layer.
  • the delta doped layers 6 contain the silicon at 6 ⁇ 10 12 /cm 2 .
  • the delta doped layers 6 contain only one kind of dopant impurity so that the tunneling phenomenon takes place at the boundaries. For this reason, the carriers can pass a potential barrier larger in height than the energy thereof.
  • the etching stopper layers 7 are formed of lightly-doped aluminum gallium arsenide epitaxially grown on the delta doped layers 6 .
  • the lightly-doped aluminum gallium arsenide is different in composition from that of the electron supply layer 4 / 5 , and is expressed as Al 0.7 Ga 0.3 As.
  • silicon is lightly doped into the aluminum gallium arsenide Al 0.7 Ga 0.3 As, the aluminum gallium arsenide Al 0.7 Ga 0.3 As contains a large amount of dx centers, and the dx centers deactivate the silicon. For this reason, the effective carrier density is drastically decreased in the aluminum gallium arsenide etching stopper layers 7 .
  • the cap layers 8 are formed from a heavily-doped n-type gallium arsenide layer epitaxially grown on the aluminum gallium arsenide etching stopper layers 7 .
  • the cap layers 8 are 80 nanometers thick, and the dopant concentration is 3 ⁇ 10 18 /cm 3 .
  • the heavily-doped n-type gallium arsenide layer 8 , the lightly-doped aluminum gallium arsenide layer 7 and the delta doped layer 6 are partially etched away so that the electron supply layer 5 is exposed to a recess between the cap layers 8 .
  • the ohmic electrodes 9 are held in contact with the cap layers 8
  • the gate electrode 10 is held in contact with the lightly-doped aluminum gallium arsenide layer 5 of the electron supply layer.
  • the energy band shown in FIG. 4 is created in the high electron mobility transistor according to the present invention. If the delta doped layers 6 are not inserted between the electron supply layer 4 / 5 and the etching stopper layers, the bottom edge of conduction band is represented by broken line.
  • the potential barriers between the cap layers 8 and the etching stopper layers 7 and between the etching stopper layers 7 and the electron supply layer 5 are wide.
  • the delta doped layers 6 make the potential level of the etching stopper layers 7 lower.
  • the potential barriers between the cap layers 8 and the etching stopper layers 7 and between the etching stopper layers 7 and the electron supply layer 5 are made narrow. As a result, the carriers or electrons are smoothly moved between the ohmic electrodes 9 and the channel layer 3 , and, accordingly, the resistance is decreased.
  • the etching stopper 7 keeps the electron supply layer 4 / 5 constant in thickness among the products.
  • the electron supply layer 4 / 5 with constant thickness is effective against the fluctuation of threshold voltage.
  • the high electron mobility transistor according to the present invention achieves the low resistance without sacrifice of the constant thickness of the electron supply layer 4 / 5 .
  • the high electron mobility transistor shown in FIG. 3 is fabricated through a process shown in FIGS. 5A to 5 C.
  • compound semiconductor layers are labeled with the references designating the layers of the high electron mobility transistor shown in FIG. 3.
  • the process starts with preparation of the semi- insulating substrate 1 .
  • the gallium arsenide layer 2 , the indium gallium arsenide layer 3 , the heavily-doped aluminum gallium arsenide layer 4 , the lightly-doped aluminum gallium arsenide layer 5 , the delta doped layers 6 , the aluminum gallium arsenide layer 7 and the heavily-doped gallium arsenide layer 8 are epitaxially grown on the semi-insulating substrate 1 in succession.
  • Nickel-gold-germanium alloy Ni/AuGe is grown on the heavily-doped gallium arsenide layer 8 , and the ohmic electrodes 9 are formed from the nickel-gold- germanium alloy layer.
  • the resultant semiconductor structure in this stage is shown in FIG. 5A.
  • a photo-resist mask 11 is provided on the resultant semiconductor structure by using a photo- lithography. Namely, photo-resist solution is spread over the resultant semiconductor structure, and is baked so as to form a photo-resist layer. A pattern image is transferred from a photo-mask to the photo-resist layer so as to produce a latent image in the photoresist layer. The latent image is developed. Then, the photo-resist mask 11 is left on the resultant semiconductor structure. A part of the heavily-doped gallium arsenide layer 8 is exposed to the opening formed in the photo-resist mask 11 .
  • the heavily-doped gallium arsenide layer 8 is partially removed. Since the wet etchant has the selectivity larger to the gallium arsenide than to the lightly-doped n-type aluminum gallium arsenide Al 0.7 Ga 0.3 As, the wet etching is terminated on the lightly-doped n- type aluminum gallium arsenide Al 0.7 Ga 0.3 As layer 7 , and a recess 12 is formed in the heavily-doped n-type gallium arsenide layer 8 as shown in FIG. 5B.
  • the lightly-doped n-type aluminum gallium arsenide Al 0.7 Ga 0.3 As layer 7 serves as an etching stopper. While the lightly.-doped n- type aluminum gallium arsenide Al 0.7 Ga 0.3 As layer 7 is being etched with the wet etchant, the exposed portion of the lightly-doped n-type aluminum gallium arsenide Al 0.7 Ga 0.3 As etching stopper layer 7 is oxidized, and aluminum oxide Al 2 O 3 is left on the delta-doped layers 6 .
  • the lightly-doped n- type aluminum gallium arsenide Al 0.7 Ga 0.3 As layer 7 contains a large amount of dx centers. For this reason, the dopant impurity, i.e., silicon atoms are hardly activated, and the actual carrier concentration is drastically reduced. This means that the lightly-doped n-type aluminum gallium arsenide Al 0.7 Ga 0.3 As layer 7 is highly resistive.
  • the aluminum oxide layer and the delta-doped layers 6 under the aluminum oxide layer are etched away by using hydrochloric acid.
  • the lightly-doped n-type aluminum gallium arsenide layer 5 is hardly etched so that the high electron mobility transistor is constant in threshold and the amount of channel current among products.
  • titanium- aluminum alloy is deposited over the entire surface by using an evaporation technique, and the photo-resist mask 11 is stripped off together with the titanium-aluminum alloy deposited thereover.
  • the gate electrode 10 is left on the electron supply layer 4 / 5 as shown in FIG. 5C.
  • the potential barrier of the etching stopper layer 7 is lowered by virtue of the delta-doped layers 6 , and the resistance between the ohmic electrodes 9 and the electron supply layer 4 / 5 is decreased.
  • the source resistance of the high electron mobility transistor is reduced, and the high-frequency characteristics such as, for example, the noise factor and the gain are improved.
  • the delta-doped layers are removed from the upper surface of the electron supply layer 4 / 5 exposed to the recess 12 . This means that the gate electrode 10 is directly held in contact with the electron supply layer 4 / 5 . This results in a small amount of gate leakage current and a high gate-and-drain withstand voltage.
  • the channel layer 3 and the electron supply layer 4 / 5 as a whole constitute an active layer.
  • FIG. 6 illustrates another high electron mobility transistor embodying the present invention.
  • the high electron mobility transistor is fabricated on a semi- insulating substrate 1 of gallium arsenide.
  • the high electron mobility transistor comprises a buffer layer 2 , a channel layer 3 , an electron supply layer 4 a , delta doped layers 6 , undoped gallium arsenide layer 7 a , cap layers 8 , ohmic electrodes 9 , a gate electrode 10 and a protective layer 14 .
  • the buffer layer 2 is formed of gallium arsenide epitaxially grown on the semi-insulating substrate 1 of gallium arsenide.
  • the channel layer 3 is formed of indium gallium arsenide epitaxially grown on the gallium arsenide buffer layer 2 .
  • the electron supply layer 4 a is formed of n-type gallium arsenide, and the dopant concentration is 1 ⁇ 10 18 /cm 3 in the n-type gallium arsenide electron supply layer 4 a .
  • the n-type gallium arsenide electron supply layer 4 a is 30 nanometers thick.
  • the delta doped layers 6 are similar to those of the first embodiment, and no further description is incorporated hereinbelow for avoiding repetition.
  • the undoped gallium arsenide layers 7 a are 20 nanometers thick.
  • An etching stopper layer may be inserted between the cap layers 8 and the undoped gallium arsenide layers 7 a.
  • the cap layers 8 are formed from a heavily-doped n-type gallium arsenide layer epitaxially grown on the undoped gallium arsenide layers 7 a .
  • the cap layers 8 are 80 nanometers thick, and the dopant concentration is 3 ⁇ 10 18 /cm 3 .
  • the heavily-doped n-type gallium arsenide layer 8 , the undoped gallium arsenide layer 7 a and the delta doped layer 6 are partially removed, and a part of the n-type gallium arsenide layer 4 a is exposed to a recess between the undoped gallium arsenide layers 7 a .
  • the ohmic electrodes 9 are held in contact with the cap layers 8
  • the gate electrode 10 is held in contact with the n-type gallium arsenide electron supply layer 4 a .
  • the protective layer 14 is formed of silicon dioxide, and fills an upper portion of the recess.
  • the high electron mobility transistor is fabricated as follows. The process starts with preparation of the semi-insulating substrate 1 .
  • the gallium arsenide layer 2 , the indium gallium arsenide layer 3 , the n-type gallium arsenide layer 4 a , the delta doped layer 6 , the undoped gallium arsenide layer 7 a and the heavily-doped n-type gallium arsenide layer 8 are enitaxially grown on the major surface of the semi-insulating substrate 1 .
  • a photo-resist etching mask 11 a is formed on the heavily-doped n-type gallium arsenide layer 8 through the photo-lithographic techniques. Using the photo-resist etching mask 11 a , the heavily-doped n- type gallium arsenide layer 8 is partially etched away, and a wide recess 12 a takes place in the heavily-doped n- type gallium arsenide layer 8 . The remaining portions of the heavily-doped n-type gallium arsenide layer 8 serve as the cap layers 8 .
  • the resultant semiconductor structure is shown in FIG. 7A.
  • the etching stopper layer of aluminum gallium arsenide layer is inserted between the undoped gallium arsenide layer 7 a and the heavily-doped n-type gallium arsenide layer 8 , the etching is exactly terminated at the etching stopper layer.
  • Silicon dioxide is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition.
  • the silicon dioxide forms a silicon dioxide layer 14 .
  • a photo-resist etching mask (not shown) is formed on the silicon dioxide layer 14 , and has an opening over the n-type gallium arsenide layer where the gate electrode 10 is to be formed.
  • the silicon dioxide layer is partially etched away, and a gate opening 15 is formed in the silicon dioxide layer 14 as shown in FIG. 7B.
  • the undoped gallium arsenide layer 7 a and the delta-doped layer 6 are partially etched away by using the photo-resist etching mask. This results in a gate recess 12 b , and the part of the n-type gallium arsenide electron supply layer 4 a is exposed to the gate recess 12 b as shown in FIG. 7C.
  • WSi—TiN—Pt—Au alloy is deposited over the entire surface of the resultant semiconductor structure by using a sputtering technique, and the alloy is patterned into the gate electrode 10 by using the photo- lithographic techniques followed by an etching. Finally, the ohmic electrodes 9 of Ni—AuGe alloy is formed on the cap layers 8 , and the high electron mobility transistor is obtained as shown in FIG. 7D.
  • the delta-doped layers 6 lower the potential barriers of the undoped gallium arsenide layers 7 a , and decrease the resistance between the channel layer 3 and the ohmic electrodes 9 . Even though the delta-doped layers 6 are inserted between the undoped gallium arsenide layers 7 a and the n-type gallium arsenide electron supply layer 4 a , the gate electrode 10 is directly held in contact with the n-type gallium arsenide electron supply layer 4 a . For this reason, the leakage current is not increased, and the gate-and-drain withstand voltage (BVgd) is not lowered.
  • BVgd gate-and-drain withstand voltage
  • the etching stopper layers 7 are formed of Al 0.7 Ga 0.3 As.
  • the composition ratio of aluminum is allowed to be different from 0.7 in so far as the aluminum gallium arsenide gives the end point to the etchant.
  • a dry etching technique is available for the step for patterning the heavily-doped n-type gallium arsenide layer 8 .
  • the heavily-doped n-type gallium arsenide layer 8 may be patterned by using another kind of etchant such as, for example, gaseous mixture of BCl 3 and SF 6 or another kind of gaseous mixture of SiCl 4 and SF 6 .
  • the metal-semiconductor field effect transistor implementing the first embodiment may not be equipped with any electron supply layer.
  • the standard metal-semiconductor field effect transistor may have the structure comprising a gallium arsenide buffer layer 2 , an n + Al 0.2 Ga 0.8 As /n ⁇ Al 0.2 Ga 0.8 As channel layer 4 / 5 , delta doped layers 6 , n ⁇ Al 0.7 Ga 0.3 As etching stopper layers 7 and n + GaAs cap layers 8 .
  • the standard metal- semiconductor field effect transistor may be categorized in the metal-semiconductor Schottky field effect transistor.
  • the metal-semiconductor Schottky field effect transistor may comprise a gallium arsenide buffer layer 2 , an n + Al 0.2 Ga 0.8 As /n ⁇ Al 0.2 Ga 0 8 As channel layer 4 / 5 , delta doped layers 6 , n ⁇ Al 0.7 Ga 0.3 As etching stopper layers 7 and n + GaAs cap layers 8 .
  • the undoped gallium arsenide layer 7 a may be replaced with another kind of undoped compound semiconductor layer such as, for example, undoped aluminum gallium arsenide layer or undoped indium gallium arsenide layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

A high electron mobility transistor has a channel layer overlain by an electron supply layer held in contact with a gate electrode, and source/drain electrodes form ohmic contact together with cap layers, and resistive etching stopper are inserted between the cap layers and the electron supply layers for preventing the electron supply layer from over-etching, wherein extremely thin delta-doped layers are formed between the etching stopper layers and the electron supply layer so that the resistance between the electron supply layer and the source/drain electrodes are reduced.

Description

    FIELD OF THE INVENTION
  • This invention relates to a compound semiconductor and, more particularly, to a compound semiconductor device having an etching stopper layer between an active layer and an ohmic electrode. [0001]
    • DESCRIPTION OF THE RELATED ART
  • A heterojunction metal-semiconductor field effect transistor is a typical example of the compound semiconductor device. The high electron mobility transistor is a kind of heterojunction metal- semiconductor field effect transistor, and is featured by an inversion layer at the boundary between an electron supply layer and a channel layer. The heterojunction metal-semiconductor field effect transistor finds a wide variety of application such as, for example, a DBS (Direct Broadcasting Satellite). The compound semiconductor device is expected to have low- noise characteristics and achieve a high-gain. [0002]
  • In order to enhance the mutual conductance, it is known to increase the dopant impurity in the electron supply layer. Reduction of source resistance is also appropriate. However, when the dopant concentration is uniformly increased in the electron supply layer, a problem is encountered in the heterojunction metal-semiconductor field effect transistor in low withstand voltage between the gate electrode and the electron supply layer. [0003]
  • A stepped doping concentration structure has been proposed. When the stepped dopant concentration structure is applied to the electron supply layer, the electron supply layer has a relatively heavy dopant concentration close to the channel layer and a relatively light dopant concentration close to the gate electrode. [0004]
  • FIG. 1 illustrates the prior art high electron mobility transistor with the stepped dopant concentration structure. The prior art high electron mobility transistor is fabricated on a [0005] semi-insulating substrate 1, which is formed of gallium arsenide. The prior art high electron mobility transistor comprises a buffer layer 2, a channel layer 3, an electron supply layer 4/5, cap layers 8, ohmic electrodes 9 and a gate electrode 10. Gallium arsenide is epitaxially grown on the semi-insulating substrate 1, and forms a gallium arsenide layer. The gallium arsenide layer serves as the buffer layer 2. On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer 3. Heavily-doped n-type aluminum gallium arsenide, i.e., n+Al0.2Ga0.8As and lightly-doped n-type aluminum gallium arsenide, i.e., n−Al0.2Ga0.8As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly doped n-type aluminum gallium arsenide layer 5. The dopant concentration is 4×10 18/cm3 (4× 10−18/cm3) in the heavily-doped n-type aluminum gallium arsenide layer 4 and 1×1017/cm3 in the lightly-doped n-type aluminum gallium arsenide layer 5. The heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5 form in combination the electron supply layer 4/5. The heavily-doped n-type aluminum gallium arsenide layer 4 is contiguous to the channel layer 3, and the gate electrode 10 is held in contact with the lightly-doped n-type aluminum gallium arsenide layer 5. The n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5. Thus, the electron supply layer 4/5 has the stepped dopant concentration structure.
  • On the lightly-doped aluminum [0006] gallium arsenide layer 5 is epitaxially grown heavily-doped n-type gallium arsenide from which forms the cap layers 8 of 80 nanometers thick are formed. The dopant concentration is 3×1018/cm3 in the heavily-doped n-type gallium arsenide layer. Namely, the heavily-doped n-type gallium arsenide layer is partially etched so as to expose the electron supply layer 4/5 to a recess between the cap layers 8. The gate electrode 10 is held in contact with the exposed portion of the electron supply layer 5. On the other hand, the ohmic electrodes 9 are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
  • The prior art high electron mobility transistor achieves a large mutual conductance by virtue of the heavily-doped n-type aluminum [0007] gallium arsenide layer 4 as well as a high withstand voltage by virtue of the lightly-doped n-type aluminum gallium arsenide layer 5. However, the threshold voltage and, accordingly, the amount of channel current are liable to fluctuate among the products. This is because of the fact that the etchant is liable to partially remove the lightly-doped n-type aluminum gallium arsenide layer 5 during the formation of the recess.
  • An etching stopper has been proposed as a countermeasure against the problem. The recess is formed by using mixture of citric acid and H[0008] 2O2 as wet etchant. Upon completion of the fabrication process, the prior art high electron mobility transistor has the structure shown in FIG. 2.
  • The prior art high electron mobility transistor is fabricated on a [0009] semi-insulating substrate 1, which is formed of gallium arsenide. The prior art high electron mobility transistor comprises a buffer layer 2, a channel layer 3, an electron supply layer 4/5, etching stopper layers 7, cap layers 8, ohmic electrodes 9 and a gate electrode 10. Gallium arsenide is epitaxially grown on the semi-insulating substrate 1, and forms a gallium arsenide layer. The gallium arsenide layer serves as the buffer layer 2. On the gallium arsenide layer is epitaxially grown indium gallium arsenide which forms an indium gallium arsenide layer serving as the channel layer 3. Heavily-doped n-type aluminum gallium arsenide, i.e., n+Al0.2Ga0 8As and lightly-doped n-type aluminum gallium arsenide, i.e., n−Al0.2Ga0.8As are successively epitaxially grown to 10 nanometers thick and 20 nanometers thick on the indium gallium arsenide layer, and form a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly-doped n-type aluminum gallium arsenide layer 5. The dopant concentration is 4×1018/cm3 in the heavily-doped n-type aluminum gallium arsenide layer 4 and 1×1017/cm3 in the lightly-doped n-type aluminum gallium arsenide layer 5. The heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n- type aluminum gallium arsenide layer 5 form in combination the electron supply layer 4/5. The heavily-doped n-type aluminum gallium arsenide layer 4 is contiguous to the channel layer 3, and the gate electrode 10 is held in contact with the lightly-doped n-type aluminum gallium arsenide layer 5. The n-type dopant concentration is changed at the boundary between the heavily-doped n-type aluminum gallium arsenide layer 4 and the lightly-doped n-type aluminum gallium arsenide layer 5. Thus, the electron supply layer 4/5 has the stepped dopant concentration structure.
  • On the lightly-doped aluminum [0010] gallium arsenide layer 5 is grown lightly-doped n-type aluminum gallium arsenide n−Al0.7Ga0.3As which forms a lightly-doped n-type aluminum gallium arsenide layer. The etching stopper layers 7 are formed from the lightly-doped n-type aluminum gallium arsenide layer. Heavily-doped n-type gallium arsenide is epitaxially grown to 80 nanometers thick on the lightly-doped n-type aluminum gallium arsenide layer 7, and forms a heavily-doped n-type gallium arsenide layer. The cap layers 8 are formed from the heavily-doped n-type gallium arsenide layer. The dopant concentration is 3×1018/cm3 in the heavily-doped n-type gallium arsenide layer. The heavily-doped n-type gallium arsenide layer 8 and the lightly-doped aluminum gallium arsenide layer 7 are partially etched so as to expose the electron supply layer 4/5 to a recess between the cap layers 8. The gate electrode 10 is held in contact with the exposed portion of the electron supply layer 5. On the other hand, the ohmic electrodes 9 are held in contact with the cap layers on both sides of the recess, and serve as a source electrode and a drain electrode.
  • The lightly-doped n-type Al[0011] 0.7Ga0.3As layer 7 gives an end point to the wet etchant in the formation of the recess, and prevents the lightly doped Al0.8Ga0 2As layer 5 from the wet etchant. As a result, the electron supply layer 4/5 is constant in thickness, and the electron supply layer 4/5 keeps the threshold constant among products.
  • However, a problem is encountered in the prior art high electron mobility transistor shown in FIG. 2 in the high source resistance. [0012]
    • SUMMARY OF THE INVENTION
  • It is therefore an important object of the present invention to provide a compound semiconductor device, which is reduced in source resistance without sacrifice of the constant thickness of the active layer. [0013]
  • It is also an important object of the present invention to provide a process for fabricating the compound semiconductor device. [0014]
  • The present inventors contemplated the problem inherent in the prior art high electron mobility transistor shown in FIG. 2, and noticed that the n[0015] −Al0.7Ga0.3As etching stopper layers 7 were left between the electron supply layer 5 and the cap layers 8. Aluminum had the large composition ratio in the n−Al0.7Ga0.3As. The aluminum was a large amount of dx center, and the dx centers were not activated with the n-type dopant impurity, i.e., silicon. Even though the silicon was doped in the Al0.7Ga0.3As, a non-ignoreable amount of n-type dopant impurities were invalid, and the lightly-doped Al0.7Ga0.3As layer exhibited high resistivity. The present inventors replaced the lightly-doped n−Al0.7Ga0.3As etching stopper layers 7 with non-doped etching stopper layers. The high electron mobility transistor also exhibited large source resistance. The present inventors concluded that the resistance was to be reduced without deleting the etching stopper layer was required.
  • To accomplish the object, the present invention proposes to reduce the potential barrier between cap layers and an active layer by using delta-doped layers. [0016]
  • In accordance with one aspect of the present invention, there is provided a compound semiconductor device fabricated on a substrate comprising a multiple-layered structure including an active layer, plural cap layers respectively located over plural portions of the active layer, plural highly-resistive layers formed between the multiple-layered structure and the plural cap layers so as to form a recess located over a part of the multiple- layered structure and between the plural cap layers, plural delta-doped layers formed between the plural highly-resistive layers and the multiple- layered structure for decreasing potential barriers of the plural highly-resistive layers, a first electrode held in contact with the part of the multiple- layered structure for controlling the amount of current flowing through the active layer, and second electrodes respectively formed on the plural cap layers for providing current paths from and to the active layer through the plural cap layers, the plural highly-resistive layers and the plural delta-doped layers. [0017]
  • In accordance with another aspect of the present invention, there is provided a process for fabricating a compound semiconductor device comprising the steps of a) producing a multiple-layered structure having an active layer, a delta-doped layer over the active layer, a highly resistive layer over the delta-doped layer and a highly conductive layer over the delta-doped layer on a semi-insulating substrate, b) removing a part of the highly conductive layer so as to expose a part of the highly resistive layer to a first opening formed between remaining portions of the highly conductive layer serving as plural cap layers, c) removing the part of the highly resistive layer and a part of the delta-doped layer thereunder so as to expose a part of the active layer to a second opening formed between plural delta doped layers respectively overlain by highly resistive layers and d) completing a compound semiconductor device having a first electrode held in contact with the part of the active layer and second electrodes respectively held in contact with the plural cap layers.[0018]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The features and advantages of the compound semiconductor device and the fabrication process will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: [0019]
  • FIG. 1 is a cross sectional view showing the prior art high electron mobility transistor with the stepped dopant concentration structure; [0020]
  • FIG. 2 is a cross sectional view showing the prior art high electron mobility transistor with the etching stopper between the electron supply layer and the cap layers; [0021]
  • FIG. 3 is a cross sectional view showing the structure of a high electron mobility transistor according to the present invention; [0022]
  • FIGS. [0023] 4 is an energy band diagram showing the energy band created in the high electron mobility transistor;
  • FIGS. 5A to [0024] 5C are cross sectional views showing a process for fabricating the high electron mobility transistor according to the present invention;
  • FIG. 6 is a cross sectional view showing the structure of a heterojunction metal-semiconductor field effect transistor according to the present invention; and [0025]
  • FIGS. 7A to [0026] 7D are cross sectional views showing a process for fabricating the heterojunction metal-semiconductor field effect transistor according to the present invention.
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • First Embodiment [0027]
  • Referring to FIG. 3 of the drawings, a high electron mobility transistor embodying the present invention is fabricated on a semi- insulating [0028] substrate 1 of gallium arsenide. The high electron mobility transistor comprises a buffer layer 2, a channel layer 3, an electron supply layer 4/5, delta doped layers 6, etching stopper layers 7, cap layers 8, ohmic electrodes 9 and a gate electrode 10. The delta doped layers are referred to as “planar dope layer” or “pulse dope layer” in several articles. In other words, the term “delta doped layer” is synonymous with the term “planar dope layer” and the term “pulse dope layer”. The delta doped layers 6 are hereinlater described in detail.
  • The [0029] buffer layer 2 is formed of gallium arsenide epitaxially grown on the semi-insulating substrate 1 of gallium arsenide. The channel layer 3 is formed of indium gallium arsenide epitaxially grown on the gallium arsenide buffer layer 2. The electron supply layer 4/5 has the stepped dopant concentration structure, and the stepped dopant concentration structure is implemented by a heavily-doped n-type aluminum gallium arsenide layer 4 and a lightly-doped n-type aluminum gallium arsenide layer 5. The heavily-doped n- type aluminum gallium arsenide and the lightly-doped n-type aluminum gallium arsenide have the composition expressed as Al0.2Ga0.8As. The heavily-doped n-type aluminum gallium arsenide layer 4 is 10 nanometers thick, and the dopant concentration is 4×1018/cm3 in the heavily-doped n-type aluminum gallium arsenide layer 4. On the other hand, the lightly-doped n-type aluminum gallium arsenide layer 5 is 20 nanometers thick, and the dopant concentration is 1×1017/cm3 in the lightly-doped n-type aluminum gallium arsenide layer 5.
  • The delta doped [0030] layers 6 are formed by supplying Group-V element, i.e., arsenic (As) and silicon, only, and are as thin as a single atom to several atoms. The silicon is delta doped. For this reason, the dopant impurity, i.e., silicon is heavily contained in the delta doped layer 6. The dopant impurity concentration of the delta-doped layers 6 are heavier than that of the electron supply layer. In this instance, the delta doped layers 6 contain the silicon at 6×1012/cm2. The delta doped layers 6 contain only one kind of dopant impurity so that the tunneling phenomenon takes place at the boundaries. For this reason, the carriers can pass a potential barrier larger in height than the energy thereof.
  • The [0031] etching stopper layers 7 are formed of lightly-doped aluminum gallium arsenide epitaxially grown on the delta doped layers 6. The lightly-doped aluminum gallium arsenide is different in composition from that of the electron supply layer 4/5, and is expressed as Al0.7Ga0.3As. Although silicon is lightly doped into the aluminum gallium arsenide Al0.7Ga0.3As, the aluminum gallium arsenide Al0.7Ga0.3As contains a large amount of dx centers, and the dx centers deactivate the silicon. For this reason, the effective carrier density is drastically decreased in the aluminum gallium arsenide etching stopper layers 7.
  • The cap layers [0032] 8 are formed from a heavily-doped n-type gallium arsenide layer epitaxially grown on the aluminum gallium arsenide etching stopper layers 7. The cap layers 8 are 80 nanometers thick, and the dopant concentration is 3×1018/cm3.
  • The heavily-doped n-type [0033] gallium arsenide layer 8, the lightly-doped aluminum gallium arsenide layer 7 and the delta doped layer 6 are partially etched away so that the electron supply layer 5 is exposed to a recess between the cap layers 8. The ohmic electrodes 9 are held in contact with the cap layers 8, and the gate electrode 10 is held in contact with the lightly-doped aluminum gallium arsenide layer 5 of the electron supply layer.
  • The energy band shown in FIG. 4 is created in the high electron mobility transistor according to the present invention. If the delta doped [0034] layers 6 are not inserted between the electron supply layer 4/5 and the etching stopper layers, the bottom edge of conduction band is represented by broken line. The potential barriers between the cap layers 8 and the etching stopper layers 7 and between the etching stopper layers 7 and the electron supply layer 5 are wide. The delta doped layers 6 make the potential level of the etching stopper layers 7 lower. The potential barriers between the cap layers 8 and the etching stopper layers 7 and between the etching stopper layers 7 and the electron supply layer 5 are made narrow. As a result, the carriers or electrons are smoothly moved between the ohmic electrodes 9 and the channel layer 3, and, accordingly, the resistance is decreased.
  • The [0035] etching stopper 7 keeps the electron supply layer 4/5 constant in thickness among the products. The electron supply layer 4/5 with constant thickness is effective against the fluctuation of threshold voltage. Thus, the high electron mobility transistor according to the present invention achieves the low resistance without sacrifice of the constant thickness of the electron supply layer 4/5.
  • The high electron mobility transistor shown in FIG. 3 is fabricated through a process shown in FIGS. 5A to [0036] 5C. In the following description, compound semiconductor layers are labeled with the references designating the layers of the high electron mobility transistor shown in FIG. 3.
  • The process starts with preparation of the semi- insulating [0037] substrate 1. The gallium arsenide layer 2, the indium gallium arsenide layer 3, the heavily-doped aluminum gallium arsenide layer 4, the lightly-doped aluminum gallium arsenide layer 5, the delta doped layers 6, the aluminum gallium arsenide layer 7 and the heavily-doped gallium arsenide layer 8 are epitaxially grown on the semi-insulating substrate 1 in succession. Nickel-gold-germanium alloy Ni/AuGe is grown on the heavily-doped gallium arsenide layer 8, and the ohmic electrodes 9 are formed from the nickel-gold- germanium alloy layer. The resultant semiconductor structure in this stage is shown in FIG. 5A.
  • Subsequently, a photo-resist [0038] mask 11 is provided on the resultant semiconductor structure by using a photo- lithography. Namely, photo-resist solution is spread over the resultant semiconductor structure, and is baked so as to form a photo-resist layer. A pattern image is transferred from a photo-mask to the photo-resist layer so as to produce a latent image in the photoresist layer. The latent image is developed. Then, the photo-resist mask 11 is left on the resultant semiconductor structure. A part of the heavily-doped gallium arsenide layer 8 is exposed to the opening formed in the photo-resist mask 11. Using wet etchant containing citric acid and hydrogen peroxide H2O2, the heavily-doped gallium arsenide layer 8 is partially removed. Since the wet etchant has the selectivity larger to the gallium arsenide than to the lightly-doped n-type aluminum gallium arsenide Al0.7Ga0.3As, the wet etching is terminated on the lightly-doped n- type aluminum gallium arsenide Al0.7Ga0.3As layer 7, and a recess 12 is formed in the heavily-doped n-type gallium arsenide layer 8 as shown in FIG. 5B. Thus, the lightly-doped n-type aluminum gallium arsenide Al0.7Ga0.3As layer 7 serves as an etching stopper. While the lightly.-doped n- type aluminum gallium arsenide Al0.7Ga0.3As layer 7 is being etched with the wet etchant, the exposed portion of the lightly-doped n-type aluminum gallium arsenide Al0.7Ga0.3As etching stopper layer 7 is oxidized, and aluminum oxide Al2O3 is left on the delta-doped layers 6.
  • As described hereinbefore, the lightly-doped n- type aluminum gallium arsenide Al[0039] 0.7Ga0.3As layer 7 contains a large amount of dx centers. For this reason, the dopant impurity, i.e., silicon atoms are hardly activated, and the actual carrier concentration is drastically reduced. This means that the lightly-doped n-type aluminum gallium arsenide Al0.7Ga0.3As layer 7 is highly resistive.
  • The aluminum oxide layer and the delta-doped [0040] layers 6 under the aluminum oxide layer are etched away by using hydrochloric acid. The lightly-doped n-type aluminum gallium arsenide layer 5 is hardly etched so that the high electron mobility transistor is constant in threshold and the amount of channel current among products. Finally, titanium- aluminum alloy is deposited over the entire surface by using an evaporation technique, and the photo-resist mask 11 is stripped off together with the titanium-aluminum alloy deposited thereover. The gate electrode 10 is left on the electron supply layer 4/5 as shown in FIG. 5C.
  • As will be understood from the foregoing description, the potential barrier of the [0041] etching stopper layer 7 is lowered by virtue of the delta-doped layers 6, and the resistance between the ohmic electrodes 9 and the electron supply layer 4/5 is decreased. As a result, the source resistance of the high electron mobility transistor is reduced, and the high-frequency characteristics such as, for example, the noise factor and the gain are improved.
  • The delta-doped layers are removed from the upper surface of the [0042] electron supply layer 4/5 exposed to the recess 12. This means that the gate electrode 10 is directly held in contact with the electron supply layer 4/5. This results in a small amount of gate leakage current and a high gate-and-drain withstand voltage.
  • In the first embodiment, the [0043] channel layer 3 and the electron supply layer 4/5 as a whole constitute an active layer.
  • Second Embodiment [0044]
  • FIG. 6 illustrates another high electron mobility transistor embodying the present invention. The high electron mobility transistor is fabricated on a semi- insulating [0045] substrate 1 of gallium arsenide. The high electron mobility transistor comprises a buffer layer 2, a channel layer 3, an electron supply layer 4 a, delta doped layers 6, undoped gallium arsenide layer 7 a, cap layers 8, ohmic electrodes 9, a gate electrode 10 and a protective layer 14.
  • The [0046] buffer layer 2 is formed of gallium arsenide epitaxially grown on the semi-insulating substrate 1 of gallium arsenide. The channel layer 3 is formed of indium gallium arsenide epitaxially grown on the gallium arsenide buffer layer 2. The electron supply layer 4 a is formed of n-type gallium arsenide, and the dopant concentration is 1×1018/cm3 in the n-type gallium arsenide electron supply layer 4 a. The n-type gallium arsenide electron supply layer 4 a is 30 nanometers thick.
  • The delta doped [0047] layers 6 are similar to those of the first embodiment, and no further description is incorporated hereinbelow for avoiding repetition. The undoped gallium arsenide layers 7 a are 20 nanometers thick. An etching stopper layer may be inserted between the cap layers 8 and the undoped gallium arsenide layers 7 a.
  • The cap layers [0048] 8 are formed from a heavily-doped n-type gallium arsenide layer epitaxially grown on the undoped gallium arsenide layers 7 a. The cap layers 8 are 80 nanometers thick, and the dopant concentration is 3×1018/cm3.
  • The heavily-doped n-type [0049] gallium arsenide layer 8, the undoped gallium arsenide layer 7 a and the delta doped layer 6 are partially removed, and a part of the n-type gallium arsenide layer 4 a is exposed to a recess between the undoped gallium arsenide layers 7 a. The ohmic electrodes 9 are held in contact with the cap layers 8, and the gate electrode 10 is held in contact with the n-type gallium arsenide electron supply layer 4 a. The protective layer 14 is formed of silicon dioxide, and fills an upper portion of the recess.
  • The high electron mobility transistor is fabricated as follows. The process starts with preparation of the [0050] semi-insulating substrate 1. The gallium arsenide layer 2, the indium gallium arsenide layer 3, the n-type gallium arsenide layer 4 a, the delta doped layer 6, the undoped gallium arsenide layer 7 a and the heavily-doped n-type gallium arsenide layer 8 are enitaxially grown on the major surface of the semi-insulating substrate 1.
  • A photo-resist etching mask [0051] 11 a is formed on the heavily-doped n-type gallium arsenide layer 8 through the photo-lithographic techniques. Using the photo-resist etching mask 11 a, the heavily-doped n- type gallium arsenide layer 8 is partially etched away, and a wide recess 12 a takes place in the heavily-doped n- type gallium arsenide layer 8. The remaining portions of the heavily-doped n-type gallium arsenide layer 8 serve as the cap layers 8. The resultant semiconductor structure is shown in FIG. 7A. In the case where the etching stopper layer of aluminum gallium arsenide layer is inserted between the undoped gallium arsenide layer 7 a and the heavily-doped n-type gallium arsenide layer 8, the etching is exactly terminated at the etching stopper layer.
  • Silicon dioxide is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition. The silicon dioxide forms a [0052] silicon dioxide layer 14. A photo-resist etching mask (not shown) is formed on the silicon dioxide layer 14, and has an opening over the n-type gallium arsenide layer where the gate electrode 10 is to be formed. Using the photo-resist etching mask, the silicon dioxide layer is partially etched away, and a gate opening 15 is formed in the silicon dioxide layer 14 as shown in FIG. 7B.
  • Subsequently, the undoped [0053] gallium arsenide layer 7 a and the delta-doped layer 6 are partially etched away by using the photo-resist etching mask. This results in a gate recess 12 b, and the part of the n-type gallium arsenide electron supply layer 4 a is exposed to the gate recess 12 b as shown in FIG. 7C.
  • WSi—TiN—Pt—Au alloy is deposited over the entire surface of the resultant semiconductor structure by using a sputtering technique, and the alloy is patterned into the [0054] gate electrode 10 by using the photo- lithographic techniques followed by an etching. Finally, the ohmic electrodes 9 of Ni—AuGe alloy is formed on the cap layers 8, and the high electron mobility transistor is obtained as shown in FIG. 7D.
  • As similar to the high electron mobility transistor implementing the first embodiment, the delta-doped [0055] layers 6 lower the potential barriers of the undoped gallium arsenide layers 7 a, and decrease the resistance between the channel layer 3 and the ohmic electrodes 9. Even though the delta-doped layers 6 are inserted between the undoped gallium arsenide layers 7 a and the n-type gallium arsenide electron supply layer 4 a, the gate electrode 10 is directly held in contact with the n-type gallium arsenide electron supply layer 4 a. For this reason, the leakage current is not increased, and the gate-and-drain withstand voltage (BVgd) is not lowered.
  • Although particular embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. [0056]
  • In the first embodiment, the [0057] etching stopper layers 7 are formed of Al0.7Ga0.3As. The composition ratio of aluminum is allowed to be different from 0.7 in so far as the aluminum gallium arsenide gives the end point to the etchant.
  • A dry etching technique is available for the step for patterning the heavily-doped n-type [0058] gallium arsenide layer 8. The heavily-doped n-type gallium arsenide layer 8 may be patterned by using another kind of etchant such as, for example, gaseous mixture of BCl3 and SF6 or another kind of gaseous mixture of SiCl4 and SF6.
  • The metal-semiconductor field effect transistor implementing the first embodiment may not be equipped with any electron supply layer. The standard metal-semiconductor field effect transistor may have the structure comprising a gallium [0059] arsenide buffer layer 2, an n+Al0.2Ga0.8As /n−Al0.2Ga0.8As channel layer 4/5, delta doped layers 6, n−Al0.7Ga0.3As etching stopper layers 7 and n+GaAs cap layers 8. The standard metal- semiconductor field effect transistor may be categorized in the metal-semiconductor Schottky field effect transistor. The metal-semiconductor Schottky field effect transistor may comprise a gallium arsenide buffer layer 2, an n+Al0.2Ga0.8As /n−Al0.2Ga0 8As channel layer 4/5, delta doped layers 6, n−Al0.7Ga0.3As etching stopper layers 7 and n+GaAs cap layers 8.
  • The undoped [0060] gallium arsenide layer 7 a may be replaced with another kind of undoped compound semiconductor layer such as, for example, undoped aluminum gallium arsenide layer or undoped indium gallium arsenide layer.

Claims (18)

What is claimed is:
1. A compound semiconductor device fabricated on a substrate, comprising:
a multiple-layered structure including an active layer;
plural cap layers respectively located over plural portions of said active layer;
plural highly-resistive layers formed between said multiple-layered structure and said plural cap layers so as to form a recess located over a part of said multiple-layered structure and between said plural cap layers;
plural delta-doped layers formed between said plural highly-resistive layers and said multiple-layered structure for decreasing potential barriers of said plural highly-resistive layers;
a first electrode held in contact with said part of said multiple-layered structure for controlling the amount of current flowing through said active layer; and
second electrodes respectively formed on said plural cap layers for providing current paths from and to said active layer through said plural cap layers, said plural highly-resistive layers and said plural delta-doped layers.
2. The compound semiconductor device as set forth in claim 1, in which said plural delta-doped layers are thin so that a tunneling phenomenon takes place.
3. The compound semiconductor device as set forth in claim 1, in which the thickness of said plural delta-doped layers is equal to a single atom to several atoms.
4. The compound semiconductor device as set forth in claim 1, in which said plural delta doped layers contain only one kind of dopant impurity.
5. The compound semiconductor device as set forth in claim 1, in which said active layer has a conductive channel layer for said current.
6. The compound semiconductor device as set forth in claim 5, in which said active layer further has a carrier supply layer for producing an inversion layer at the boundary between said carrier supply layer and said conductive channel layer.
7. The compound semiconductor device as set forth in claim 6, in which said carrier supply layer has a large dopant concentration in a first portion close to the boundary formed with said channel layer and a small dopant concentration in a second portion close to said gate electrode.
8. The compound semiconductor device as set forth in claim 1, in which said plural highly-resistive layers serve as an etching stopper for preventing said active layer from an etchant used for patterning said plural cap layers.
9. The compound semiconductor device as set forth in claim 1, in which said plural highly-resistive layers are formed of undoped compound semiconductor.
10. A process for fabricating a compound semiconductor device, comprising the steps of:
a) producing a multiple-layered structure having an active layer, a delta-doped layer over said active layer, a highly resistive layer over said delta-doped layer and a highly conductive layer over said delta-doped layer on a semi-insulating substrate;
b) removing a part of said highly conductive layer so as to expose a part of said highly resistive layer to a first opening formed between remaining portions of said highly conductive layer serving as plural can layers;
c) removing said part of said highly resistive layer and a part of said delta-doped layer thereunder so as to expose a part of said active layer to a second opening formed between plural delta doped layers respectively overlain by highly resistive layers; and
d) completing a compound semiconductor device having a first electrode held in contact with said part of said active layer and second electrodes respectively held in contact with said plural cap layers.
11. The process as set forth in claim 10, in which said highly resistive layer serves as an etching stopper carried out in said step b) so as to prevent said active layer from a first etchant.
12. The process as set forth in claim 11, in which step b) includes the sub-steps of
b-1) forming an etching mask on said highly conductive layer, and
b-2) exposing said highly conductive layer to said first etchant having a large selectivity to a first kind of compound semiconductor forming said highly conductive layer with respect to a second kind of compound semiconductor forming said highly resistive layer.
13. The process as set forth in claim 12, in which said first etchant contains an oxidizing agent for producing an oxide from said second kind of compound semiconductor.
14. The process as set forth in claim 13, in which a second etchant is used for removing said oxide and said part of said delta-doped layer, and has a large selectivity to said oxide and said delta-doped layer with respect to a third kind of compound semiconductor forming said active layer.
15. The process as set forth in claim 13, in which said oxidizing agent is hydrogen peroxide, and said first kind of compound semiconductor and said second kind of compound semiconductor contain a negligible amount of aluminum and a large amount of aluminum, respectively.
16. The process as set forth in claim 15, in which said first etchant further contains citric acid, and said first kind of compound semiconductor and said second kind of compound semiconductor are gallium arsenide and aluminum gallium arsenide, respectively.
17. The process as set forth in claim 10, in which said step b) includes the sub-steps of
b-1) depositing an oxide over said highly conductive layer for forming an oxide layer,
b-2) partially removing said oxide layer for forming an etching mask, and
b-3) etching said part of said highly conductive layer by using said etching mask.
18. The process as set forth in claim 17, in which said etching mask serves as a protective layer surrounding said first electrode.
US10/191,435 1999-11-16 2002-07-10 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof Abandoned US20020187623A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/191,435 US20020187623A1 (en) 1999-11-16 2002-07-10 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP32619399A JP3371871B2 (en) 1999-11-16 1999-11-16 Method for manufacturing semiconductor device
JP11-326193 1999-11-16
US09/711,505 US6627473B1 (en) 1999-11-16 2000-11-14 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof
US10/191,435 US20020187623A1 (en) 1999-11-16 2002-07-10 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US09/711,505 Division US6627473B1 (en) 1999-11-16 2000-11-14 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

Publications (1)

Publication Number Publication Date
US20020187623A1 true US20020187623A1 (en) 2002-12-12

Family

ID=18185070

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/711,505 Expired - Fee Related US6627473B1 (en) 1999-11-16 2000-11-14 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof
US10/191,435 Abandoned US20020187623A1 (en) 1999-11-16 2002-07-10 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US09/711,505 Expired - Fee Related US6627473B1 (en) 1999-11-16 2000-11-14 Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof

Country Status (2)

Country Link
US (2) US6627473B1 (en)
JP (1) JP3371871B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148182A1 (en) * 2005-01-03 2006-07-06 Suman Datta Quantum well transistor using high dielectric constant dielectric layer
US20070235824A1 (en) * 2006-03-31 2007-10-11 Titash Rakshit Novel schottky barrier metal-germanium contact in metal-germanium-metal photodetectors
US20070235877A1 (en) * 2006-03-31 2007-10-11 Miriam Reshotko Integration scheme for semiconductor photodetectors on an integrated circuit chip
US20080142786A1 (en) * 2006-12-13 2008-06-19 Suman Datta Insulated gate for group iii-v devices
US20090085063A1 (en) * 2007-09-28 2009-04-02 Fujitsu Limited Compound semiconductor device with t-shaped gate electrode and its manufacture
US20140017885A1 (en) * 2012-07-11 2014-01-16 Electronics And Telecommunications Research Institute Method of manufacturing field effect type compound semiconductor device
US20140291774A1 (en) * 2013-03-29 2014-10-02 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US20210280467A1 (en) * 2018-12-10 2021-09-09 Filnex Inc. Semiconductor substrate, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003174039A (en) * 2001-09-27 2003-06-20 Murata Mfg Co Ltd Heterojunction field effect transistor
US6838325B2 (en) * 2002-10-24 2005-01-04 Raytheon Company Method of forming a self-aligned, selectively etched, double recess high electron mobility transistor
KR100475122B1 (en) * 2002-12-20 2005-03-10 삼성전자주식회사 Semiconductor device fabricating method for improving a silicon contact resistance
US6867078B1 (en) * 2003-11-19 2005-03-15 Freescale Semiconductor, Inc. Method for forming a microwave field effect transistor with high operating voltage
US7550783B2 (en) * 2004-05-11 2009-06-23 Cree, Inc. Wide bandgap HEMTs with source connected field plates
US7573078B2 (en) * 2004-05-11 2009-08-11 Cree, Inc. Wide bandgap transistors with multiple field plates
US9773877B2 (en) * 2004-05-13 2017-09-26 Cree, Inc. Wide bandgap field effect transistors with source connected field plates
US7238560B2 (en) * 2004-07-23 2007-07-03 Cree, Inc. Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US7229903B2 (en) * 2004-08-25 2007-06-12 Freescale Semiconductor, Inc. Recessed semiconductor device
WO2006080109A1 (en) * 2005-01-25 2006-08-03 Fujitsu Limited Semiconductor device provided with mis structure and method for manufacturing the same
US11791385B2 (en) * 2005-03-11 2023-10-17 Wolfspeed, Inc. Wide bandgap transistors with gate-source field plates
US20080001181A1 (en) * 2006-06-28 2008-01-03 Titash Rakshit Complementarily doped metal-semiconductor interfaces to reduce dark current in MSM photodetectors
JP5105160B2 (en) * 2006-11-13 2012-12-19 クリー インコーポレイテッド Transistor
JP5526353B2 (en) * 2007-08-03 2014-06-18 旭化成エレクトロニクス株式会社 High electron mobility transistor
KR101243836B1 (en) * 2009-09-04 2013-03-20 한국전자통신연구원 Semiconductor devices and methods forming thereof
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
JP2013131650A (en) * 2011-12-21 2013-07-04 Fujitsu Ltd Semiconductor device and method of manufacturing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
WO2014071049A2 (en) 2012-10-31 2014-05-08 Suvolta, Inc. Dram-type device with low variation transistor peripheral circuits, and related methods
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US9847411B2 (en) 2013-06-09 2017-12-19 Cree, Inc. Recessed field plate transistor structures
US9679981B2 (en) 2013-06-09 2017-06-13 Cree, Inc. Cascode structures for GaN HEMTs
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030032154A1 (en) * 2001-01-30 2003-02-13 Yizhong Gu Human LCCL domain containing protein

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4780748A (en) * 1986-06-06 1988-10-25 American Telephone & Telegraph Company, At&T Bell Laboratories Field-effect transistor having a delta-doped ohmic contact
JPH01166568A (en) 1987-12-23 1989-06-30 Hitachi Ltd Semiconductor device
US5172197A (en) * 1990-04-11 1992-12-15 Hughes Aircraft Company Hemt structure with passivated donor layer
US5313093A (en) * 1991-10-29 1994-05-17 Rohm Co., Ltd. Compound semiconductor device
EP0565054A3 (en) * 1992-04-09 1994-07-27 Hughes Aircraft Co N-type antimony-based strained layer superlattice and fabrication method
JP3135185B2 (en) 1993-03-19 2001-02-13 三菱電機株式会社 Semiconductor etching solution, semiconductor etching method, and method for determining GaAs surface
JP3368452B2 (en) 1995-04-25 2003-01-20 富士通株式会社 Compound semiconductor device and method of manufacturing the same
JP2739852B2 (en) 1995-10-16 1998-04-15 日本電気株式会社 Method for manufacturing semiconductor device
US6160274A (en) * 1996-04-18 2000-12-12 The United States Of America As Represented By The Secretary Of The Army Reduced 1/f low frequency noise high electron mobility transistor
JPH11214676A (en) 1998-01-22 1999-08-06 Oki Electric Ind Co Ltd Semiconductor device
JP3370929B2 (en) 1998-04-10 2003-01-27 株式会社デンソー Photoresponsive high electron mobility transistor
KR100262940B1 (en) * 1998-05-29 2000-09-01 이계철 Method for fabricating compound semiconductor device using lift-off of insulator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030032154A1 (en) * 2001-01-30 2003-02-13 Yizhong Gu Human LCCL domain containing protein

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060148182A1 (en) * 2005-01-03 2006-07-06 Suman Datta Quantum well transistor using high dielectric constant dielectric layer
WO2006074197A1 (en) * 2005-01-03 2006-07-13 Intel Corporation Quantum well transistor using high dielectric constant dielectric layer
GB2438331A (en) * 2005-01-03 2007-11-21 Intel Corp Quantum well transistor using high dielectric constant dielectric layer
KR100948211B1 (en) * 2005-01-03 2010-03-18 인텔 코오퍼레이션 Quantum well transistor using high dielectric constant dielectric layer
GB2438331B (en) * 2005-01-03 2010-10-13 Intel Corp Quantum well transistor using high dielectric constant dielectric layer
US20070235824A1 (en) * 2006-03-31 2007-10-11 Titash Rakshit Novel schottky barrier metal-germanium contact in metal-germanium-metal photodetectors
US20070235877A1 (en) * 2006-03-31 2007-10-11 Miriam Reshotko Integration scheme for semiconductor photodetectors on an integrated circuit chip
US7700975B2 (en) * 2006-03-31 2010-04-20 Intel Corporation Schottky barrier metal-germanium contact in metal-germanium-metal photodetectors
US20080142786A1 (en) * 2006-12-13 2008-06-19 Suman Datta Insulated gate for group iii-v devices
WO2008076527A3 (en) * 2006-12-13 2011-06-23 Intel Corporation Insulated gate for group iii-v devices
US7906417B2 (en) * 2007-09-28 2011-03-15 Fujitsu Limited Compound semiconductor device with T-shaped gate electrode and its manufacture
US20110127545A1 (en) * 2007-09-28 2011-06-02 Fujitsu Limited Compound semiconductor device with t-shaped gate electrode
US20090085063A1 (en) * 2007-09-28 2009-04-02 Fujitsu Limited Compound semiconductor device with t-shaped gate electrode and its manufacture
US8183558B2 (en) 2007-09-28 2012-05-22 Fujitsu Limited Compound semiconductor device with T-shaped gate electrode
US20140017885A1 (en) * 2012-07-11 2014-01-16 Electronics And Telecommunications Research Institute Method of manufacturing field effect type compound semiconductor device
US8841154B2 (en) * 2012-07-11 2014-09-23 Electronics And Telecommunications Research Institute Method of manufacturing field effect type compound semiconductor device
US20140291774A1 (en) * 2013-03-29 2014-10-02 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US9123792B2 (en) * 2013-03-29 2015-09-01 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US9484446B2 (en) 2013-03-29 2016-11-01 Sumitomo Electric Device Innovations, Inc. Semiconductor device and method for manufacturing the same
US20210280467A1 (en) * 2018-12-10 2021-09-09 Filnex Inc. Semiconductor substrate, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US11894272B2 (en) * 2018-12-10 2024-02-06 Filnex Inc. Semiconductor substrate, method for manufacturing semiconductor substrate and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
US6627473B1 (en) 2003-09-30
JP2001144110A (en) 2001-05-25
JP3371871B2 (en) 2003-01-27

Similar Documents

Publication Publication Date Title
US6627473B1 (en) Compound semiconductor device with delta doped layer under etching stopper layer for decreasing resistance between active layer and ohmic electrode and process of fabrication thereof
JP3111985B2 (en) Field-effect transistor
US7071499B2 (en) Heterojunction field effect type semiconductor device having high gate turn-on voltage and low on-resistance and its manufacturing method
US4889831A (en) Method of forming a high temperature stable ohmic contact to a III-V substrate
US6822307B2 (en) Semiconductor triode device having a compound-semiconductor channel layer
JP2000077651A (en) Compound semiconductor device and its manufacture
US5610410A (en) III-V compound semiconductor device with Schottky electrode of increased barrier height
JPH03229426A (en) Integrated circuit and manufacture there- of
US5321302A (en) Heterojunction bipolar transistor having base structure for improving both cut-off frequency and maximum oscillation frequency
US5627090A (en) Semiconductor element and process for production for the same
US20040016941A1 (en) Hetero-junction bipolar transistor and a manufacturing method of the same
JP3396579B2 (en) N-type HIGFET and method
JP2746482B2 (en) Field effect transistor and method for manufacturing the same
US5939737A (en) High-speed compound semiconductor device having a minimized parasitic capacitance and resistance
US6278144B1 (en) Field-effect transistor and method for manufacturing the field effect transistor
US5672890A (en) Field effect transistor with lightly doped drain regions
JP3119248B2 (en) Field effect transistor and method of manufacturing the same
US5231040A (en) Method of making a field effect transistor
JP3952383B2 (en) Compound field effect semiconductor device
JP2002064183A (en) Semiconductor device and manufacturing method thereof
JP3767759B2 (en) Field effect semiconductor device
EP0394590A2 (en) Field effect transistors and method of making a field effect transistor
JP3125574B2 (en) Method for manufacturing compound semiconductor device
JPH11176839A (en) Semiconductor device and its manufacture
JP3099874B2 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: NEC ELECTRONICS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEC CORPORATION;REEL/FRAME:013790/0699

Effective date: 20021101

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION