JPH1098056A - Field-effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a FET and its manufacturing method in which high frequency and improvement of low voltage operation are realized without being accompanied with deterioration of a FET characteristics. SOLUTION: The first and second semiconductor layers 3 and 4, acting as channel areas, are laminated in this order, and the top surface of the second semiconductor layer 4 is overlaid with the third semiconductor layer 5 so that the distance from the bottom surface of a recess, formed by etching a part of the third semiconductor layer 5, to the surface of the second semiconductor layer 4 is about 0.03-0.10μm. Further more, the recess is provided with an opening hole, reaching the surface of the second semiconductor layer 4 and having a length of 0.2μm in gate length direction. A gate electrode 8 is formed, so that its lower buried part 8a fills the opening hole to be brought into contact with the second semiconductor layer 4, and further that a main body part 8b of the electrode is formed on a part of the top surface of the third semiconductor layer near the opening hole, including the upper part of the opening hole of the bottom surface of the recess.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter, referred to as an FET) and a method of manufacturing the same, and more particularly to improvement of characteristics of the field effect transistor.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view showing a conventional FET. In the figure, 1 is a semi-insulating substrate, 2 is a buffer layer,
Reference numeral 30 denotes an n-GaAs active layer, 6 denotes a source electrode, 7 denotes a drain electrode, and 16 denotes a gate electrode.

In general, it is necessary to reduce the rising voltage in order to increase the frequency of the FET and to improve the low-voltage operation. To reduce the rising voltage, the gate length (hereinafter referred to as Lg) is required. ) Needs to be shortened. However, there is a problem in that FET characteristics such as an increase in gate resistance and a decrease in drain conductance are degraded as Lg is shortened.

Therefore, the length of the gate electrode in the gate length direction (L
g) is the length of the entire gate electrode in the gate length direction,
An FET in which Lg is shortened without increasing the gate resistance by making it extremely short, that is, by making the gate electrode have a T-shaped (Y-shaped) cross-sectional shape has been used.

As another example of a conventional FET,
An FET in which the FET has a HEMT structure and a recess is formed in two steps and a method of manufacturing the same are disclosed in Japanese Patent Application Laid-Open No. Sho 59-218778.
No. in the official gazette. FIGS. 7 (a) to 7 (g) show this
FIG. 9 is a diagram showing a manufacturing process of a conventional FET described in Japanese Patent Application Laid-Open No. 9-218778, wherein 31 is a semi-insulating GaAs substrate, 32
Is an undoped GaAs layer, 33 is an n-AlGaAs layer,
34 indicates that the Al composition is n-AlG from the lower layer to the upper layer.
An n-Al _x Ga _a1-x As layer formed so as to decrease sequentially from the same as the aAs layer 33, 35 is an n-GaAs layer,
6 is an n ⁺ -GaAs layer, 37 is an undoped GaAs layer 3
A two-dimensional electron gas formed near the heterojunction interface between the n-AlGaAs layer 2 and the n-AlGaAs layer 33, 38 is a source electrode, 39 is a drain electrode, 40 is a gate pattern mask formed of resist, and 41 is a gate electrode. I have.

Hereinafter, a method of manufacturing the conventional FET will be described. First, on a semi-insulating GaAs substrate 31, an undoped GaAs layer 32, an n-AlGaAs layer 33, an n-
Al _x Ga _a1-x As layer 34, n-GaAs layer 35, n ⁺
-GaAs layers 36 are sequentially formed (FIG. 7A), and the n ⁺
-A source electrode 38 and a drain electrode 39 are formed on the upper surface of the GaAs layer 36 (FIG. 7B).

Next, a resist is applied to the entire surface of the n ⁺ -GaAs layer 36, the source electrode 38, and the drain electrode 39, and is patterned to form a gate electrode.
A gate pattern mask 40 having an opening gradually expanding from the surface toward the substrate is formed (FIG. 7C), and the GaAs layer 26 is removed by wet etching using this mask to form a recess (FIG. 7C). FIG. 7 (d)). This etching is performed while measuring the source / drain current, and the etching is stopped at a substantially intermediate position of the n-GaAs layer 25. Thereafter, the gate pattern mask 40 is further formed.
A second etching is performed by reactive ion etching to remove the n-GaAs layer 25 and
The etching is stopped at the GaAs layer 24 (FIG. 7E).

Thereafter, a gate metal is applied from above the gate pattern mask 40 (FIG. 7 (f)), and the gate pattern mask 40 is peeled off to lift off the extra gate metal 42 to remove the gate electrode 41. Form, F
The ET is completed (FIG. 7 (g)). Thus, the FE having two recesses using the same gate pattern mask 40 is used.
T was manufactured.

[0009]

As described above, in the conventional FET shown in FIG. 6, when the gate length (Lg) is reduced in order to increase the frequency of the FET and to improve the low-voltage operation, Along with this, FE such as an increase in gate resistance, an increase in drain conductance, a decrease in breakdown voltage, etc.
There is a problem that the T characteristic deteriorates.

In order to solve this problem, by making the cross-sectional shape of the gate electrode T-shaped, the effective gate length Lg can be shortened while suppressing an increase in gate resistance. In addition, as the effective gate length Lg is shortened, the width of the depletion layer formed below the gate electrode in the gate length direction is reduced, thereby increasing the drain conductance or decreasing the breakdown voltage. There was a problem that occurs.

The conventional FET shown in FIG. 7 in which the recesses are formed in two stages has a structure in which Lg is formed sufficiently short in order to increase the frequency of the FET and improve the low-voltage operation. Therefore, it is not possible to sufficiently increase the frequency and improve the low-voltage operation. Even if an FET having a short Lg is manufactured by the conventional method for manufacturing an FET shown in FIG. Since Lg cannot be formed sufficiently short, and the length L of the entire gate electrode in the gate length direction also decreases with the reduction of Lg.
As in the conventional FET shown in FIG.
There is a problem that the drain conductance increases and the breakdown voltage decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has been made to increase the frequency and improve the low-voltage operation without deteriorating FET characteristics such as an increase in gate resistance, an increase in drain conductance and a decrease in breakdown voltage. It is an object of the present invention to provide a field effect transistor capable of achieving the above and a method for manufacturing the same.

[0013]

According to a first aspect of the present invention, there is provided a field effect transistor including a first semiconductor layer formed on a semiconductor substrate and serving as a channel region, and an upper surface of the first semiconductor layer. A second semiconductor layer formed as a channel region together with the first semiconductor layer, a bottom surface of a recess formed on a top surface of the second semiconductor layer and partially etching the second semiconductor layer; A distance between the upper surface of the second semiconductor layer and the upper surface of the second semiconductor layer is about 0.03 to 0.1 μm, and the upper surface of the second semiconductor layer reaches the upper surface of the second semiconductor layer substantially at the center in the channel length direction in the recess; A third semiconductor layer having an opening having a length of 0.2 μm or less; and a third semiconductor layer embedded in the opening, in contact with the second semiconductor layer, and in the vicinity of the opening, including on the opening. A gate formed so as to be in contact with the upper surface of the third semiconductor layer. And a gate electrode.

Further, a field effect transistor according to the present invention (claim 2) is the above field effect transistor, wherein the third semiconductor layer is made of a material which can be selectively etched with respect to the second semiconductor layer. It is something that was taken.

In the field effect transistor according to the present invention (claim 3), in the above field effect transistor, the third semiconductor layer is made of undoped GaAs or n ⁻ -GaAs.

In the field-effect transistor according to the present invention (claim 4), in the field-effect transistor, the gate electrode is in contact with the upper surface of the third semiconductor layer on the source side of the opening. The length in the gate length direction is shorter than the length in the gate length direction in contact with the upper surface of the third semiconductor layer on the drain side of the opening.

Further, according to the field effect transistor of the present invention (claim 5), in the above field effect transistor, the first semiconductor layer is made of undoped InGaAs.
And the second semiconductor layer is formed of n-AlG
aAs.

Further, according to a method of manufacturing a field effect transistor according to the present invention (claim 6), the first
Growing a second semiconductor layer with a thickness of 50 to 200 angstroms on the upper surface of the first semiconductor layer; and forming a second semiconductor layer on the upper surface of the second semiconductor layer.
Growing a third semiconductor layer made of a material that can be selectively etched with respect to the first semiconductor layer, and after forming source and drain electrodes, etching the third semiconductor layer in a predetermined region between the source and drain electrodes The distance between the bottom surface and the top surface of the second semiconductor layer is about 0.03 to 0.1.
Forming a recess having a thickness of 0 μm, and forming at least a surface of the third semiconductor layer on the bottom surface of the recess among the source electrode, the drain electrode, and the surface of the third semiconductor layer by a CVD method. 500-2000 thickness
Growing an Angstrom CVD film;
A first resist pattern having an opening having a predetermined length in the gate length direction is formed on the entire surface including the VD film substantially at the center of the source and the drain in the recess, and the CVD film in the opening is formed. Removing the first resist pattern, forming a second resist pattern for determining the size of the main body of the gate electrode after removing the first resist pattern, and using the CVD film as a mask, And the second
Forming an opening reaching the second semiconductor layer by etching the third semiconductor layer using the semiconductor layer as an etching stopper layer, and etching away the CVD film using the second resist pattern as a mask Forming a gate metal on the exposed surfaces of the second and third semiconductor layers by a vapor deposition lift-off method.

In the method for manufacturing a field effect transistor according to the present invention (claim 7), the first and third semiconductor layers are made of n-GaAs in the method for manufacturing a field effect transistor. The second semiconductor layer is made of AlGaAs.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. FIG. 1 is a structural sectional view of an FET according to a first embodiment of the present invention. In the drawing, 1 is a semi-insulating substrate, 2 is a buffer layer, and 3 is an n-
An GaAs active layer 4, an AlGaAs layer 4 serving as a channel region together with the n-GaAs active layer 3, an n-GaAs layer 5 in which a recess is formed, 6 a source electrode, 7 a drain electrode, and 8 a gate electrode. The gate electrode 8 is buried below the gate electrode main body 8b and substantially below the center of the lower surface of the gate electrode main body 8b so as to fill the opening formed in the n-GaAs layer 5. And a section 8a. In the figure, reference numerals 21 to 23 schematically show depletion layers formed during operation.

In the FET according to the first embodiment, n-G as first and second semiconductor layers serving as channel layers, which are sequentially formed on a semi-insulating substrate 1 via a buffer layer 2, are provided.
aGaAs active layer 3 and AlGaAs layer 4 and AlGaAs
The bottom of the recess formed by etching a part between the source and the drain formed on the upper surface of the s layer 4 and the AlGa
The distance from the upper surface of the As layer 4 is about 0.03 to 0.1 μm, and the length Lg in the gate length direction reaching the upper surface of the AlGaAs layer 4 almost at the center between the source and the drain in the recess. An n-GaAs layer 5 which is a third semiconductor layer having an opening of 0.1 to 0.2 μm, a lower portion of the n-GaAs layer 5 is embedded in the opening and is in contact with the AlGaAs layer 4, and a main body portion 8 b is formed of the opening. A gate electrode 8 formed on the n-GaAs layer 5 at the bottom of the recess near the opening, including on the hole;
It is provided with.

Hereinafter, a method of manufacturing the FET according to the first embodiment will be described. 5A to 5F are process cross-sectional views for explaining the method of manufacturing the FET according to the first embodiment. In the figure, 13 is a CVD film formed by the CVD method, 14 is a first resist pattern, 15 is a second resist pattern, and the same reference numerals as those in FIG. 1 indicate the same or corresponding parts.

First, undoped Ga is placed on a semi-insulating substrate 1.
The buffer layer 2 made of As or the like is formed. Then, n-
After growing the GaAs active layer 3 to a predetermined thickness,
An n-GaAs active layer including a layer serving as a channel region is formed by growing a GaAs layer 4 to a thickness of 50 to 200 angstroms and then growing an n-GaAs layer 5 which can be selectively etched with respect to the AlGaAs layer 4. 3, AlGa
The As layer 4 and the n-GaAs layer 5 are 3,000 to 5,000.
It is grown to a thickness of Å (FIG. 5 (a)).

Next, after the source and drain electrodes 6 and 7 are formed, n-Ga in a predetermined region between the source and drain electrodes is formed.
The As layer 5 is wet-etched to form a recess bottom and Al
The distance H from the upper surface of the GaAs layer 4 is about 0.03 to 0.10 μm.
m, and then a SiN,
A CVD film 13 of SiO, SiON or the like is
500 on the surface of the drain electrode 7 and the n-GaAs layer 5
Grown to a thickness of ~ 2000 Angstroms (Fig. 5
(b)).

A gate electrode lower buried portion 8a is formed at a predetermined position in the center of the recess, and an opening having a length Lg of about 0.1 to 0.2 μm in the gate length direction is provided. 1 is formed, and the CVD film 13 in the opening is removed by anisotropic etching (FIG. 5).
(c)).

After removing the first resist pattern 14, a second resist pattern 15 for determining the length L of the gate electrode body in the gate length direction is formed (FIG. 5).
(d)).

Thereafter, n-
Wet etching of the GaAs layer 5 is performed. At this time,
By using an etching solution having a low solubility for the AlGaAs layer 4, the AlGaAs layer 4 is used as an etching stopper layer, and only the n-GaAs layer 5 is selectively removed to form an opening reaching the AlGaAs layer 4. Is formed (FIG. 5E).

Finally, the CVD film 13 is removed by etching using the second resist pattern 15 as a mask, and the exposed n-GaAs layer 5 and the exposed AlGaAs are removed.
By forming the gate electrode 8 on the surface of the layer 4 by the vapor deposition lift-off method, the FET according to the first embodiment is obtained (FIG. 5F).

The operation of the FET according to the first embodiment will be described below. In general, the length Lg of the lower surface of the gate electrode in contact with the channel layer in the gate length direction is very short with respect to the length L of the entire gate electrode in the gate length direction, thereby suppressing an increase in gate resistance. Although the effective gate length can be shortened, as the effective gate length is shortened, the width of the depletion layer formed below the gate electrode in the gate length direction also becomes narrower. There is a problem that the current cannot be stopped down, that is, the drain conductance deteriorates.

The FET according to the first embodiment of the present invention
The length Lg in the gate length direction of the lower surface of the gate electrode lower buried portion 8a in contact with the AlGaAs layer 4 is 0.1 to 0.2 μm, and the upper surface of the gate electrode is adjacent to the gate electrode lower buried portion 8a. N-GaAs with main body 8b formed
The thickness H of the layer 5 is formed to be 0.03 to 0.1 μm, so that a depletion layer formed during operation is:
FIG. 1 shows the depletion layer 21.

Here, n-GaAs near the gate electrode 8 is used.
The reason why the thickness of the layer 5, that is, the distance H between the recess bottom surface and the upper surface of the AlGaAs layer 4 is H = about 0.03 to 0.10 μm is as follows. That is, this distance H is 0.1
When the thickness is set to μm or more, the depletion layer formed below the gate electrode 8 during operation becomes as shown by the depletion layer 22 in FIG. 1, and this is due to the narrow width of the depletion layer 22 in the gate length direction. This leads to a deterioration in drain conductance and a decrease in breakdown voltage.

When the distance H is set to 0.03 μm or less, the AlGaAs layer 4 of the gate electrode lower buried portion 8a is formed.
Not only the bottom surface in contact with the gate electrode body 8b
The lower surface of the right and left portions in contact with the upper surface of the n-GaAs layer 5 also serves as an effective gate length, so that the depletion layer formed below the gate electrode 8 during operation is the depletion layer 2 of FIG.
As a result, the effect of reducing the rising voltage, which is the object of the present invention, cannot be obtained.

That is, in the FET according to the first embodiment of the present invention, the length Lg in the gate length direction of the lower surface of the gate electrode lower buried portion 8a in contact with the AlGaAs layer 4 is 0.1-0.
2 μm, which is adjacent to the gate electrode lower buried portion 8 a and has a gate electrode main body portion 8 b formed on the upper surface thereof.
-Since the thickness H of the GaAs layer 5 is formed to be 0.03 to 0.1 [mu] m, even if the effective gate length Lg is reduced to 0.2 or less, it is formed below the gate electrode 8 during operation. The depletion layer becomes a depletion layer 21 having a sufficiently wide width in the gate length direction as shown in the depletion layer 21 of FIG. 1, and while increasing the frequency and improving the low-voltage operation, the drain conductance deteriorates and the breakdown voltage decreases. The decrease can be suppressed.

In the first embodiment, the length Lg of the bottom surface of the gate electrode lower buried portion 8a in the gate length direction is as follows.
In order to achieve the high frequency operation of the FET and the improvement of the low voltage operation, which are the objects of the present invention, and in view of the accuracy of the manufacturing technology, etc., the range of Lg is set to 0.1 to 0.2 μm. The length Lg is not limited to 0.1 to 0.2 μm, and the same effect can be obtained if it is about 0.2 μm, and can be 0.1 μm or less if the precision of the manufacturing technology is improved.

Further, n-GaAs as the third semiconductor layer
The layer 5 is made of AlGaAs, which is a second semiconductor layer in the layer.
It may have a three-layer structure in which a layer having a predetermined thickness and functioning as an etching stopper layer for the third semiconductor layer is inserted at a predetermined position where the distance from the s layer 4 is about 0.03 to 0.10 μm. In this case, the bottom surface of the recess can be formed with higher accuracy.

As described above, the FE according to the first embodiment
In T, the n-GaAs active layer 3 and the AlGaAs layer 4 which are the first and second semiconductor layers to be channel regions sequentially formed on the upper surface of the buffer layer 2 on the semi-insulating substrate 1
And a bottom of the recess formed by etching a part of the top of the AlGaAs layer 4 and the AlGaAs.
An opening having a distance H from the surface of the layer 4 of about 0.03 to 0.10 μm and a length L in the gate length direction of 0.2 μm or less reaching the upper surface of the AlGaAs layer 4 substantially at the center of the recess. An n-GaAs layer 5 as a third semiconductor layer having
The lower portion (8a) fills the opening to form AlGaAs.
Since the gate electrode 8 is in contact with the layer 4 and the main body portion 8b includes the opening, and the gate electrode 8 is formed on the n-GaAs layer 5 on the bottom of the recess near the opening. Is determined by the length L of the lower surface of the gate electrode lower buried portion 8a in the gate length direction, thereby reducing the rising voltage,
The frequency of the FET can be increased and the low-voltage operation can be improved. In addition, the lower surface mainly on the drain side of the left and right portions in contact with the n-GaAs layer 5 on the lower surface of the recess on the lower surface of the gate electrode main body 8b has an electric field. To alleviate the concentration, the effect of suppressing the adverse effects such as the deterioration of the drain conductance and the reduction of the withstand voltage, which are problems with the reduction of the gate length, can be obtained.

According to the method of manufacturing the FET according to the first embodiment, the buffer layer 2, the n-GaAs active layer 3, and the AlGaAs layer 4 are sequentially grown on the semi-insulating substrate 1. The AlGa layer is formed on the AlGaAs layer 4.
After forming an n-GaAs layer 5 that can be selectively etched with respect to the As layer 4 and forming a source electrode 6 and a drain electrode 7, the bottom surface and the AlGaAs layer 4 are formed on the n-GaAs layer 5.
A recess having a distance from the surface of about 0.03 to 0.10 μm is formed, and the source electrode 6, the drain electrode 7, and the n-
A CVD film 13 is grown on the surface of the GaAs layer 5, and a first resist pattern 14 having an opening having a predetermined length in the gate length direction is formed in the center of the recess. 13 is removed by anisotropic etching, the first resist pattern 14 is removed, and a second resist pattern 15 for determining the size of the gate electrode is formed.
Using the film 13 as a mask and the AlGaAs layer 4 as an etching stopper layer, the n-GaAs layer 5 is etched to form an opening reaching the AlGaAs layer 4, and the CVD film 13 is formed using the second resist pattern 15 as a mask. Etching is removed to expose the exposed n-GaAs layer 5 and the exposed A-layer.
Since the gate metal 8 was formed on the surface of the lGaAs layer 4 by the vapor deposition lift-off method, the second semiconductor layer AlGa was formed.
N-GaAs as a third semiconductor layer up to the surface of the As layer 4
When the layer 5 is etched, by using an etchant having low solubility in AlGaAs, only the n-GaAs layer 5 as the third semiconductor layer is selectively removed, and the AlGaAs layer 4 is precisely removed. This embodiment can stop the etching on the surface, thereby reducing the variation in the recess shape, improving the frequency of the FET and improving the low voltage operation, and suppressing the adverse effects such as the deterioration of the drain conductance. There is an effect that one FET can be manufactured with good controllability.

Embodiment 2 FIG. FIG. 2 is a structural sectional view of an FET according to a second embodiment of the present invention. In the figure, reference numeral 9 denotes an undoped GaAs layer, and the same reference numerals as those in FIG. 1 denote the same or corresponding parts. The FET according to the second embodiment is different from the FET according to the first embodiment in that the third semiconductor layer (n
The GaAs layer 5) is formed of undoped GaAs.

The method for fabricating an FET according to the second embodiment is different from the method for fabricating an FET according to the first embodiment in that, in the step of growing the third semiconductor layer, the semiconductor material to be grown is changed to n-GaAs. Undoped GaAs, and the other steps are the same as in the first embodiment.

The operation of the FET according to the second embodiment will be described below. In the FET thus formed according to the second embodiment, since the third semiconductor layer in contact with the lower surfaces of the left and right portions of the gate electrode main body 8b is an undoped GaAs layer with few carriers, the gate electrode When a gate voltage is applied, the depletion layer greatly spreads over the undoped GaAs layer 9 below the gate electrode 8 and into the n-GaAs active layer 3 serving as a channel region.
Therefore, the depletion layer 2 in the FET according to the first embodiment described above.
1 (FIG. 1), the area (volume) of the depletion layer 24 is increased, and the withstand voltage of the FET can be increased.

As described above, the FE according to the second embodiment
In T, since the third semiconductor layer is formed of undoped GaAs, the size of the depletion layer 24 that spreads to the channel region during operation can be increased. In addition to the same effect as the FET according to the first embodiment, And more FE
This has the effect of increasing the breakdown voltage of T.

In the second embodiment, the third semiconductor layer is formed of undoped GaAs, but this material is replaced by undoped GaAs and n ⁻
Almost the same effect can be obtained by using -GaAs.

Embodiment 3 FIG. FIG. 3 is a structural sectional view of an FET according to a third embodiment of the present invention. In the figure, reference numeral 10 denotes a gate electrode, and the gate electrode 10 in the third embodiment is a gate electrode lower buried portion 10a formed so as to fill an opening formed in the n-GaAs layer 5.
And a gate electrode main body 10b disposed in contact with the upper surface of the third semiconductor layer in the vicinity of the opening including the opening, and the gate electrode main body 10b is arranged with respect to the gate electrode lower buried portion 10a. And is formed offset to the drain side. The same reference numerals as those in FIG. 1 denote the same or corresponding parts.

The gate electrode 10 of the FET according to the third embodiment is the same as that of the FET according to the first embodiment except that the volume of the gate electrode is kept as it is, and
The length (LS) in the gate length direction in contact with the upper surface of the n-GaAs layer 5 on the source side of the gate electrode a is lower than the buried portion 1 of the gate electrode.
0a, it is shorter than the length (LD) in the gate length direction in contact with the upper surface of the n-GaAs layer 5 on the drain side, and LD> LS.

In the method of manufacturing an FET according to the third embodiment, in the step of forming the second resist pattern 15 in the method of manufacturing the FET described in the first embodiment, the second resist pattern is used as the second resist pattern. The shape is such that the center of the opening that determines the size of the gate electrode main body 10b is offset to the drain side with respect to the center of the portion where the gate electrode lower buried portion 10a is formed. Is the same as in the first embodiment.

The operation of the FET according to the third embodiment will be described below. In the third embodiment, the gate electrode 1
0 is the length of the portion in contact with the upper surface of the n-GaAs layer 5 on the source side of the gate electrode body 10b, as compared with the FET according to the first embodiment, because LS is shorter than LD while the volume remains unchanged. (LS), the capacitance (Cgs) between the gate and the source can be reduced without increasing the gate resistance, and the concentration of the electric field is mainly reduced. Since the length (LD) of the portion in contact with the upper surface of the n-GaAs layer 5 on the drain side is longer than in the first embodiment, the depletion layer is shown as a depletion layer 25 in the drawing. As described above, compared to the depletion layer 21 of the first embodiment shown in FIG. 1, the width in the gate length direction is formed wider, and a higher breakdown voltage can be achieved.

In such an FET according to the third embodiment, the gate electrode is formed in the gate length direction in contact with the upper surface of the n-GaAs layer 5 on the source side from the gate electrode lower buried portion 10a while maintaining the volume. Since the length (LS) is formed to be shorter than the length (LD) in the gate length direction in contact with the upper surface of the n-GaAs layer 5 on the drain side from the gate electrode lower buried portion 10a, the first embodiment is described. FE by
In addition to the same effect as T, the gate-source capacitance (Cg
s) can be reduced, which has the effect of expanding the usable frequency range, ie, improving the high frequency characteristics such as increasing the cutoff frequency.

Embodiment 4 FIG. FIG. 4 is a structural sectional view of an FET according to a fourth embodiment of the present invention. In the figure, 11 is an undoped InGaAs layer, 12 is n-Al
The same reference numerals as those in FIG. 1 denote the same or corresponding parts. The FET according to the fourth embodiment includes:
In the structure of the FET according to the first embodiment, the first semiconductor layer is formed of an undoped I having a thickness of 0.01 to 0.02 μm.
In the nGaAs layer 11, the second semiconductor layer is formed of n-AlGaAs.
The s layer 12 is formed.

In the method of manufacturing an FET according to the fourth embodiment, the step of growing the first semiconductor layer in the method of manufacturing the FET described in the first embodiment is performed by using undoped InGaAs as the material of the first semiconductor layer. A step of growing an undoped InGaAs layer 11 having a desired thickness by using
The step of growing the second semiconductor layer is performed by using n-AlGaAs as the material of the second semiconductor layer, and forming n-Al of a desired thickness.
This is a step of growing the GaAs layer 12, and other steps are the same as in the first embodiment.

The operation of the FET according to the fourth embodiment will be described below. In the fourth embodiment, the n-AlGaAs layer 1 having a large band gap and serving as an electron supply layer is used.
2 and the undoped InGaAs layer 11 having a small band gap and functioning as an electron transit layer can form a HEMT structure, thereby improving electron mobility and increasing the amount of current flowing. Further, the n-AlGaAs layer 12 as the second semiconductor layer can be selectively etched with respect to the n-GaAs layer 5 as the third semiconductor layer.
When forming an opening in the s layer 5, the n-AlGaAs layer 12 can be used as an etching stopper layer.

As described above, the FE according to the fourth embodiment
At T, the same effects as those of the FET according to the first embodiment are obtained, and the n-AlGaAs layer 12 having a large band gap acting as an electron supply layer and the undoped InG having a small band gap acting as an electron transit layer are provided.
Since the HEMT structure is constituted by the aAs layer 11, the amount of current flowing by the HEMT structure can be increased, and the effect of improving the mutual conductance can be obtained.

[0052]

As described above, according to the field effect transistor of the present invention (claim 1), the first semiconductor layer serving as the channel region formed on the semiconductor substrate and the first semiconductor layer A second semiconductor layer formed on the upper surface of the layer and serving as a channel region together with the first semiconductor layer;
The distance between the bottom surface of the recess formed by partially etching the upper surface of the semiconductor layer and the upper surface of the second semiconductor layer is about 0.03 to 0.1 μm; The length in the gate length direction, which reaches the upper surface of the second semiconductor layer substantially at the center in the channel length direction in the recess, is 0.2 μm.
A third semiconductor layer having the following opening, and an upper surface of the third semiconductor layer near the opening including the opening and being in contact with the second semiconductor layer by filling the opening. And a gate electrode formed so as to be in contact with the gate electrode, so that the rising voltage can be reduced by an effective shortening of the gate length, thereby increasing the frequency of the FET and improving the low voltage operation. Since the left and right portions of the gate electrode body in contact with the upper surface of the third semiconductor layer relieve the concentration of the electric field, the adverse effects such as the deterioration of drain conductance and the reduction of withstand voltage, which are problems with the reduction of the gate length, are suppressed. The effect that can be obtained is obtained.

According to the field effect transistor of the present invention (claim 2), in the field effect transistor, the third semiconductor layer can be selectively etched with respect to the second semiconductor layer. , While preventing the deterioration of drain conductance,
F that can increase the frequency and improve the low-voltage operation
There is an effect that ET can be obtained with good controllability.

According to the field effect transistor of the present invention (claim 3), in the field effect transistor, the third semiconductor layer is made of undoped GaAs.
Since it is made of s or n ⁻ -GaAs, there is an effect that the withstand voltage can be increased in addition to the same effect as the above FET.

According to the field effect transistor of the present invention (claim 4), in the field effect transistor, the gate electrode is in contact with the upper surface of the third semiconductor layer on the source side of the opening. Since the length in the gate length direction is shorter than the length in the gate length direction in contact with the upper surface of the third semiconductor layer on the drain side of the opening, the same effect as in the above FET is obtained. In addition, there is an effect that the high frequency characteristics can be improved.

According to the field effect transistor of the present invention (claim 5), in the field effect transistor, the first semiconductor layer is formed of undoped InG.
aAs, and the second semiconductor layer is formed of n-
Since it is made of AlGaAs, a HEMT structure can be formed, and this HEMT structure has the effect of increasing the electron mobility and improving the transconductance.

According to a method of manufacturing a field-effect transistor according to the present invention (claim 6), the method of manufacturing a field-effect transistor described above includes a step of growing a first semiconductor layer on a semiconductor substrate. Growing a second semiconductor layer with a thickness of 50 to 200 Å on the first semiconductor layer, and selectively etching the second semiconductor layer with respect to the second semiconductor layer on the second semiconductor layer. Growing a third semiconductor layer made of a material; forming source and drain electrodes; etching the third semiconductor layer in a predetermined region between the source and drain electrodes; The distance from the upper surface of the semiconductor layer is about 0.03 to 0.0.
A step of forming a recess having a thickness of 10 μm, and at least a surface of the third semiconductor layer at a bottom surface of the recess among the source electrode, the drain electrode, and the surface of the third semiconductor layer by a CVD method. 500-2000 thickness
Growing an Angstrom CVD film;
A first resist pattern having an opening having a predetermined length in the gate length direction is formed on the entire surface including the VD film substantially at the center of the source and the drain in the recess, and the CVD film in the opening is formed. Removing the first resist pattern, forming a second resist pattern for determining the size of the main body of the gate electrode after removing the first resist pattern, and using the CVD film as a mask, And the second
Forming an opening reaching the second semiconductor layer by etching the third semiconductor layer using the semiconductor layer as an etching stopper layer, and etching away the CVD film using the second resist pattern as a mask And forming a gate metal on the exposed surfaces of the second and third semiconductor layers by a vapor deposition lift-off method, thereby preventing deterioration of drain conductance, improving the frequency and improving the low-voltage operation. Thus, there is an effect that the FET described in each of the above claims can be manufactured with good controllability.

According to a method of manufacturing a field effect transistor according to the present invention (claim 7), in the method of manufacturing a field effect transistor, the first and third semiconductor layers are made of n-GaAs. And the second
Since the semiconductor layer is made of AlGaAs, it is possible to prevent the deterioration of the drain conductance, improve the frequency, and improve the low voltage operation.
Can be manufactured with good controllability.

[Brief description of the drawings]

FIG. 1 is a structural sectional view of an FET according to a first embodiment of the present invention.

FIG. 2 is a structural sectional view of an FET according to a second embodiment of the present invention.

FIG. 3 is a structural sectional view of an FET according to a third embodiment of the present invention.

FIG. 4 is a structural sectional view of an FET according to a fourth embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method of manufacturing the FET in the first embodiment of the present invention.

FIG. 6 is a structural sectional view of a conventional FET.

FIG. 7 is a process sectional view showing a conventional method for manufacturing an FET.

[Explanation of symbols]

1 semi-insulating substrate, 2 buffer layer, 3 n-GaAs
Active layer, 4 AlGaAs layer, 5 n-GaAs layer, 6
Source electrode, 7 Drain electrode, 8 Gate electrode, 8
a Gate electrode lower surface column, 8b Gate electrode main body, 9
Undoped GaAs layer, 10 gate electrode, 10a
Gate electrode lower pillar, 10b Gate electrode body, 11
Undoped InGaAs layer, 12 n-AlGaAs
Layer, 13 CVD film, 14 first resist pattern, 1
5 second resist pattern, 16 gate electrode, 20
25 depletion layer, 31 semi-insulating GaAs substrate, 32 undoped GaAs layer, 33 n-AlGaAs layer, 34
n-Al _x Ga _a1-x As layer, 35 n-GaAs layer,
36 n ⁺ -GaAs layer, 37 two-dimensional electron gas, 38
Source electrode, 39 drain electrode, 40 gate pattern mask, 41 gate electrode, 42 gate metal.

Claims (7)

[Claims] A first semiconductor layer formed on a semiconductor substrate and serving as a channel region; and a second semiconductor layer formed on an upper surface of the first semiconductor layer and serving as a channel region together with the first semiconductor layer. A distance between a bottom surface of a recess formed by etching a part of the upper surface of the second semiconductor layer and an upper surface of the second semiconductor layer is about 0.03 to 0; .1 .mu.m and reaches the upper surface of the second semiconductor layer substantially at the center in the channel length direction within the recess, and has a length in the gate length direction of 0.1 .mu.m.
A third semiconductor layer having an opening of not more than 2 μm, and a third semiconductor layer embedded in the opening and in contact with the second semiconductor layer and in the vicinity of the opening, including over the opening. A field effect transistor comprising: a gate electrode formed to be in contact with the upper surface. 2. The field effect transistor according to claim 1, wherein said third semiconductor layer is made of a material which can be selectively etched with respect to said second semiconductor layer. Transistor. 3. The field effect transistor according to claim 1, wherein the third semiconductor layer is made of undoped GaAs or n.
^- field effect transistor characterized by comprising from -GaAs. 4. The field effect transistor according to claim 1, wherein said gate electrode is connected to said third electrode on a source side of said opening.
A field-effect transistor wherein the length in the gate length direction in contact with the upper surface of the semiconductor layer is shorter than the length in the gate length direction in contact with the upper surface of the third semiconductor layer on the drain side of the opening. . 5. The field effect transistor according to claim 1, wherein said first semiconductor layer is made of undoped InGaAs, and said second semiconductor layer is made of n-AlGaAs. Field-effect transistor. 6. A step of growing a first semiconductor layer on a semiconductor substrate, and forming a second semiconductor layer on the upper surface of the first semiconductor layer by 50 to 200.
A step of growing to a thickness of Å, a step of growing a third semiconductor layer made of a material that can be selectively etched with respect to the second semiconductor layer on the upper surface of the second semiconductor layer, After the formation, the third semiconductor layer in a predetermined region between the source and drain electrodes is etched to form a recess having a distance between the bottom surface and the top surface of the second semiconductor layer of about 0.03 to 0.10 μm. Forming a thickness of 50% by CVD on at least the surface of the third semiconductor layer at the bottom surface of the recess among the surfaces of the source electrode, the drain electrode, and the third semiconductor layer.
A step of growing a CVD film of 0 to 2000 angstroms;
Forming a first resist pattern having an opening having a predetermined length in the gate length direction substantially at the center of the drain, and removing the CVD film in the opening by anisotropic etching; Forming a second resist pattern that determines the size of the main body of the gate electrode after removing the resist pattern; and using the CVD film as a mask and using the second semiconductor layer as an etching stopper layer. Etching a third semiconductor layer to form an opening reaching the second semiconductor layer; and etching and removing the CVD film using the second resist pattern as a mask to expose the second, and the second exposed portions. Forming a gate metal on the surface of the semiconductor layer by a vapor deposition lift-off method. 7. The method for manufacturing a field effect transistor according to claim 6, wherein the first and third semiconductor layers are made of n-GaAs, and the second semiconductor layer is made of AlGaAs. Manufacturing method of a field-effect transistor.