JP3446664B2 - Tunnel transistor and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor utilizing tunneling phenomenon, which can be highly integrated, operate at high speed, and have multiple functions, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A tunnel transistor has been proposed as a transistor that can be highly integrated and have multiple functions by utilizing a tunnel phenomenon at a p ⁺ -n ⁺ junction on a semiconductor surface. This device and its manufacturing method are shown in, for example, the technology (tunnel transistor and its manufacturing method) disclosed in Japanese Patent Publication No. 2778447, and this technology will be described below.

A schematic view of the structure of this conventional tunnel transistor is shown in FIG. This transistor includes a degenerate first semiconductor 2 having one conductivity type, a separation layer 3 made of a semiconductor having a low impurity concentration, and a first semiconductor 2 on a substrate 1.
And a degenerate second semiconductor 4 having a conductivity type opposite to that of the first semiconductor 2 to the second semiconductor 4.
A degenerate fourth semiconductor 6 having the same conductivity type as the first semiconductor 2 on the exposed surface of the first semiconductor 2, an insulating layer 7 made of a material having a wider band gap than the fourth semiconductor 6, and a gate on the insulating layer 7. It has an electrode 8 and a source electrode 9 and a drain electrode 10 which form ohmic junctions with the first semiconductor 2 and the second semiconductor 4, respectively.

Operation of this conventional tunnel transistor
To the substrate 1, semi-insulating GaAs, and the first semiconductor 2 to n.⁺
-GaAs, and the isolation layer 3 is formed of AMP and the second half
P on conductor 4⁺-GaAs, n in the fourth semiconductor 6⁺-GaA
s, Insulating layer 7 is formed of AND-Al _0.3Ga_0.7As, Gate
Electrode 8 is Al, source electrode 9 is AuGe / Au, drain
A case where AuZn / Au is used for the electrode 10 will be described.
To do.

The source electrode 9 is set to the ground potential, and a voltage is applied between the source electrode 9 and the drain electrode 10. A tunnel diode is provided where the fourth semiconductor 6 that will be the channel layer and the second semiconductor 4 that will be the drain region are in contact with each other.
A junction similar to the (Esaki diode) is formed, and as a result, a current (tunnel current) due to the tunnel effect flows between the source and the drain. In particular, when a positive voltage is applied to the drain electrode 10, the Esaki diode becomes forward biased, so that a differential negative resistance characteristic appears in its current-voltage characteristic. Since the magnitude of the tunnel current depends on the concentration of electrons induced in the channel, this differential negative resistance characteristic is controlled by the voltage applied to the gate electrode 8, and the operation of a transistor having a function can be obtained. To be

Next, a method of manufacturing this conventional tunnel transistor will be described. First, semi-insulating GaAs
On the substrate 1, n ⁺ with a thickness of 400 nm to be the first semiconductor is formed.
-GaAs layer 2 (contains 1x10 ¹⁹ m ^-3 of Si as a dopant) and has a thickness of 200 nm to serve as a separation layer.
Undoped GaAs layer 3, thickness to be the second semiconductor 1
00 nm p ⁺ -GaAs layer 4 (concentration 1 × 10 ²⁰ cm ⁻³ B
e as a dopant. ) Are sequentially formed by a molecular beam epitaxy method.

Next, parts other than the drain region are removed by etching to expose the isolation layer 3 and the first semiconductor.
Then, on the exposed surface, the n ⁺ -GaAs layer 6 having a thickness of 20 nm, which is the fourth semiconductor, is again formed by the molecular beam epitaxy method.
(Si containing a concentration of 1 × 10 ¹⁹ cm ⁻³ as a dopant) and Al _0.3 G having a thickness of 40 nm to be an insulating layer.
a _0.7 As layer 7 is grown.

Further, after Al to be a gate electrode is vapor-deposited thereon, Al / Al _0.3 Ga _0.7 As layer / n ⁺ -GaA is deposited.
The s layer is etched into the shape of the gate electrode 8. Finally,
AuGe / Au is formed as a source electrode on the first semiconductor exposed by etching, and AuZn / Au is formed as a drain electrode on the second semiconductor.

[0009]

In the conventional tunnel transistor, the band-to-band tunnel junction is formed at the junction between the second semiconductor and the fourth semiconductor. However, the second
After forming the first semiconductor, the first semiconductor is formed during the formation of the fourth semiconductor.
Therefore, there is an etching step for exposing the surface of the second semiconductor, so that impurities generated in the etching step exist at the bonding interface between the second semiconductor and the fourth semiconductor. The residual impurities increase the leak current at the junction interface and deteriorate the device characteristics.

The present invention has been made in view of the problems of the above-described conventional techniques, and reduces the amount of residual impurities at the junction surface where the band-to-band tunnel junction is formed, thereby improving the device characteristics. An object is to provide an excellent tunnel transistor.

[0011]

In order to achieve the above-mentioned object, a tunnel transistor according to the present invention has a "separation layer made of a first semiconductor having one conductivity type and a semiconductor having a low impurity concentration on a substrate." A stacked structure including a degenerate second semiconductor having an opposite conductivity type to the first semiconductor and a degenerate third semiconductor having the same conductivity type as the first semiconductor; A fourth semiconductor having the same conductivity type as the first semiconductor on the exposed surface of the third semiconductor to the third semiconductor; an insulating layer made of a material having a wider bandgap than the third and fourth semiconductors; has an electrode on the insulating layer, and said first semiconductor and a second semiconductor on a pair of forming an ohmic junction each electrode, the insulating layer, the third Oyo
Beauty when the fourth semiconductor is Si is GaP, the
When the third and fourth semiconductors are InGaAs, I
nAlAs or InP, said third and fourth halves
When the conductor is GaSb or InAs, AlGaSb
It "(claim 1) is characterized by. Further, in the tunnel transistor, "the separation layer made of the semiconductor having the low impurity concentration is Andove GaAs (claim 2)", "the first to fourth semiconductors are G
aAs, Si, Ge, InP, InGaAs, GaS
It is one material selected from b and InAs ”(claim 3).

Further, the tunnel transistor according to the present invention includes a "first semiconductor having one conductivity type selectively formed on a substrate having an insulating surface at least, and a first semiconductor on the substrate". A laminated structure composed of a second semiconductor having a conductivity type opposite to that of the first semiconductor and a degenerate second semiconductor and a third semiconductor having the same conductivity type as the first semiconductor selectively formed at different positions. A fourth semiconductor that is in contact with at least a part of the surfaces of the first and third semiconductors and has the same conductivity type as the first semiconductor; and the third and third semiconductors on the fourth semiconductor. An insulating layer made of a material having a wider band gap than the semiconductor of No. 4, and an electrode on the insulating layer;
A pair of electrodes forming ohmic junctions respectively on the first semiconductor and the second semiconductor, and the insulating layer,
When the third and fourth semiconductors are Si, GaP
And the third and fourth semiconductors are InGaAs
In the case of InAlAs or InP, the third or
And when the fourth semiconductor is GaSb or InAs,
It is AlGaSb ”(claim 4).
Further, the tunnel transistor is described as follows: "The first to fourth semiconductors are GaAs, Si, Ge, InP, I.
It is one material selected from nGaAs, GaSb, and InAs ”(claim 5).

[0013]

[0014]

[0015]

[0016]

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited to the following examples, and is within the range of the features according to the present invention. Various modifications and changes are possible. Hereinafter, the present invention will be described in detail with reference to the drawings showing a preferred embodiment.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention (hereinafter referred to as "first embodiment"). In FIG. 1, the same symbols as those in FIG. 3 have the same functions as those in FIG. This tunnel transistor has a degenerate first semiconductor 2 having one conductivity type, a separation layer 3 made of a semiconductor having a low impurity concentration, and a conductivity type opposite to the first semiconductor 2 on a substrate 1. An exposed surface of the first semiconductor 2 to the third semiconductor 5 having a laminated structure composed of the degenerate second semiconductor 4 and the degenerate third semiconductor 5 having the same conductivity type as the first semiconductor. A fourth semiconductor 6 having the same conductivity type as the first semiconductor 2; an insulating layer 7 made of a material having a wider band gap than the third semiconductor 5 and the fourth semiconductor 6; A source electrode 9 having a gate electrode 8 and forming ohmic junctions with the first semiconductor 2 and the second semiconductor 4, respectively.
And a drain electrode 10.

The operation of this tunnel transistor is performed by semi-insulating GaAs on the substrate 1 and n ⁺ -GaA on the first semiconductor 2.
s, the isolation layer 3 is an and-type GaAs, the second semiconductor 4 is p ⁺ -GaAs, the third semiconductor 5 is n ⁺ -GaAs, and
N-GaAs for the semiconductor 6 and anodic Al for the insulating layer 7
A case will be described where _0.3 Ga _0.7 As, Al for the gate electrode 8, AuGe / Au for the source electrode 9, and AuZn / Au for the drain electrode 10 are used.

A source potential is applied to the source electrode 9 and a voltage is applied between the source electrode 9 and the drain electrode 10. An interband tunnel junction is formed at the junction of the second semiconductor and the third semiconductor. Since the first semiconductor and the third semiconductor are connected by the fourth semiconductor 6, a tunnel current flows between the source and drain. In particular, when a positive voltage is applied to the drain electrode 10, the tunnel junction becomes forward biased, so that a differential negative resistance characteristic appears in the current-voltage characteristic. Depending on the voltage applied to the gate electrode, the third gate
Also, the electron concentration in the fourth semiconductor can be changed, and as a result, a transistor operation for controlling the source-drain tunnel current can be obtained.

Next, a method of manufacturing the tunnel transistor of the first embodiment will be described. First, semi-insulating GaA
s On the substrate 1, an n having a thickness of 400 nm to be the first semiconductor is formed.
⁺ -GaAs layer 2 (containing Si with a concentration of 1x10 ¹⁹ cm ^-3 as a dopant) and a thickness of 200 n to serve as a separation layer.
m and-type GaAs layer 3 and a 100 nm-thickness p ⁺ -GaAs layer 4 serving as the second semiconductor (concentration 1 × 10 ²⁰ cm ⁻³
Be as a dopant. ), A 18 nm thick n ⁺ -GaAs layer 5 (concentration 1 × 1
It contains 0 ¹⁹ cm ⁻³ of Si as a dopant. ) Are sequentially formed by a molecular beam epitaxy method.

Next, parts other than the drain region are removed by etching to expose the surfaces of the first semiconductor and the third semiconductor. Then, the exposed surface is again subjected to molecular beam epitaxy by a fourth semiconductor, n-GaA having a thickness of 12 nm.
s layer 6 (the Si concentration 2x10 ¹⁸ cm ^-3 de -. containing as dopant) and A thickness 40nm as the insulating layer
l _0.3 Ga _0.7 As layer 7 is grown.

Further, after Al to be a gate electrode is vapor-deposited thereon, Al / Al _0.3 Ga _0.7 As layer / n ⁺ -GaA is deposited.
The s layer is etched into the shape of the gate electrode 8. Finally, after removing the n ⁺ -GaAs layer other than the gate region by etching, AuGe / A as a source electrode is formed on the first semiconductor.
u, AuZn / A as a drain electrode on the second semiconductor
Each u is formed and it is completed.

According to the tunnel transistor of this structure and the manufacturing method thereof, the tunnel junction can be formed without interrupting the growth, so that the residual impurity concentration at the junction interface is reduced and the surplus current is reduced by one digit or more. In this structure, the fourth semiconductor layer is not involved in the formation of the tunnel junction,
It does not have to be degenerate. Further, the second semiconductor is in contact with the fourth semiconductor layer on its side wall, but the junction area thereof is significantly smaller than the area of the tunnel junction composed of the second semiconductor and the third semiconductor. The impact can be ignored.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention (hereinafter referred to as "embodiment 2"). 2, the same symbols as those in FIG. 3 have the same functions as those in FIG. This tunnel transistor is selectively formed at a position different from the first semiconductor 2 having one conductivity type, which is selectively formed on the substrate 1 having an insulating surface, and the first semiconductor 2 on the substrate 1. In addition, a laminated structure composed of a degenerate second semiconductor 4 having a conductivity type opposite to that of the first semiconductor and a third semiconductor 5 having the same conductivity type as the first semiconductor, and a first and a third structure. A fourth semiconductor 6 in contact with at least a part of the semiconductor surface and having the same conductivity type as the first semiconductor;
An insulating layer 7 made of a material having a wider band gap than the semiconductor 5 and the fourth semiconductor 6, and a gate electrode 8 on the insulating layer,
Each of the first semiconductor 2 and the second semiconductor 4 has a source electrode 9 and a drain electrode 10 that form an ohmic junction.

The operation of this tunnel transistor is as follows. The substrate 1 is semi-insulating GaAs and the first semiconductor 2 is n ⁺ -GaA.
s, p ⁺ -GaAs on the second semiconductor 4, and the third semiconductor 5
As n ⁺ -GaAs, the fourth semiconductor 6 as n-GaAs, the insulating layer 7 as anodic Al _0.3 Ga _0.7 As, and the gate electrode 8.
A case in which Al is used, AuGe / Au is used for the source electrode 9, and AuZn / Au is used for the drain electrode 10 will be described.

The source electrode 9 is set to the ground potential, and a voltage is applied between the source electrode 9 and the drain electrode 10. Similar to the first embodiment, an interband tunnel junction is formed at the junction between the second semiconductor and the third semiconductor. First semiconductor and third
Since these semiconductors are connected by the fourth semiconductor 6, a tunnel current flows between the source and drain. In particular, when a positive voltage is applied to the drain electrode 10, the tunnel junction becomes forward biased, so that a differential negative resistance characteristic appears in the current-voltage characteristic. The voltage applied to the gate electrode can change the electron concentration in the third and fourth semiconductors under the gate, and as a result, the transistor operation for controlling the tunnel current between the source and drain can be performed. can get.

Next, a method of manufacturing the tunnel transistor of the second embodiment will be described. First, semi-insulating Ga
On the As substrate 1, a 100 nm-thick n ⁺ -GaAs layer 2 (concentration of 1 × 10 ¹⁹ cm ⁻³ Si) was formed on the As substrate 1.
Included as a punt. ) Is formed by a molecular beam epitaxy method, and then the portions other than the source region are removed by etching.
Next, a 100-nm-thick p ⁺ -Ga film that becomes the second semiconductor is formed.
As layer 4 (the Be concentration 1x10 ^{2 0 m-3-de} -. Containing a dopant), and the thickness 1 of the third semiconductor
8 nm n ⁺ -GaAs layer 5 (concentration of 1 × 10 ¹⁹ cm ^-3 S
i is included as a dopant. ) Are sequentially formed by a molecular beam epitaxy method. After removing the second and third semiconductors other than the drain region by etching, the exposed surface is again subjected to the molecular beam epitaxy method by the n-GaAs layer 6 (concentration 2 × 10 ¹⁸⁾ having a thickness of 12 nm as the fourth semiconductor.
It contains m ^-3 of Si as a dopant. ) And an Al _0.3 Ga _0.7 As layer 7 having a thickness of 40 nm to be an insulating layer are grown. Further, Al to be a gate electrode is vapor-deposited thereon, and then the Al / Al _0.3 Ga _0.7 As layer / n-GaAs layer is etched into the shape of the gate electrode 8. Finally, after etching away the n ⁺ -GaAs layer on the drain region, the first
Then, AuGe / Au is formed as a source electrode on the above semiconductor and AuZn / Au is formed as a drain electrode on the second semiconductor, respectively.

Similar to the first embodiment, the tunnel transistor of this structure and the manufacturing method thereof can form the tunnel junction without interrupting the growth, so that the residual impurity concentration at the junction interface is reduced and the surplus current is reduced by one digit or more. To do. In this structure, the source region and the drain region do not overlap in the vertical direction and have a planar structure. As a result, the parasitic capacitance between the source and drain is reduced, which is suitable for high speed operation.

Even in this structure, the fourth semiconductor layer does not necessarily have to be degenerated because it does not participate in the formation of the tunnel junction. Further, the second semiconductor is in contact with the fourth semiconductor layer on its side wall, but the junction area thereof is significantly smaller than the area of the tunnel junction composed of the second semiconductor and the third semiconductor. The impact can be ignored.

In Examples 1 and 2 of the present invention described above, only GaAs was shown as the semiconductor material used, but these layers are made of Si, Ge, InP, InGaAs, GaS.
It is obvious that the present invention can be applied to other semiconductors such as b and InAs.

Further, here, AlGaAs is used as the insulating layer.
However, other insulators such as SiO ₂ , Si ₃ N ₄ , and AlN, and semiconductor materials having a wider band gap than the third and fourth semiconductors (for example, GaP and InGaAs for Si) are used.
On the other hand, InAlAs or InP, GaSb or InAs may be AlGaSb).

[0033]

According to the present invention , the tunnel transistor
The structure of the semiconductor is described as "a first semiconductor having one conductivity type on a substrate.
A body, a separation layer made of a semiconductor with a low impurity concentration, and
A second semiconductor having a conductivity type opposite to that of the first semiconductor and degenerate
And has the same conductivity type as the first semiconductor
A laminated structure composed of a third semiconductor and the first semiconductor
The same conductivity type as the first semiconductor on the exposed surface of the third semiconductor
A fourth semiconductor having, and the third and fourth semiconductors
An insulating layer made of a material having a wider band gap than
An electrode on a layer and the first and second semiconductors
Each having a pair of electrodes forming an ohmic junction,
The insulating layer is used when the third and fourth semiconductors are Si.
Is GaP, and the third and fourth semiconductors are In
In the case of GaAs, it is InAlAs or InP,
The third and fourth semiconductors are GaSb or InAs
In this case, it is AlGaSb ”, and also“ less
Conductors that are selectively formed on a substrate with an insulating surface
A first semiconductor having a conductivity type and a first semiconductor on the substrate.
The first semiconductor selectively formed at a position different from the body
A degenerate second semiconductor having a conductivity type opposite to the body;
A third semiconductor having the same conductivity type as the first semiconductor.
And a small laminated structure on the surfaces of the first and third semiconductors.
Conductivity that contacts at least a part and has the same conductivity as the first semiconductor
A fourth semiconductor having a mold, and on the fourth semiconductor,
Is the material with a wider band gap than the third and fourth semiconductors?
An insulating layer, an electrode on the insulating layer, and the first half
Forming ohmic contact between the conductor and the second semiconductor
A pair of electrodes, and the insulating layer is
And the fourth semiconductor is Si, it is GaP, and
When the third and fourth semiconductors are InGaAs, I
nAlAs or InP, said third and fourth halves
When the conductor is GaSb or InAs, AlGaSb
Since the interface of the tunnel junction does not become a regrowth interface, the residual impurities in the tunnel junction are reduced. As a result, a good-quality bonding interface is obtained, its negative resistance characteristic is improved, and the range of application as a functional element is expanded.

[Brief description of drawings]

FIG. 1 is a structural schematic diagram of a tunnel transistor of a first embodiment of the present invention.

FIG. 2 is a structural schematic diagram of a tunnel transistor of a second embodiment of the present invention.

FIG. 3 is a schematic diagram of the structure of a conventional tunnel transistor.

[Explanation of symbols]

1 substrate 2 First semiconductor 3 separation layers 4 Second semiconductor 5 Third semiconductor 6 Fourth semiconductor 7 Insulation layer 8 gate electrodes 9 Source electrode 10 drain electrode

Claims (5)

(57) [Claims] 1. A first semiconductor having one conductivity type, a separation layer made of a semiconductor having a low impurity concentration, and a second semiconductor having a conductivity type opposite to that of the first semiconductor and degenerate on a substrate. A stacked structure made of a degenerated third semiconductor having the same conductivity type as the first semiconductor, and the same conductivity type as the first semiconductor on the exposed surface of the first semiconductor to the third semiconductor. A fourth semiconductor, an insulating layer made of a material having a bandgap wider than those of the third and fourth semiconductors, an electrode on the insulating layer, and ohmic junctions to the first semiconductor and the second semiconductor, respectively. And a pair of electrodes for forming the insulating layer, and the insulating layer is provided when the third and fourth semiconductors are Si.
Is GaP, and when the third and fourth semiconductors are InGaAs,
Is InAlAs or InP, and the third and fourth semiconductors are GaSb or InAs.
In the case, it is AlGaSb . 2. The tunnel transistor according to claim 1, wherein the isolation layer made of a semiconductor having a low impurity concentration is Andove GaAs. 3. The first to fourth semiconductors are GaA.
2. The tunnel transistor according to claim 1, wherein the material is one material selected from s, Si, Ge, InP, InGaAs, GaSb, and InAs. 4. A first semiconductor having one conductivity type that is selectively formed on a substrate whose surface is at least insulating, and a first semiconductor that is selectively formed at a position different from the first semiconductor on the substrate. A stacked structure composed of a degenerate second semiconductor having a conductivity type opposite to that of the first semiconductor and a third semiconductor having the same conductivity type as the first semiconductor; and the first and third layers. Contacting at least a part of the semiconductor surface, and
A fourth semiconductor having the same conductivity type as that of the first semiconductor, an insulating layer on the fourth semiconductor made of a material having a wider band gap than the third and fourth semiconductors, and an insulating layer on the insulating layer. An electrode and a pair of electrodes forming ohmic junctions with the first semiconductor and the second semiconductor, respectively , and the insulating layer is provided when the third and fourth semiconductors are Si.
In the case of GaP and the third and fourth semiconductors are InGaAs
Is InAlAs or InP, and the third and fourth semiconductors are GaSb or InAs.
In the case, it is AlGaSb . 5. The first to fourth semiconductors are GaA.
The tunnel transistor according to claim 4, wherein the tunnel transistor is one material selected from s, Si, Ge, InP, InGaAs, GaSb, and InAs.