JP2513118B2 - Tunnel transistor and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tunnel transistor whose negative resistance characteristic can be controlled and a manufacturing method thereof.

[0002]

2. Description of the Related Art A resonance tunnel transistor is known as a transistor having a negative resistance characteristic by utilizing a resonance tunneling phenomenon in a double barrier structure in a semiconductor. Regarding this, for example, Applied Physics Letters (Applied Physics Let)
ters), Vol. 59, p. 967, 1991, Longenbach et al. (K. F. Longenbach, e.
t. al. ) Has been described by the author.

FIG. 4 is a band diagram of a conventional resonance tunnel transistor. Quantum well 3 sandwiched by two barrier layers
, The quantum level shown by the dotted line in the figure is formed, and the source 4
The electrons inside tunnel through this double barrier layer, reach the drain 2, and become the drain current. At this time, only electrons having energy resonating with the quantum level can tunnel, and the drain current-voltage characteristic has a negative resistance characteristic. The electron concentration in the source can be changed by the voltage applied to the gate 3, and the collector current can be modulated.

[0004]

In the above-mentioned conventional tunnel transistor having the negative resistance characteristic, the resonance tunnel phenomenon in the double barrier structure is used to obtain the negative resistance characteristic. In this case, in this double-barrier structure transistor, electrons are trapped in the level formed in the quantum well surrounded by the double barrier, which results in a long tunnel time and is not suitable for high-speed operation. there were.

An object of the present invention is to provide a tunnel transistor and a method of manufacturing the same which can shorten the tunnel time and improve the operation speed as compared with the case of the conventional tunnel transistor using the resonant tunneling with the double barrier structure. To provide.

[0006]

The tunnel transistor of the present invention is formed on a substrate and has a first semiconductor exhibiting n-type conduction and an intrinsic ionization energy smaller than the electron affinity of the first semiconductor. And a barrier layer having an electron affinity smaller than those of the first semiconductor and the third semiconductor between the first semiconductor and the third semiconductor and having a thickness such that electrons can tunnel. Formed on the second semiconductor and the third semiconductor, which partially or wholly contains p-type ionized impurities, has a smaller electron affinity than the third semiconductor, and has a large first ionization energy. A source electrode having a stacked structure with a semiconductor and having an ohmic contact formed on a two-dimensional hole gas formed by joining a third semiconductor and a fourth semiconductor, and an ohmic contact with a first semiconductor on a substrate. A drain electrode formed was, is characterized by having a gate electrode to form a Schottky junction on the fourth semiconductor.

Further, according to the method of manufacturing the tunnel transistor of the present invention, the first semiconductor exhibiting n-type conduction is formed on the substrate, and the intrinsic first semiconductor has a first ionization energy smaller than the electron affinity of the first semiconductor. The third semiconductor has a barrier layer between the first semiconductor and the third semiconductor, the barrier layer having an electron affinity smaller than those of the first semiconductor and the third semiconductor and having a thickness that allows electrons to tunnel. A fourth semiconductor formed by sandwiching the second semiconductor, containing part or all of p-type ionized impurities on the third semiconductor, having a smaller electron affinity than the third semiconductor and a large first ionization energy. After forming a semiconductor, mesa etching is performed up to the first semiconductor, and ohmic contact is made with the two-dimensional hole gas formed by the bonding of the third semiconductor and the fourth semiconductor to form the source electrode, The drain electrode is formed by ohmic contact to the first semiconductor, it is characterized by forming a gate electrode and a Schottky junction on the fourth semiconductor.

[0008]

In the present invention, the band-to-band tunneling phenomenon of the single barrier structure is used in order to improve the operation speed of the tunnel transistor. Since there is no electron trap in the barrier in the single barrier structure, the tunnel time can be shortened as compared with the double barrier structure. According to the transistor of the present invention, a differential negative resistance is generated in the current-voltage characteristic, which is controlled by the gate electrode.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. 1 is a schematic sectional view showing a first embodiment of a tunnel transistor of the present invention, and FIG.
2 is an energy band diagram in the structure of FIG. In FIG. 1, 1 is a substrate, 2 is a first semiconductor forming a drain layer, 3 is a second semiconductor forming a single tunnel barrier, and 4 is a third semiconductor forming a source layer. A semiconductor, 5 is a fourth semiconductor forming a gate insulating layer, 6 is a source electrode, 7 is a drain electrode,
8 is a gate electrode.

Next, the operation of the tunnel transistor of the first embodiment will be described. In this embodiment, the substrate 1
nAs, n-InAs for the first semiconductor 2, AlSb for the second semiconductor 3, GaSb for the third semiconductor 4, p-AlGaSb for the fourth semiconductor 5, and AuZn / A for the source electrode 6.
uGe, AuGe / Au is used for the drain electrode 7, and Al is used for the gate electrode 8. Since the p-type ionized impurity is added to the fourth semiconductor 5, the two-dimensional hole gas is accumulated in the source region having a higher valence band energy than that of the fourth semiconductor 5. When a voltage is applied between the source and drain, the two-dimensional hole gas tunnels through the barrier, causing a drain current to flow. When the drain voltage is negatively applied to the source and the level of the two-dimensional hole gas comes to be located within the forbidden band of the drain, no current flows and a negative resistance characteristic occurs. Further, the concentration and energy level of the two-dimensional hole gas can be modulated by the gate voltage, and the transistor operation can be obtained.

The production was carried out by the molecular beam epitaxy method. First, a Si-doped InAs layer (first semiconductor 2) having a carrier concentration of 5 × 10 ¹⁸ cm ⁻³ and a thickness of 500 nm is formed on the InAs substrate 1 as a drain region, and a non-doped AlSb layer having a thickness of 8 nm is formed as a single tunnel barrier layer. (Second semiconductor 3), non-doped G having a thickness of 50 nm as a source region
An aSb layer (third semiconductor 4), a gate insulating layer having a carrier concentration of 2 × 10 ¹⁸ cm ⁻³ , a thickness of 20 nm, Be-doped Al _0.6 Ga _0.4 Sb, and a thickness of 20 nm of non-doped Al _0.6 Ga _0.4 Sb layer (the first semiconductor 4). Four semiconductors 5) are sequentially grown. After that, mesa etching is performed up to the InAs layer of the drain to form each electrode. The current-voltage characteristics of the manufactured tunnel transistor show negative resistance characteristics at room temperature,
A maximum of 3.7 was obtained as the ratio of the peak current to the valley current. Further, when the cutoff frequency at this time was estimated, about 520 GHz was obtained.

FIG. 3 is a band diagram of the second embodiment of the present invention. The first to third semiconductors are the same as in the first embodiment, and n-InAlAs is used as the fourth semiconductor. In this case, the two-dimensional electron gas accumulates in the source region and tunnels the single barrier. The same operation can be obtained by reversing the applied voltage to the tunnel transistor of the first embodiment. As in the case of the first embodiment, first, the carrier concentration was 5 × 1 on the InAs substrate 1.
0 ¹⁸ cm ⁻³ , 500 nm thick Be-doped GaSb layer (first semiconductor 2), 8 nm thick non-doped AlSb layer (second semiconductor 3), 50 nm thick non-doped InA.
s layer (third semiconductor 4), carrier concentration is 2 × 10 ¹⁸ c
m ^-3, sequentially grown undoped In _0.8 Al _0.2 As layer of Si added In _0.8 Al _0.2 As and a thickness of 20nm thickness 20nm (fourth semiconductor 5). Then GaSb
Mesa etching is performed up to the layer to form each electrode. The current-voltage characteristic of the manufactured tunnel transistor showed a negative resistance characteristic at room temperature, and a peak current-valley current ratio of 3.6 and a cutoff frequency of 580 GHz were obtained.

[0013]

As described above, since the tunnel transistor of the present invention uses the tunneling of the single barrier structure to obtain the negative resistance characteristic, the tunneling transistor of the conventional double barrier structure is used. In comparison, the tunnel time is shortened, and the operation speed can be improved.

The tunnel transistor of the present invention has an operating speed of about 3.4 as compared with the conventional tunnel transistor.
It doubled.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a first embodiment of a tunnel transistor of the present invention.

FIG. 2 is a band diagram of a first embodiment of the tunnel transistor of the present invention.

FIG. 3 is a band diagram of a second embodiment of the tunnel transistor of the present invention.

FIG. 4 is a band diagram of a conventional tunnel transistor.

[Explanation of symbols]

 1 Substrate 2 First Semiconductor 3 Second Semiconductor 4 Third Semiconductor 5 Fourth Semiconductor 6 Source Electrode 7 Drain Electrode 8 Gate Electrode

Claims (3)

(57) [Claims] 1. A first semiconductor which is formed on a substrate and exhibits n-type conduction; a third semiconductor which is intrinsic and has a first ionization energy smaller than the electron affinity of the first semiconductor; Between the semiconductor and the third semiconductor, a second semiconductor that forms a barrier layer having an electron affinity smaller than those of the first semiconductor and the third semiconductor and a thickness that allows electrons to tunnel, A fourth semiconductor, which is formed on a semiconductor and partially or wholly contains p-type ionized impurities, has a smaller electron affinity than the third semiconductor, and has a larger first ionization energy; On the 4th semiconductor, the source electrode on which the ohmic junction is formed on the two-dimensional hole gas formed by the junction of the semiconductor of 4th semiconductor and the 4th semiconductor, the drain electrode on which the ohmic junction is formed of the 1st semiconductor on the substrate To Tunnel transistor and having a gate electrode forming a Ttoki junction. 2. The tunnel transistor according to claim 1, wherein the first semiconductor and the third semiconductor are replaced with each other, and as the fourth semiconductor, an n-type ionized impurity is partially or wholly contained. A tunnel transistor characterized by using a semiconductor having a smaller electron affinity and a larger first ionization energy. 3. A first semiconductor having n-type conductivity is formed on a substrate, and the third semiconductor is intrinsic and has a first ionization energy smaller than the electron affinity of the first semiconductor. And a third semiconductor, the electron affinity is smaller than that of the first semiconductor and the third semiconductor, and a second semiconductor that forms a barrier layer having a thickness that allows electrons to tunnel is formed between them. Part of or the whole of the third semiconductor containing p-type ionized impurities, and has a smaller electron affinity than the third semiconductor,
A fourth semiconductor having a large first ionization energy is formed, and then mesa etching is performed up to the first semiconductor to form an ohmic contact with the two-dimensional hole gas formed by joining the third semiconductor and the fourth semiconductor. Forming a source electrode, forming a drain electrode by ohmic contact with the first semiconductor on the substrate, and forming a gate electrode by Schottky contact on the fourth semiconductor. Method.