JPH01158779A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the variations of a threshold voltage and the decline of increasing tendency of a transmission conductance by a method wherein the length of a gate is determined to be not longer than 0.5mum and the azimuth of the gate is selected so as to make a drain current flow to the [011] direction of a substrate crystal. CONSTITUTION:The crystal axis azimuth of a substrate 1 composed of a III-V compound semiconductor crystal is [011]. First, an i-type GaAs layer 2 with a thickness about 1mum is built up on the substrate 1 by crystal growth. Then, after an n-type AlGaAs layer 3 is built up on the layer 2 by crystal growth, the layer 3 is doped with an n-type dopant to form a hetero-junction structure. A source electrode 4 and a drain electrode 5 are deposited on the left and right ends of the layer 3 respectively. An insulating layer 6 is built up so as to cover the electrode 4, electrode 5 and layer 3, and a part of the insulating layer 6 is patterned with a gate length L to form a window 7. Then a Ti/Pt/Au layer is built up above the window and both the sides of the Ti/Pt/Au layer are scraped to form a gate electrode 10 with a length not larger than 0.5mum. With this constitution, the degradation of a threshold voltage and a transmission conductance due to the stress near the gate electrode can be suppressed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields (Figure 7) Prior Art
(Figure 4) Problems to be solved by the invention Examples of means and effects for solving the problems One embodiment of the present invention (Figures 1 to 3, Figures 5.6) Effects of the invention [Summary] Semiconductor Regarding the device, the present invention aims to provide a semiconductor device that can avoid changes in the dark voltage Vth and decrease in the increasing tendency of the transfer conductance gm even with a gate length of 0.5 μm or less, and is an m-v group compound semiconductor. A heterojunction is formed using the compound semiconductor on a substrate made of crystal, a two-dimensional electron gas layer formed at the interface of the heterojunction is used as a channel region, and a gate electrode is provided to face the channel region. , a field effect transistor element in which a source/drain region is formed at the end of a channel region, the field effect transistor element has a gate length of 0.5 μm or less, and the gate direction is such that the drain current is of the substrate crystal (
011) so that it flows in the direction.

[Industrial application field]

The present invention relates to a semiconductor device, and more particularly to a semiconductor device that uses a compound semiconductor and includes a minute FET with a gate length of 0.5 μm or less.

Substances that can form semiconductors are B (boron), A7!, which is in group II of the periodic table. , Ga (gallium), In (indium), etc., Si (silicon), Ge (germanium), Se (selenium), etc. of the ■ group, P (phosphorus), As (
Arsenic (arsenic), sb (antimony), etc., and currently Si (silicon)-based semiconductors from group II are mainly used. In recent years, along with the development of V-LSI technology using Sii conductors, so-called m-v group compound semiconductors consisting of elements of groups 1 and 2 have attracted attention as materials suitable for high-speed computers, and are particularly useful as light-emitting materials and light-receiving materials. As a material, it has many characteristics compared to Si-based materials. Its greatest feature is that compound semiconductors with desired properties can be freely produced by changing the ratio of the group (1) and group (2) components. In addition, compared to Si-based semiconductors, it is possible to create devices with great appeal, such as a wider temperature range, less noise, resistance to radiation, ability to emit and receive light, and good ultra-high-speed switching characteristics.

One of these ■-V group compound semiconductors is gallium arsenide (
In gallium arsenide, Ga atoms and As
Atoms are arranged alternately at the center and four corners of the tetrapod, and are arranged regularly in three dimensions. This is called a zincblende crystal structure. hatondono m
-V group compounds are crystallized in this form, and the atomic spacing, or in other words, the lattice constant, is slightly different.

In addition, A 12 G a As system, (Ga, In
) (P.

There are a number of II[-V compounds such as the As) series.

These compound semiconductors have recently attracted particular attention because they are used as materials for cutting-edge technologies such as optical communication/information processing technology and ultra-high-speed LSI.

Such single crystal semiconductors exhibit different properties depending on the orientation of the crystal lattice. In addition, the LSI manufacturing process involves chemical processes such as crystal growth, oxidation, diffusion, and etching of single crystal ingots, but the conditions for these processes often depend on the plane orientation of the crystal; Microfabrication technology that actively utilizes the characteristics is used. Miller indices are used to represent planes and orientations within a crystal.

The Miller index is defined as follows.

(b) With a certain arbitrary grid point as the origin, the fundamental vector i
, Lower, King is used as a coordinate axis, and the intersection of a certain plane and each coordinate axis is measured using the size of each fundamental vector as a unit.

(b) Take the reciprocal of the values of the three intersection points obtained, find β in the smallest integer Mih such that the ratios are equal, and express the plane as (hkA). The plane is the basic hector a, b
, c, the intersection is ■, so the reciprocal is O. If the planes intersect on the negative side of the fundamental vector, then (π
Write a negative sign above the number, such as kA). For example, when a certain plane intersects the coordinate axes determined by fundamental vectors a, b, and c at 2a, 3b, and 4c, respectively, the reciprocals are 1/2.1/3.1/4, which is the mirror of this plane. The index is (643).

FIG. 7 shows an example of a cubic lattice, which is important when considering semiconductor crystals. The numbers in the figure are Miller indices and indicate each side of the cubic lattice where the fundamental vectors a=b=c, h==j2=1. As can be seen from the figure, starting from the point of basic length a on the X axis, the side parallel to the y and z axes is (10
The side surface in the y-axis direction is represented by (010), and the side surface in the z-axis direction is represented by (001). These three aspects (1
00), (010), and (001) are orthogonal to each other. Further, the plane (011) has an angle of 45° with the y-axis and the Z-axis, as shown by the dotted line in the figure, and represents a plane parallel to the X-axis. Note that the plane (Oll) is a plane in which the z-axis is negative, that is, the plane exists in the opposite direction to the two axes in the figure.

To express the orientation of a crystal, the direction is expressed as a composition of each basic hector, and a set of component ratios is used. For example, direction r=h
a+kb+Ac is written using (hk6) and [], and to represent a set of directions equivalent to this, write (h, ni, n).
Expressed using In the cubic lattice, the orientation [hkβ] is the plane (
h, is perpendicular to -β).

[Conventional technology]

Similarly to Si-based FETs, If-V group compound semiconductor FETs also have channels in the source and drain regions in order to improve their characteristics, such as reducing the resistance between the source and gate and between the source and drain. It is desirable to introduce impurities at a higher concentration than the semiconductor region, and the gate electrode formed on the semiconductor substrate is used as a part of the mask to implant impurity ions at a high concentration and heat treatment to activate the implanted impurities. A structure is known in which a high impurity concentration region is formed by doing this, and source and drain electrodes are disposed in this region. For example, as an example, H
E M T (High Electron Mobi
In this HEMT, an undoped GaAs layer and an Si-doped n-AρxGa, -XAs layer are grown on a semi-insulating GaAs substrate using molecular beam epitaxial growth (MBE). Bea
n'-G was grown to a thickness of 0.07 μm by the m epitaxy method, and on top of this was grown an n'-G film doped with the same Sl.
An aAs layer is grown. The gate electrode of such a HEMT is made of (titanium-platinum-gold) TiPtAu, and the source and drain electrodes are made of A.
uGeAu is used, and the thickness of the depletion layer directly under the gate electrode is changed by the gate voltage to control the source-drain current. Note that the current-voltage characteristics are basically G
aAs MES FET (MEtal-5emic
onductor junction FET). In addition, in such HEMTs, the gate length (the length of the gate electrode in contact with the semiconductor) is at least greater than 0.5 μm, and the operating characteristics of a transistor operating at a high frequency are 0.5 μm or less. Although this is highly desirable, it has not yet been realized.

On the other hand, a semiconductor integrated circuit device previously disclosed by the present applicant in Japanese Unexamined Patent Publication No. 51-79577 is also known. In this device, a gate electrode provided on a substrate made of a ■-■ group compound semiconductor is aligned, a high concentration impurity is implanted into the channel region, and an electric field is applied to form source and drain electrodes at the edges of the substrate. A plurality of effect transistors (FETs) are provided, each of which has a gate width direction parallel to the (OO1) direction of the substrate crystal and a gate width direction parallel to the [010) direction of the substrate crystal. It contains an element.

The reason why the gate direction is limited with respect to the substrate crystal in this way is that when the gate length is shortened to 2 μm or less in order to increase the speed of semiconductor devices, the distance between the gate direction and the substrate crystal will be reduced. This is because some kind of correlation is recognized between the two.

[Problem that the invention seeks to solve]

However, in such conventional semiconductor devices, the following problems have become apparent as the gate length becomes finer. The first problem is a change in the dark value voltage vth, and the second problem is a decrease in the transfer conductance gm.

FIGS. 5 and 6 are diagrams showing changes in characteristics with respect to the crystal direction and gate length of the HEMT. Conventional HEMT (
, crystal axis orientation (011)), when the gate length is less than 0.5 μm, the pinch-off voltage Vp (
(almost the same as the dark value voltage vth) largely shifts to the (-) side, while the increasing tendency of the transfer conductance gm reaches a plateau at gate lengths of 0.5 μm or less and similarly deteriorates.

Note that the measurement conditions at this time are Vn-2V, In =
IQm A , , Wc = 200 p m.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device that can avoid changes in threshold voltage vth and decrease in the increasing tendency of transfer conductance gm even when the gate length is 0.5 μm or less.

[Means for solving problems]

In order to achieve the above object, the semiconductor device according to the present invention has m-v
A heterojunction is formed using the compound semiconductor on a substrate made of group compound semiconductor crystal, a two-dimensional electron gas layer formed at the interface of the heterojunction is used as a channel region, and a gate is formed opposite to the channel region. A field effect transistor element is provided with an electrode, and a source/drain region is formed at the end of a channel region, the field effect transistor element has a gate length of 0.5 μm or less, and has a gate orientation of 0.5 μm or less. A current flows through the substrate crystal (011
) so that it flows in the direction.

[For production]

In the present invention, a heterojunction is formed using a compound semiconductor on a substrate made of an m-v group compound semiconductor crystal, and a two-dimensional electron gas layer formed at the heterojunction interface is used as a channel region. A gate electrode is provided to face the channel region, and a source/drain region is provided at the end of the channel region to form an FET.
The ET has a gate length of 0.5 μm or less, and a drain current with a gate orientation of [011] of the substrate crystal.
Take it so that it flows in the direction.

Therefore, a decrease in dark voltage Vth (pinch-off voltage Vp) and transfer conductance gm caused by stress near the gate electrode is suppressed, and compared to conventional HEMTs, significant noise reduction and improvement in high frequency characteristics are achieved. Ru.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of a semiconductor device, particularly a HEMT, according to the present invention.

FIG. 1 shows a cross-sectional view of the HEMT, and in this figure, reference numeral 1 denotes a substrate made of semi-insulating GaAs. A compound semiconductor single crystal made of GaAs, which is a component of the substrate 1, is grown in a crystal growth apparatus into a large single crystal ingot having an axially cylindrical shape, and then the single crystal ingot is grown in a direction perpendicular to the axis of the single crystal. It is cut into thin cross-sections to form thin disc-shaped wafers. The single crystal ingot is produced by pulling the single crystal, which serves as a seed, upward in a crystal growth device, and this pulling direction is done in accordance with a specific crystal axis orientation of the semiconductor crystal, is the axial direction of the single crystal ingot.

This wafer becomes substrate 1, and its surface (crystal axis direction)
Each semiconductor layer is laminated to form a HEMT. Second
The figure shows HE with respect to the crystal direction within the ingot of single crystal 30.
The crystal axis orientation of MT is shown, and the second number in the figure each shows the Miller index when the single crystal 30 is considered as a cubic lattice.

In FIG. 2, the HEMT of this example is in the direction (011).
Therefore, it is written as (011)-HEMT. (
011)-The three rectangles of HEMT indicate the arrangement of each element (drain, gate, source). On the other hand, since the conventional HEMT has an orientation (011) (a direction perpendicular to the HEMT of this embodiment), it is written as (011)-HEMT. Therefore, the HEMT of this embodiment and the conventional HEMT differ in crystal axis orientation by 90°.

Returning to FIG. 1 again, in order to form the HEMT, first a layer of GaAs of the highest purity that can be produced is placed on the substrate 1.
The GaAs layer 2 is crystal-grown to a thickness of about 1 μm. In addition,
The crystal growth of the 1-GaAs layer 2 is performed using M B E (Mol
ecular Beam Epitax method or M
O-CV D (Metal Organic Che
It is carried out by the vapor deposition method.

Next, n-Aj2GaAs is deposited on the top surface of the 1-GaAs layer 2.
Layer 3 is similarly grown to a thickness of 35 μm. Thereafter, the n-AlGaAS layer 3 is doped with an n-type dopant such as Si to a carrier concentration of 2.times.10.sup.18 cm.sup.-'. 1-GaAs layer 2 and n-A7! The GaAS layer 3 constitutes a so-called heterojunction structure. And n −A
7! A source electrode 4 is placed at the left end of the Ga A 3 layer 3 in the figure.
A composition of uGe/Au (gold-germanillam/gold) is deposited by vapor deposition, and a drain electrode 5 is vapor-deposited on the right end of the n-AlGaAs layer 3 in the figure.

In addition, these source electrode 4, drain electrode 5 and n
-3402 or S to cover the A7iGaAs layer 3
The insulating layer 6 made of i3N4 is CV-treated to a thickness of 300 μm.
The layers are laminated by the D method, and then a window (gate) 7 is formed in the constant T-layer 6 (D- part (center part in the figure) with a gate length of 0.5 μm or less ("L" in the figure) by EB (electron beam) exposure.
) to butter.

This patterning is performed by etching the insulating layer 6, for example, by dry etching.

Next, Ti (titanium)/
Pt (platinum)/Au (gold) 100/100/5 respectively
The gate electrode 10 having a length of 2 .mu.m is formed by sequentially stacking the layers by vapor deposition to a thickness of about 0.00 .mu.m and cutting both sides by Ar (argon) milling. In this way, a HEMT with a gate length of 0.5 μm or less is formed.

Next, we will describe the effects of the HEMT with the above structure and compare its effects with the conventional HEMT.

HEMT is a heterojunction surface (i-GaAs layer 2 and n-
This is a field effect transistor (FET) that uses a two-dimensional electron gas layer 20 formed on the interface (15) of the AlGaAs layer 3 as a channel layer.

FIG. 3.4 is a diagram showing the effects of the HEMT of this embodiment and the conventional HEMT. In particular, using the structure of the HEMT shown in FIG. 011) direction. In these figures, the HEMT is represented only by the 1-GaAs layer 2, the n-A#GaAs layer 3, and each electrode 4, 5, and 10 in FIG. 1 to facilitate the explanation of the operation. In FIG. 3, a source electrode 4 and a drain electrode 5 are connected to -, respectively, of a DC power source.
Some of the electrons emitted from the highly concentrated donor impurity (Sl) near the source electrode 4 move across the heterojunction surface 15 to the 1-GaAS layer 2, which has lower energy, and - two-dimensional electron gas layer 20 parallel to GaAs layer 2;
(shown with diagonal lines in the figure).

That is, the n-A flGaAs layer 3 serves as a carrier supply source to the high-purity i-GaAs layer 2.

Furthermore, the two-dimensional electron gas layer 20 directly under the source electrode 4 and drain electrode 5 forms source and drain regions. The highly concentrated electrons transferred to the two-dimensional electron gas layer 20 are separated from the ionized donors and can move at high speed without being scattered by impurities.

Although the HEM T in this example has a gate length of 0.5 μm or less, it has a superior effect compared to the conventional one, but the principle thereof is not necessarily clear yet. It can be considered as follows. That is, n
- Si in the insulating layer 6 around the AnGaAs layer 3 is elongated due to the piezoelectric effect due to the potential difference between the source electrode 4, drain electrode 5, and gate electrode 10, and the n-AlGaAs layer 3
from both sides, or n-A from the gate electrode 10.
/! Electric charges are generated by the piezo effect directly under the gate electrode 10 compressed by stress on the GaAs layer 3 (hereinafter referred to as piezo charges). In the figure, piezoelectric charges are represented by + and - symbols, and a + charge is generated directly below the gate electrode IO, and a - charge is generated above the heterojunction surface.

The piezoelectric charge that depends on the voltage applied to the gate electrode 10 is ten charges in the two-dimensional electron gas layer 20,
The concentration of electrons in the two-dimensional electron gas layer 20 is changed to control the current. That is, the current characteristics of the HEMT can be controlled by the voltage applied to the gate electrode 10. At this time, in this embodiment, since positive charges are induced in the two-dimensional electron gas layer 20 directly under the gate electrode 10, the two-dimensional electron gas layer 20 is parallel to the heterojunction surface 15, and the movement of electrons is not affected much.

On the other hand, in the conventional HEMT shown in FIG. 4, a negative charge is induced in the two-dimensional electron gas layer 21 directly under the gate electrode 10 by a similar function, and the two-dimensional electron gas layer 21 similar to the two-dimensional electron gas layer 20 follows a concave path (arrow in the figure) due to the repulsion of negatively charged electrons, resulting in a meandering path. This meandering occurs when the electric field due to the piezoelectric charge of the two-dimensional electron gas layer 21 increases (gate length I5 in FIG. 1 is 0)
．． (referring to devices with a diameter of 5 μm or less), and the shorter the gate length, the farther away from the heterojunction surface 15 the meandering distance becomes. For this reason, in conventional HEMTs, elements with short gate lengths are significantly affected by the piezoelectric charge.

Fig. 5.6 is a diagram showing the change in characteristics with respect to the crystal direction and gate length of HEMT, and Fig. 5 shows the pinch-off voltage Vp.
FIG. 6 is a diagram showing changes in transfer conductance gm. In FIG. 5, the HEM of this example
For the T crystal axis orientation [011], the pinch-off voltage Vp does not change even if the gate length LO is 95 μm or less. On the other hand, conventional HE
MT (crystal axis direction [01 completed]) is gate length L 0.5
The pinch-off voltage Vp decreases significantly below μm. In FIG. 6, in the HEMT of this example, the transfer contamination gm (corresponding to hFE of a bipolar transistor) increases steadily even when the gate length is 0.5 μm or less, and even if the gate length is shortened, the transfer contamination gm (corresponding to hFE of a bipolar transistor) increases steadily, especially at high frequencies. It is possible to improve the characteristics in this area.

On the other hand, in the conventional HEMT, the gate length L is 0.75 μm
Below, the growth of the transfer conductance gm slows down and remains almost flat.

It is clear that the above phenomenon caused by piezoelectric charges generated in the n-ApGaAs layer 3 due to the compression of the gate electrode 10 depends on the crystal axis orientation (gate electrode orientation). The dependence of this phenomenon on crystal axis orientation is remarkable in short gate length devices with a gate length L of 0.5 μm or less, and in conventional HEMs.
In this embodiment in which the crystal axis orientation differs from T by 90°, deterioration of the pinch-off voltage Vp and the transfer conductance gm can be effectively prevented.

The practical application of such short gate length devices has conventionally been hindered due to significant deterioration of pinch-off voltage Vp and transfer conductance gm, but as a result of intensive research, the present inventors have discovered that the crystal axis of short gate length devices The discovery of the -1 direction dependence made it possible to put it into practical use.

That is, in the present invention, when producing a single crystal ingot, the orientation of the crystal axis is different from the conventional HEMT by 90 degrees (0
11) direction, it is possible to effectively suppress the deterioration of the pinch-off voltage Vp and the transfer conductance gm, resulting in significant noise reduction compared to the conventional HEMT.
It is possible to improve high frequency characteristics. In particular, when the gate length is set to 0.5 μm or less, the transfer characteristics in the high frequency region are significantly improved, and at the same time, the high-speed switching characteristics inherent to HEMT can be obtained.

〔Effect of the invention〕

According to the present invention, since the gate orientation of the substrate crystal made of an m-v group compound semiconductor is set to the [011] direction, which is 90° different from the conventional one, the threshold voltage vth (pinch-off voltage Vp) caused by stress near the gate electrode It is also possible to effectively suppress a decrease in transfer conductance gm, and it is possible to significantly reduce noise and improve high frequency characteristics compared to conventional HEMTs.

[Brief explanation of the drawing]

1 to 6 are diagrams showing one embodiment of a semiconductor device according to the present invention. FIG. 1 is a cross-sectional view of the HEMT, FIG. 2 is a diagram showing the crystal axis orientation of the HEMT, and FIG. is a diagram showing the action of the HEMT, Figure 4 is a diagram showing the action of the conventional HEMT to explain the effect of the HEMT, Figure 5 is a diagram showing the change in the pinch-off voltage Vp, and Figure 6 is the diagram. FIG. 7 is a diagram showing changes in transfer conductance gm. FIG. 7 is a diagram showing a side surface corresponding to the Mira constant of a cubic lattice. 1...Substrate, 4...Source electrode, 5...Drain electrode, 10...Gate electrode, 15...Heterojunction surface, 20... Two-dimensional electron gas layer (channel region, source region, drain region), L... Gate length.

Claims (1)

[Claims] A heterojunction is formed on a substrate made of III-V compound semiconductor crystal using the compound semiconductor, and a two-dimensional electron gas layer formed at the interface of the heterojunction is used as a channel region. , a field effect transistor element in which a gate electrode is provided to face a channel region, and a source/drain region is formed at an end of the channel region, and the field effect transistor element has a gate length of 0.5 μm or less. A semiconductor device characterized in that the gate orientation is set so that a drain current flows in the [011] direction of the substrate crystal.