JPS639983A - High-speed semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate superconduction by removing the local storage of the hole of a transistor using the superconductive mechanism of the pair of an electron and the hole by taking a hole current (an electron current when the hole current is taken) by a selective electrode and by short-circuiting. CONSTITUTION:Only the current by an electron is taken by the selective electrodes 9 and 10 of a source and a drain and a transistor is operated by controlling the depletion layer in an n-GaAs layer region 5 by the concentration of the electron and a gate electrode 6. An electrode 13 for taking from a (p) layer and the wiring 15 for a short-circuit are provided. Thus an electron layer 3 and a hole layer 2 have external connections to provide an external loop. The hole current of the hole layer easily flows since a loop which has an external route is provided, the superconductivity by the superconductive mechanism of the pair of an electron and a hole is not obstructed and the superconductivity can easily be obtained.

Description

[Detailed Description of the Invention] [Summary] Selective electrodes for source and drain are provided on one of the electron layer or the hole layer of an electron-hole pair superconductor consisting of an electron layer and a hole layer adjacent to each other by planar doping. In addition, a high-speed semiconductor device is provided with a pair of selection electrodes in the other layer, the selection electrodes are short-circuited, and the carrier concentration in the electron layer or hole layer is controlled by a third control electrode.

[Industrial application field]

The present invention relates to the structure of superconducting transistors that can operate at relatively high temperatures.

[Conventional technology]

Conventionally, superconducting phenomena have been observed at extremely low temperatures, about the temperature of liquid helium, and devices that utilize this phenomenon must be cooled to extremely low temperatures, making it difficult to use superconducting devices. Furthermore, there are no transistors using superconductivity on a practical level.

At the research stage, there are methods that use the seepage effect of superconductivity in field-effect transistors, and methods that use electron injection through Josephson junctions. Both use superconducting phenomena based on normal BC3 logic.

By the way, it has recently been proposed that superconductivity can be achieved at relatively high temperatures due to an electron-hole pair superconductivity mechanism created by composite particles of electron and hole pairs, and superconductivity occurs even at temperatures higher than liquid helium. I have come to understand that (Yu, E, L
ozovik and V,! , Yudson:
5 solid 5tate
ns 19 (1976) pp.

391-393). The superconductivity phenomenon in electron-hole pairs is based on the conventional BC8! This is completely different from what is described by the #i theory, and theoretically superconducting phenomena are expected even at room temperature.

The present inventors have conducted various studies to see if it is possible to realize a transistor by utilizing this electron-hole pair superconductivity mechanism, and one example is shown in FIG. 3. 1' semiconductor insulating (SI) GaAs substrate, 1' non-doped G
An aAs layer (buffer layer) is formed, and 2 p” Ga
As planar doped layer (Be doped, doping concentration 1
．． 1 x 10” elm-2), 1) non-doped GaAs layer (5 people), 4 non-doped GaAs layer (90
), 12 undoped GaAs layers (5), and n
-GaAs layers are stacked one after the other. The planar doped layers 2 and 3 form a hole layer and an electron layer. Reference numeral 5 is an n-GaAs layer doped with Si and having a doping concentration of I.times.10''(2)''3 and a thickness of 300 mm. Then, in each electrode region, 6 gate electrodes (AJ deposition), 7.8 source and drain electrodes AuGe/
After Au is deposited with silane, it is alloyed to form an ion implantation area for forming a selective electrode of 9.10 [implanted ion Se (selenium), implantation concentration peak concentration: 5×10' days (m-3)].

With the above configuration, an electron layer and a hole layer are formed sandwiching the non-doped GaAs-AIAs-GaAs insulating layer, and as a result, superconductivity occurs due to an electron-hole pair superconductivity mechanism.

(Problem to be solved by the invention) However, in the above case, since electrons and holes move in the same direction, no current flows in the whole, and therefore it is necessary to extract only one of the electron flow and the hole flow. In this case, for example, there is a problem that holes accumulate locally when an electron flow is extracted, which has the disadvantage of hindering superconductivity.

[Means for solving problems]

The present invention provides selective electrodes for sources and drains that make selective ohmic contact with one layer of the electron layer or the hole layer of an electron-hole pair superconductor consisting of an electron layer and a hole layer in close proximity by planar doping. and another selective electrode provided in close proximity to the source and drain electrodes and making selective ohmic contact with the other layer to provide a closed loop to the carriers in the other layer, and carriers in the electron or hole layer. Provided is a high-speed semiconductor device characterized by comprising a control electrode for controlling the concentration of.

[Effect]

The principle and operation of the present invention will be explained using the energy band diagram of the embodiment of the present invention shown in FIG.

In FIG. 2, the layer structure is such that an insulating Al1As thin layer 4 is interposed between GaAs layers 1 and 5.
As layer Aj! An n-type impurity is introduced near the As interface 3 by planar doping, and Aj! As/GaA
Similarly, a p-type impurity is introduced near the s-interface 2 by planar doping. and 2 along the interface 2.3.
Dimensional channel (hereinafter referred to as electron layer 3 and hole layer 2)
is formed, and a two-dimensional electron gas and a two-dimensional hole gas are formed sandwiching the insulating AlAs thin layer. To explain the formation process of the electron layer 3 and hole layer 2 in FIG.
Electrons from the planar doping layer of type impurity diffuse into the planar doping layer of p-type impurity 2 and fill the acceptors, so that the donors of the n-type planar doping layer 3 are ionized, thereby causing the The ends of the conduction band bend and the energy level decreases. On the other hand, the energy level of the valence band of the p-type planar doped layer 2 increases. As a result, an electric field is generated in a direction that impedes electron transition, and an equilibrium state is reached at a certain point. Figure 2 shows this equilibrium state, where the energy level at the edge of the conduction band of the n-type planar doping layer of 3 is the Fermi level EF.
It has declined further. On the other hand, the energy level of the valence band of the p-type planar doped layer of No. 2 has increased and is now above the Fermi level. Here, since the impurity concentration of the n-type planar doping layer No. 3 is sufficiently high, in this equilibrium state, carriers remain without being completely depleted and form an electronic layer. On the other hand, carriers also exist in the p-type planar doped layer 2, forming a hole layer.

When this two-dimensional electron gas and hole gas exist with an insulating thin layer sandwiched between them, synthetic particles are obtained by electron and hole pairs and become superconducting. However, due to this superconductivity,
Electrons and holes move in the same direction, and the current is canceled as a whole, so to obtain a transistor using superconductivity due to exciton synthesis particles of electrons and holes,
Only one of the electrons or holes must be extracted.

Therefore, in the present invention, a selection electrode is provided that contacts only the two-dimensional electron layer or the hole layer, and only one of the electrons and the holes is extracted.

However, there still remains a problem in obtaining a transistor based on the electron-hole pair superconducting mechanism.

The reason for this is, for example, when considering a configuration in which source and drain selective electrodes are formed in contact with a two-dimensional electron layer to extract electrons, no electrodes are formed in the hole layer and no hole flow is extracted. Therefore, holes locally stay and accumulate within the hole layer, which generates an electric field within the hole layer and impedes the hole flow.

Therefore, electron-hole pair superconductivity becomes difficult to occur.

Therefore, in the present invention, as described above, a selection electrode is formed also in the layer in which the source and drain selection electrodes of the electron layer or hole layer are not formed, and an external bus is also formed in the carrier of this layer. This facilitates the flow of carriers, making it easier for superconductivity to occur due to the electron-hole pair superconductivity mechanism. and,
With this configuration, an electron-hole pair superconductivity mechanism can be realized even at a relatively high temperature, and an element capable of transistor operation can be obtained.

C Example] The present invention will be explained in detail below using the drawings.

FIG. 1(A) shows a cross-sectional configuration of a main part of a transistor according to an embodiment of the present invention, and FIG. 1(B) shows an arrangement of electrodes on its upper surface.

In FIG. 1(A), each layer is as follows.

1.-Semiconductor insulating (SI) GaAs substrate 1'-
Non-doped GaAs layer (buffer layer) 2・-p ” −
GaAs planar doped layer Be (beryllium) doped,
Doping concentration 1, I ) Dope, doping concentration 1, lX10凰3 cff
l-2 5.=n -GaAs layer St-doped, doping concentration 1 x 101" C1)-3 thickness 300 people These layers are grown by MBE (molecular beam epitaxial growth) or MOCVD (metal-organic chemical vapor deposition), etc. can be formed in sequence.

Next, using a suitable mask, as shown in FIG. 1(A), the mesa 15 is formed by selectively removing up to 3 n''-GaAs planar doped layers by etching.

Hereinafter, each electrode region is formed as follows.

6.-- Gate electrode (^l deposition) 7.8-- Source and drain electrodes After depositing AuGe/Au, alloying 9.10-11 Ion implantation region for selective electrode formation Implantation of Se (selenium) ions ), implantation concentration peak concentration 5x 101) 1 cm-313-P layer extraction electrode (alloyed after AuZn deposition) 14.-Ion implantation area for p layer selective electrode formation As -M
Further, referring to the planar configuration of the electrodes shown in FIG. 1(B), in addition to the source S, drain D, and gate G of the transistor, there is a p Layer extraction electrode (13 in Figure 1 (A))
A short-circuit wiring 15 is formed.

Next, the transistor operation of the device of this example will be explained.

Of the electrons from the 3n"-GaAs planar doped layer, 1x10I3c1)-2 are from the 2p"-GaAs
It does not become a free carrier because it fills the acceptors in the planar doped layer. Therefore, n”-GaAs
1 x 1012 cIII-2 electrons in planar doped layer 3, 1 x 101 in 2 p++-GaAs planar doped layers
Each hole of 3 cm-2 remains as a free carrier.

These two layers are composed of 100 undoped layers, ie undoped GaAs layer 1). Since they are separated by 12 (5 layers each) and 4 non-doped AlAs layers (90 layers each), they become superconductive at low temperatures due to the electron-hole pair superconductivity mechanism described above. The superconducting region is the ion implantation region 9 for selective electrode formation among the electron layer and hole layer in 2.3.
．． This is the part between 9.10 and 9.10.

Due to this superconductivity, electrons and holes move in the same direction, and the current is canceled as a whole. Therefore, in order to enable transistor operation, the source and drain selection electrodes 9 and 1
0, only the current due to electrons is taken out. Then, the concentration of these electrons is controlled by the gate electrode 6 to 5 n −
The transistor operation is controlled by controlling the depletion layer in the GaAs layer region.

In the above embodiment, since the pFi extraction electrode 13 and the short-circuit wiring 15 were provided, the electrons in the electron layer 3 are taken out to the external circuit by the drain selection electrode, and then passed through the source selection electrode again to the electron channel 3. However, since the hole layer 2 is also provided with a p-layer extraction electrode (13 or H in FIG. 1) and a short-circuit wiring 15, the electron layer 3 and the hole Since layer 2 is both drawn out to the outside and has a loop that passes through the outside, the hole flow in the hole layer becomes easier to flow, and superconductivity due to the electron-hole pair superconductivity mechanism is inhibited. disappears, making it easier for superconductivity to occur.

Next, the use of planar doping in this embodiment will be explained.

When the electron layer 3 and hole layer 2 are doped using normal doping, electrons move from the n layer to the p layer, so
A carrier depletion layer is formed, increasing the distance between the electron layer and the hole layer, making it difficult to achieve superconductivity. On the other hand, when planar doping is performed as in this example, the doping concentration is extremely high and no depletion layer is formed, so the electron layer and hole layer remain on the planar doped surface, and the insulating layer Superconductivity occurs due to the electron-hole pair superconductivity mechanism due to the electron and hole pairs generated by sandwiching the two.

In the above embodiment, the source and drain selection electrodes are formed in the electron layer, but the source and drain selection electrodes may be formed in the hole layer. Also,
As shown in FIG. 1, the selection electrode for the p-layer and the p-layer lead-out electrode 13 are provided in pairs in the direction in which the sources and drains are arranged, and are not limited to short-circuiting with the short-circuit wiring 15; A selection electrode and a p-layer extraction electrode may be provided for a pair of p-layers in the direction.

Furthermore, the selection electrode for the p layer and the p layer extraction electrode may be formed in an annular shape so as to closely surround the element region including the source, gate, and drain.

〔Effect of the invention〕

As described above, according to the present invention, the accumulation of holes (accumulation of electrons when extracting a hole flow) in a transistor that utilizes an electron-hole pair superconducting mechanism is This can be prevented by extracting the electron current (electron current) using a selective electrode and short-circuiting it.

[Brief explanation of drawings]

FIG. 1(A) is a sectional view of an embodiment of the present invention, FIG. 1(B)
FIG. 2 is an energy band diagram of the embodiment, and FIG. 3 is a sectional view of the main part of the conventional example. 1 - Semiconductor insulating (SI) GaAs substrate 1)
・-Non-doped GaAsFf 2--- p''-GaAs planar doped layer 3 ・
-n'' -GaAs brainer doped layer 4-Non-doped Aj!As layer 5--n-GaAsFi 6-Gate electrode (An deposition) 7.8-m-Source and drain electrodes 9.10-11 Ions for forming selective electrodes Injection area 1).1
2-m-non-doped GaAs layer 13-p-layer extraction electrode 14...-p-layer selective bridge formation ion implantation region 15--
Wiring for short

Claims (1)

[Claims] (1) Selective electrodes for sources and drains that make ohmic contact selectively with one layer of the electron layer or hole layer of an electron-hole pair superconductor consisting of an electron layer and a hole layer in close proximity by planar doping. , another selective electrode provided in close proximity to the source and drain electrodes and selectively in ohmic contact with the other layer to provide a closed loop for carriers in the other layer; A high-speed semiconductor device comprising a control electrode for controlling concentration.