JPS59968A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electron mobility in a high electric field from decreasing in a high electron mobility transistor by increasing the difference of the electron affinity in a hetero junction between a channel layer and an electron supply layer. CONSTITUTION:A GaAs (channel) layer 12, and an AlxGa1-xAs layer which has a region 13 having no impurity and an N type region 14 are sequentially formed on a GaAs substrate 11. Si is introduced as an impurity to the region 14. Then, AuGe/Au<2> layer is deposited on the position where a source electrode 15 and a drain electrode 16 are arranged, and a resistive connection region 17 to the layer 12 is formed. Then, a gate electrode 18 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to semiconductor devices, and in particular,
High electron mobility transistor proposed in Application No. 55-82035
tyTransistor: hereinafter abbreviated as HEMT)
Regarding the improvement of

(b) Technology background: It is believed that further improvements in the capabilities and cost performance of information processing devices depend on the semiconductor devices used in them, and improvements in the speed and power consumption of logical arithmetic devices and the reduction in power consumption of memory devices are essential. Larger capacity is being strongly promoted.

Currently, only silicon (Sl) semiconductor devices are in practical use, but the speedup of St-type conductor devices is limited by the physical properties of 81 such as carrier mobility, so carrier mobility is around 81 higher than 81. Efforts are being made to achieve higher speeds and lower power consumption using compound semiconductors such as gallium arsenide (GaAs).

In a conventional semiconductor device using a compound such as 81 or GaAs, carriers move in a space where impurity ions are present. During this movement, carriers are scattered by lattice vibrations and impurity ions,
When the temperature is lowered to reduce the probability of scattering due to lattice vibrations, the probability of scattering due to impurity ions increases, thereby limiting carrier mobility.

In order to eliminate this impurity scattering effect, the region where impurities are added and the region where carriers move are spatially separated, thereby increasing the carrier movement by 1, especially at low temperatures. The target is a high electron mobility transistor (HKMT).

(e) Conventional technology and problems An example of a conventionally known structure of HEMT is shown in Figure 1 (a).
This will be explained with reference to the cross-sectional view shown in FIG. A non-doped GaAs layer 2 and a nu aluminum gallium arsenic (AAGa) layer with a smaller electron affinity are formed on a semi-insulating GaAs substrate 1.
Ai) layer 3 is provided, and the interface between both layers forms a heterojunction. n MALGaAs layer 3 (referred to as electron supply layer) to non-doped GaAs layer 2 (referred to as channel layer)
The concentration of electrons in the electron storage layer (two-dimensional electron layer) 4 generated by the transfer of electrons to the gate electrode 54 is controlled by the voltage applied between the source electrode 6 and the drain electrode 7. The impedance of the conduction path formed by the electron storage layer 4 is controlled by fil.

Note that 8 is a resistive connection (open contact) region.

The conventional HEMT is as described above (a non-doped GaAs layer 2 on a GaAs substrate 1, and a heterojunction n
It has a layer 3 of At*G & straight-X As, and the bonding interface side of this n-ya AL
(2) It is known that a non-doped region of about 100% is used as a buffer.

These nMM or non-doped AtxGal-X
Conventionally, the composition ratio
(b) ALxGal-xAs, which tends to deteriorate when the composition ratio X is constant and cause disturbances at the bonding interface.
Impurities such as oxygen are mixed into the epitaxial layer along with active At, forming a deep level that acts as a carrier wrap, which tends to adversely affect the electronic properties of the crystal. This is because contact tends to deteriorate, etc. during mt-.

In the case of At composition ratio X = 0.3 - this is GaAs layer 2 and A
to, 8 Ga4) and the yAs layer 3 is approximately 0.3(
A difference in electron affinity of eV,' occurs, and n-type A t O,
3Q IL 0.7 Carrier electrons are transferred from the As layer 3 to the GaAs layer 2 to form an electron storage layer 4.

However, when the difference in electron affinity is about 0.3 (eV), when the electric field formed through the source electrode 6 and the drain electrode &i is lowered in the electron storage m4, the original high electron mobility However, at an electric field strength gL used to operate an actual semiconductor device, the electron mobility is lower than at a low electric field. This is because carrier electrons gain large kinetic energy in a high electric field, causing the distribution of the two-dimensional electron layer to shift more than in a low electric field, and the carrier electrons cross the barrier and leak into the ALxGal-XA11 layer 3, which has low electron mobility. It depends.

In order to prevent the electron mobility from decreasing in this high electric field, the GaAs layer 2 which is the channel layer and the A layer which is the electron supply layer are required.
LxGhl-x It is sufficient to further increase the difference in electron affinity with As scrap 3, that is, to make the At composition ratio Xt-0, even larger than 3, but increasing the At composition I ratio Xt causes the problem mentioned earlier. accompanies.

(Φ Purpose of the Invention The present invention relates to a high electron mobility transistor (HgMT) by expanding the difference in electron affinity at the heterotetrajunction between the channel layer and the electron supply layer to suppress the decrease in electron mobility in high electric fields. It is an object of the present invention to provide a structure that prevents deterioration of the crystal state of an electron supply layer.

(e) Structure of the Invention The object of the present invention is to provide a semiconductor layer comprising a first semiconductor layer and a second semiconductor layer having a lower electron affinity than the first semiconductor layer and containing an n-type impurity. , the first semiconductor layer and the second semiconductor layer form a heterojunction, and a two-dimensional electron layer constituted by electrons transitioning from the second semiconductor layer to the first semiconductor layer is used as a current path. This is achieved by a high electron mobility semiconductor device in which the composition ratio of the elements constituting the second semiconductor device is such that the electron affinity is small in the vicinity of the tetraheterojunction.

(f) Embodiments of the Invention The present invention will be specifically described below by way of embodiments with reference to the drawings.

Figure 2(a) shows GaAs and AtxGaI-XAIk
FIG. 2(b) is a cross-sectional view of an embodiment of the present invention constructed using
) is a chart showing an example of the distribution of the At composition ratio X in this example, corresponding to each layer in FIG. 2(a).

The HEMT of this example is manufactured approximately as follows. A molecular beam crystal growth method (
Motecutar Beam Epitax3'S
Hereinafter abbreviated as MBE method), a GaAs layer (channel layer) 12 containing substantially no impurities and having a thickness of approximately 1 [μm] and a GaAs layer (channel layer) 12 containing substantially no impurities and having a thickness of 5 to 20 nm (nm) are formed. ) area 13 and thickness 0.1 to 0.2
AtxGal- consisting of an n-type region 14 of about [μm]
In this example, for the impurity-free region 13 of the AtxGaI-xA'' layer, the At composition ratio For example, it is highest at about X = 0.4, and gradually decreases as the distance from the bonding interface increases, and
The composition ratio X=O, a, which is the same as that of No. 4, has been reached. (Second
(See figure (b)). Further, silicon (Si) is introduced into the n-type Tsukuda region 14 as an impurity during crystal growth by the MBE method.

After forming the epitaxial growth layer, a gold germanium b (AuGe)/gold (Au) layer is selectively deposited at the positions where the source electrode 15 and the drain electrode 16t are to be provided, and is further deposited at a temperature of 450 (°C) for about 3 minutes. This is alloyed by heat treatment to form a resistive connection region 17 with the GaAs layer 12 serving as a channel layer.Then, a gate electrode 18 is formed using, for example, aluminum (At) by a conventionally known method. Note that 19 indicates an electron storage layer.

HE of this example obtained by the manufacturing method explained above
The energy band of MT is shown in Fig. 3. However, in Fig. 3, °C is the same sign as in Fig. 2(a), and c is A4xGa, -XA I according to the conventional technology of the valence band.
This shows a case where the At composition ratio X is a constant value of about 0.3 for the entire layer, and the broken line shown in region 13 shows a state in which the embodiment of the present invention is different from the conventional example.

As is clear from FIG. 3, in the structure of the present invention,
The size of the barrier in the heteroepitaxial junction field 1 was expanded compared to the conventional one, and an electron mobility of about 35.000 (eJ/v-s°) was obtained for the carrier charge.In contrast, the AtxGal-XA21 layer The electron mobility under the same conditions of a comparative sample in which the At composition ratio was kept constant up to the heterojunction interface remained at about 20.000 Wv-s.

In addition, as mentioned earlier, the At of the AAxGa, -XAI layer
An increase in the At composition ratio Xt- tends to cause deterioration of the crystal state or an increase in the contact resistance of the orthogonal contact electrode. However, when the At composition ratio Xt- is increased in an extremely thin layer as in the present invention, the above point can be avoided. It was confirmed by the test results of the above-mentioned Examples that this was not a problem.

In this embodiment, the At composition ratio X near the heterojunction interface was changed linearly by #1 in the non-doped region 13, but the effect of the present invention is that the At composition ratio X changes linearly. It is not limited to cases where
It may change in a curved or stepwise manner, and the range in which the At composition ratio
The non-doped region 13 does not necessarily have to be provided.

Furthermore, although the above explanation uses an example of HEMTt' using GaAs/AtGaAs, HEMT is
It can also be constructed by a combination of antimony (GaSb) and aluminum, potassium, antimony (CatyGaz-ysb), and such GaAs/A
It is also possible to apply the present invention to HEMTs using materials other than tGaAs.

(Effects of the Invention According to the present invention, as explained above, carrier electron mobility in the electron storage layer, that is, the two-dimensional electron layer, is prevented from decreasing in a high electric field, and the two-dimensional electron layer is formed, etc.)
Since it does not have a negative influence W on the characteristics of i E MT, high-density integration of HEMTs greatly contributes to realizing a high-speed, low power consumption semiconductor device i'.

[Brief explanation of drawings]

FIG. 1(a) is a sectional view showing a conventional example, FIG. 1(b) is a chart showing the At composition ratio X of each layer, and FIG. 2(a) is a sectional view showing an embodiment of the present invention. FIG. 2(b) is a chart showing the At composition ratio X of each layer, and FIG. 3 is a chart showing its energy band. In the drawing numbers, 1 is a GaAs substrate, 2 is a GaAs substrate, and 2 is a GaAs substrate.
M s3 is an Al x Gar-z As layer, 4 is an electron storage layer, 5 is a gate electrode, 6 is a source electrode,
7 is a drain electrode, 8 is a resistive connection region, 11 is GaA
s substrate, 1.2 is a non-doped GaAs layer, 13 is A
Non-doped region of LxGal-xA 8 layer, 14 is Alx
n-type region of Ga1-xAs layer, 15 is source electrode, 16
1 is a drain electrode, 17 is a resistive connection region, 18 is a gate electrode, and 19 is an electron storage layer. i) t) Rod 2 diagram (Q-) (I rod diagram

Claims (1)

[Claims] The first semiconductor layer and the second single conductor layer have a lower electron affinity than the first semiconductor layer and contain all n-shield impurities. A high electron mobility wJ semiconductor device in which a two-dimensional electron layer formed by a semiconductor layer or a heterojunction and configured by electrons transitioning from the second semiconductor layer to the first semiconductor layer is used as a current path. There it is,
A semiconductor device, wherein the composition ratio of elements constituting the second semiconductor layer is such that electron affinity is small in the vicinity of the heterojunction.