JPS62130565A - Field effect type semiconductor device - Google Patents

Field effect type semiconductor device

Info

Publication number
JPS62130565A
JPS62130565A JP27051085A JP27051085A JPS62130565A JP S62130565 A JPS62130565 A JP S62130565A JP 27051085 A JP27051085 A JP 27051085A JP 27051085 A JP27051085 A JP 27051085A JP S62130565 A JPS62130565 A JP S62130565A
Authority
JP
Japan
Prior art keywords
layer
doped
gaas
xas
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27051085A
Other languages
Japanese (ja)
Inventor
Tomonori Ishikawa
石川 知則
Yasumi Hikosaka
康己 彦坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP27051085A priority Critical patent/JPS62130565A/en
Publication of JPS62130565A publication Critical patent/JPS62130565A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Abstract

PURPOSE:To reduce a decrease in a saturated current by forming an energy barrier layer in a hetero junction of a channel layer for generating secondary electron gas to suppress transition of the gas. CONSTITUTION:A buffer layer 2 made of non-doped GaAs, an non-doped AlxGa1-xAs layer 3 (x=0.3), and a spacer layer 5 made of non-doped AlxGa1-xAs (x=0.3) are sequentially formed on a semi-insulating GaAs substrate 1. A channel layer 6 made of non-doped GaAs is formed through a barrier layer BB on the layer 5. An Si-doped AlxGa1-xAs layer 7 (x=0.3), a cap layer 8 made of Si-doped GaAs and source and drain electrodes 9, 10 are sequentially formed through a barrier layer BA on the layer 6. The layers BB, BA are both formed of non-doped AlxGa1-xAs (x>0.3) or AlAs and so formed thin in the degree as not to tunnel carrier.

Description

【発明の詳細な説明】 C概 要〕 高電力用HEMTの構造であって、2次元電子ガスが形
成されるチャネル層のへテロ界面にバンドギャップが大
きなA11!GaAsまたはAlAs等のエネルギー・
バリアを形成することによりパワーゲインを向上する。
[Detailed Description of the Invention] C Overview] This is a high power HEMT structure in which A11 has a large band gap at the hetero interface of the channel layer where two-dimensional electron gas is formed! Energy such as GaAs or AlAs
Improving power gain by forming a barrier.

〔産業上の利用分野〕[Industrial application field]

本発明は、高出力用電界効果型トランジスタHEMTに
係り、特に、2次元電子ガスが生じるチャネル層のへテ
ロ界面にエネルギー障壁層を設けた素子構造に関する。
The present invention relates to a high-output field effect transistor HEMT, and particularly to an element structure in which an energy barrier layer is provided at a heterointerface of a channel layer where two-dimensional electron gas is generated.

〔従来の技術〕[Conventional technology]

従来、高出力用HEMT(高電子移動度トランジスタ)
として、ダブルへテロ型の選択ドープ侮As/rL−A
l13;Ga1−zAsへテロ構造(x=0.3)が用
いられている。
Conventionally, high-power HEMT (high electron mobility transistor)
As, double hetero type selective doping As/rL-A
l13; Ga1-zAs heterostructure (x=0.3) is used.

第4図にその素子要部断面を示している。第4図におい
て、41は半絶縁性GaAs基板、42はバッファ一層
、43は非ドープA 1.21.G a +−jcA 
s Jtiii (x=0.3 ) 、44はSiドー
プのA l z G 11 + −z A 5(x=0
.3)層、45はスペーサ一層の非ドープの4、よGa
、−□As  、46はチャネル層の非ドープのGaA
、、r  、47はSi ドープのAlxGalzAs
層(、=0.3 ) 、48はキャップ層の5i)−プ
のCrctAs層であり、ソース及びドレイン電極49
及び5oが形成されている。
FIG. 4 shows a cross section of the main part of the element. In FIG. 4, 41 is a semi-insulating GaAs substrate, 42 is a buffer layer, and 43 is an undoped A 1.21. G a +-jcA
s Jtiii (x=0.3), 44 is Si-doped Al z G 11 + -z A 5 (x=0
.. 3) layer 45 is a spacer layer of undoped 4, Ga
, -□As, 46 is undoped GaA of the channel layer
,,r,47 is Si-doped AlxGalzAs
The layer (,=0.3), 48 is a CrctAs layer of 5i) as a cap layer, and the source and drain electrodes 49
and 5o are formed.

第5図に第4図の素子の断面組成図を示してあり、横軸
に表面からの距離を示し、縦にX値(ルルのモル比)を
表している。第5図に於いて、斜線を施した部分がn型
不純物のドープ層を表し、この両便1のドープされたA
lGaAs 層から電子がチャネル層46にそれぞれ供
給されるため電子密度が大きくとれる。このとき、チャ
ネル層46を十分薄く形成しておくと(150A程度)
両側のキャリア供給層からの電子の波動関数は完全に重
なり、単一のキャリアを形成する。それ故、この様な構
造は2次元電子ガスの電子密度が大きくとれ、高出力H
E M Tの提供を可能とする。
FIG. 5 shows a cross-sectional composition diagram of the element shown in FIG. 4, in which the horizontal axis represents the distance from the surface, and the vertical axis represents the X value (Lulu molar ratio). In FIG. 5, the shaded area represents the n-type impurity doped layer, and the doped A
Since electrons are supplied from the lGaAs layer to the channel layer 46, the electron density can be increased. At this time, if the channel layer 46 is formed sufficiently thin (about 150A)
The wave functions of electrons from the carrier supply layers on both sides completely overlap to form a single carrier. Therefore, such a structure allows the two-dimensional electron gas to have a large electron density, and is capable of producing high output H.
Enables the provision of EMT.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところが、上記従来の高出力用HEMTは、高電圧側に
おけるソース/ドレイン飽和電流1tssの減少がかな
り大きいという欠点があった。
However, the conventional high-output HEMT described above has a drawback in that the source/drain saturation current 1tss decreases considerably on the high voltage side.

第6図に従来の高出力用HE M Tの特性図を示して
いる。第6図において、横軸にソース/ドレイン間の電
圧VDs(v)を示し、諮軸にソース。
FIG. 6 shows a characteristic diagram of a conventional high-output HEMT. In FIG. 6, the horizontal axis shows the source/drain voltage VDs (v), and the horizontal axis shows the source.

ドレイン間の電流値17 s (m A )を示す、図
のように、従来の高出力HEMTではVDSが高い方で
ソース/ドレイン飽和電流1dssの低下が大きいく実
線で指示)。この高電圧側での飽和電流の低下はGaA
3M E S F E Tの場合においてもみられるが
(点線で詣示)、これに比べてかなり大きく、パワーゲ
インを太き(する上で障害となる。
As shown in the figure, which shows a drain-to-drain current value of 17 s (mA), in a conventional high-output HEMT, the source/drain saturation current 1 dss decreases greatly when VDS is high (indicated by a solid line). This decrease in saturation current on the high voltage side is caused by GaA
This can also be seen in the case of 3M E S F E T (indicated by the dotted line), but it is considerably larger than this and becomes an obstacle in increasing the power gain.

〔問題点を解決するための手段〕[Means for solving problems]

そこで、本発明者等は、種々検討を重ねたが、前記高出
力用HE M Tでの高電界側(2■)以上での飽和電
流1dssの低下はGaAs M E S F E T
の場合に比べて大きく、虫に熱的な原因による移動度の
低下だけでは説明がつかずHEMT構造に特有のもので
あることがわかった。そして、その原因は、高電界によ
る2次元電子ガスのAlGaAsへの実空間遷移により
、実効的に移動度が低下することによるとの結論に達し
た。そこで、まずルエGa1−xAsのX値を0.3よ
り大きくしてヘテロの障壁を大きくすることが考えられ
るが、結晶の不整合(ミスマツチ)やAlが多くなると
不純物をゲッターする効果が現れるためきれいな界面が
形成されず実際上不可能である。
Therefore, the present inventors conducted various studies, and found that the decrease in saturation current of 1 dss on the high electric field side (2■) or higher in the high power HEMT is due to GaAs MESFET.
This was found to be unique to the HEMT structure, and could not be explained solely by a decrease in mobility due to thermal causes. It was concluded that the reason for this is that the two-dimensional electron gas transitions to AlGaAs in real space due to a high electric field, resulting in an effective decrease in mobility. Therefore, it is possible to first increase the hetero barrier by increasing the X value of Lue Ga1-xAs to more than 0.3, but this is because the effect of gettering impurities appears when the crystal mismatch or Al content increases. This is practically impossible because a clean interface is not formed.

そこで本発明においては、2次元電子ガスが形成される
チャネル層のへテロ界面にバンドギャフプが大きな、灯
GaArま々はA IAs等のエネルギー・バリア(以
下障壁層という)を電子がトンネルしない程度でできる
だけ薄く形成した高電力用HE M Tの素子構造を提
供するものである。
Therefore, in the present invention, a GaAr lamp with a large band gap at the hetero interface of the channel layer where a two-dimensional electron gas is formed is used to prevent electrons from tunneling through an energy barrier (hereinafter referred to as a barrier layer) such as AIAs. The present invention provides a high power HEMT element structure that is formed as thin as possible.

〔作 用〕[For production]

ソース/ドレイン間に高電圧がかかる飽和状態において
、高電界によりエネルギーを得て電子はホットになって
いる。その結果、通常のHEMTで用いられるGaAs
 / Al、、; Ga+−z:As (x =0.3
)のヘテロ接合のバリアを越えてチャネルの電子がAI
工Ga 1−、A、S一層の方に78みだしてくる。特
に、ゲートバイアスの関係で、基板側のAIGaAsN
に電子の滲み出しが多い。ここで、 AlGaAsはG
aAsに比較して移り1度が低い上、ドープされた不純
物の関係でさらに移動度が低下している。このようなA
eGahs Fiにチャネル層の電子が11みだして(
るとその分電流が低下することになる。
In a saturated state where a high voltage is applied between the source and drain, the electrons gain energy from the high electric field and become hot. As a result, the GaAs used in normal HEMT
/Al, ,; Ga+-z:As (x = 0.3
), the channel electrons cross the barrier of the heterojunction
78 protrudes toward the engineering Ga 1-, A, and S layers. In particular, due to gate bias, AIGaAsN on the substrate side
There is a lot of electron leakage. Here, AlGaAs is G
In addition to having a lower mobility than aAs, its mobility is further reduced due to the presence of doped impurities. A like this
11 electrons from the channel layer leak out to eGahs Fi (
Then, the current will decrease accordingly.

しかし、上記本発明の構成によれば、障壁層を設けたの
で、2次元電子ガスのAIGαA、?側への遷移を抑え
ることができ、高電圧側での飽和電流の低下を防ぎ、電
力利得の大きな高出力用)IEMTを得ることができる
However, according to the configuration of the present invention, since the barrier layer is provided, the two-dimensional electron gas AIGαA, ? It is possible to suppress the transition to the high voltage side, prevent the saturation current from decreasing on the high voltage side, and obtain a high output IEMT with a large power gain.

〔実施例〕〔Example〕

第1図に本発明の実施側の高出力用HEMTの要部断面
を示し、また、第2図にその組成図帽A5モル比)を示
している。第1図において、1は半絶縁性GaAs基板
、2はバッファ層、3は非ドープのA l z G (
11−jCA S VA、4はSiドープのA1.21
゜Ga1−、:A、層、5はスペーサ一層、6はチャネ
ル層の非トープのG a A s、7はSiドーブノA
e:tGa、+ −、xAs層、8はキャップ層のSi
ドープのGaAs hであり、9.10はソース及びド
レイン電極である。
FIG. 1 shows a cross section of a main part of a high-output HEMT according to the present invention, and FIG. 2 shows its composition (A5 molar ratio). In FIG. 1, 1 is a semi-insulating GaAs substrate, 2 is a buffer layer, and 3 is an undoped A l z G (
11-jCA S VA, 4 is Si-doped A1.21
゜Ga1-, : A, layer, 5 is a spacer layer, 6 is a non-tope Ga As of the channel layer, 7 is a Si dove layer A
e: tGa, + -, xAs layer, 8 is Si cap layer
Doped GaAs h, 9.10 are source and drain electrodes.

各層はMBE(分子線エピタキシャル成長法)またはM
OCVD (有機全屈を用いた気相成長法)で形成され
る。以下に一例として基板上にエピタキシャル成長され
た各層について詳しく示す。
Each layer is formed by MBE (Molecular Beam Epitaxial Growth) or M
It is formed by OCVD (organic vapor phase growth method). Each layer epitaxially grown on a substrate will be described in detail below as an example.

2:ハ・7フア一層、非ドープGaAs 、厚さ3oo
o、Z3:非ドープのAI:tGa1−xA’ Fi 
(x =0.3)、厚さ500A 4:n(不純物Si)型のAxxGα1−xA5N(x
−〇、3 ) 、厚さ100オ、キャリア濃度l×10
18m−3 5ニスペーサ一層、非ドープのA l xGa 1−x
As 層(X =0.3 )厚さ80A 6:チャネル層の非ドープのGaAs 、厚さ150 
Al:n(不純物Si)型のA l 3; G a 1
−3; A s−層(X =0.3 ) 、厚さ300
A、キャリア濃度1×101810l 8:キャンプ層のn (不純物Si)型のGaA s層
、厚さ600A BB、BA:障壁層、非ドープAlxGα1−3Ju 
(x>0.3 )またはAI!A、9、厚さ数十A(典
型的には20〜30A) 各層を形成した後、ソース、トレインの各電極9.10
を従来のプロセスによって形成する。
2: Single layer, undoped GaAs, thickness 3oo
o, Z3: undoped AI: tGa1-xA' Fi
(x = 0.3), thickness 500A 4:n (impurity Si) type AxxGα1-xA5N(x
-〇, 3), thickness 100 ohms, carrier concentration 1 x 10
18m-3 5 varnish spacer layer, undoped Al xGa 1-x
As layer (X = 0.3) thickness 80A 6: Channel layer undoped GaAs, thickness 150A
Al: n (impurity Si) type Al 3; Ga 1
-3; As-layer (X = 0.3), thickness 300
A, carrier concentration 1×101810l 8: camp layer n (impurity Si) type GaAs s layer, thickness 600A BB, BA: barrier layer, undoped AlxGα1-3Ju
(x>0.3) or AI! A, 9, several tens of amps thick (typically 20 to 30 amps) After forming each layer, source and train electrodes 9.10
formed by conventional processes.

以上の構成において、障壁層BA、BBは前記のように
キャリアがトンネルしない程度で薄く形成する必要があ
る。極く薄く形成した障壁層のルGaAsやAIA!は
結晶学的な問題がない。それは超格子でA IA s 
 / GaAsの結晶が良好に得られるのと同じ理由で
あり、ミスマツチによる歪を横方向に逃がす作用による
ものと考えられる。最もミスマツチが大きいAlAs 
/ GaAsの場合障壁層のAlAsの厚さとして20
〜50イが最適である。
In the above structure, the barrier layers BA and BB need to be formed thin enough to prevent carriers from tunneling, as described above. The barrier layer formed extremely thin is GaAs or AIA! has no crystallographic problems. It is a superlattice and A IA s
This is the same reason why GaAs crystals can be obtained in good condition, and is thought to be due to the effect of releasing strain caused by mismatch in the lateral direction. AlAs with the largest mismatch
/ In the case of GaAs, the thickness of AlAs in the barrier layer is 20
~50 i is optimal.

第3図に実施例の特性図を示してあり、図のように従来
の高出力用HEMTに比較して高電界側での飽和電流の
低下がずっと少なくなっている。
FIG. 3 shows a characteristic diagram of the embodiment, and as shown in the figure, the drop in saturation current on the high electric field side is much smaller than in the conventional high-output HEMT.

以上、GaAs / AlGaAs系のHE M Tに
ついて説明したが、本発明はこれに限ることがなく多く
の変形が可能であり、他のへテロ系例えばInGaA7
AIIrLAS等にも適用することができる。
Although the GaAs/AlGaAs-based HEMT has been described above, the present invention is not limited to this and can be modified in many ways.
It can also be applied to AIIrLAS and the like.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明の高出力用HEMTによれば、高
電圧下においても、2次元電子ガスのAIGaAEI9
への実空間遷移が抑えられるため飽和電流I〆55の低
下が少なく、高いパワーゲインが得られる利点がある。
As described above, according to the high-output HEMT of the present invention, even under high voltage, the two-dimensional electron gas AIGaAEI9
Since the real space transition to is suppressed, there is a small decrease in the saturation current I≆55, and there is an advantage that a high power gain can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の要部断面図、第2図は実施例
の断面組成図、第3図は実施例の特性図、第4図は従来
例の要部断面図、第5図は従来例の断面組成図、第6図
は従来例の特性図である。 1 ・= GaAS基板 2・・・バッファ一層 3 ・= AI GaAs H 4・・・n型F−プ層 5・・・スペーサ一層 6・・・チャネル層 7・・・n型(不純物Si)ドー7018・・・キャン
プ層 9.10・・・電極 BA、BB・・・障壁層 特許出願人   冨 士 通 株式会社代理人 弁理士
 玉 蟲 久 五 部 (外1名) 発明の実施例の断面組成図 第  2  図 VQ5 (V) 実施例の特性図 第6図 従来例の要部断面図 第  4  図
Fig. 1 is a sectional view of the main part of the embodiment of the present invention, Fig. 2 is a cross-sectional composition diagram of the embodiment, Fig. 3 is a characteristic diagram of the embodiment, Fig. 4 is a sectional view of the main part of the conventional example, and Fig. 5 is a sectional view of the main part of the embodiment of the present invention. The figure is a cross-sectional composition diagram of a conventional example, and FIG. 6 is a characteristic diagram of the conventional example. 1 ・= GaAS substrate 2 . . . Buffer single layer 3 ・= AI GaAs H 4 . . . N-type F-type layer 5 . . . Spacer single layer 6 . 7018...Camp layer 9.10...Electrode BA, BB...Barrier layer Patent applicant: Fuji Tsutsu Co., Ltd. Agent Patent attorney: Hisashi Tamamushi Gobu (1 other person) Cross-sectional composition of embodiments of the invention Figure 2 Characteristic diagram of VQ5 (V) Example Figure 6 Cross-sectional view of main parts of conventional example Figure 4

Claims (1)

【特許請求の範囲】 第1の半導体からなるチャネル層と、該チャネル層の両
側の第1の半導体より電子親和力が小さな第2の半導体
からなるキャリア供給層とが結晶学的に適合して備えら
れる電界効果型半導体装置において、 前記チャネル層の少なくとも基板側の第2の半導体層と
の界面に第2の半導体よりバンドギャップが大きな半導
体からなる障壁層を有することを特徴とする電界効果型
半導体装置。
[Claims] A channel layer made of a first semiconductor and a carrier supply layer made of a second semiconductor having a smaller electron affinity than the first semiconductor on both sides of the channel layer are crystallographically compatible. A field effect semiconductor device comprising: a barrier layer made of a semiconductor having a larger bandgap than the second semiconductor at an interface between the channel layer and the second semiconductor layer on at least the substrate side; Device.
JP27051085A 1985-11-30 1985-11-30 Field effect type semiconductor device Pending JPS62130565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27051085A JPS62130565A (en) 1985-11-30 1985-11-30 Field effect type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27051085A JPS62130565A (en) 1985-11-30 1985-11-30 Field effect type semiconductor device

Publications (1)

Publication Number Publication Date
JPS62130565A true JPS62130565A (en) 1987-06-12

Family

ID=17487246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27051085A Pending JPS62130565A (en) 1985-11-30 1985-11-30 Field effect type semiconductor device

Country Status (1)

Country Link
JP (1) JPS62130565A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522952A2 (en) * 1991-07-08 1993-01-13 France Telecom Field effect transistor with thin barrier layers and a thin doped layer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59968A (en) * 1982-06-25 1984-01-06 Fujitsu Ltd Semiconductor device
JPS6012775A (en) * 1983-07-02 1985-01-23 Agency Of Ind Science & Technol Field effect transistor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59968A (en) * 1982-06-25 1984-01-06 Fujitsu Ltd Semiconductor device
JPS6012775A (en) * 1983-07-02 1985-01-23 Agency Of Ind Science & Technol Field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0522952A2 (en) * 1991-07-08 1993-01-13 France Telecom Field effect transistor with thin barrier layers and a thin doped layer
FR2679071A1 (en) * 1991-07-08 1993-01-15 France Telecom FIELD EFFECT TRANSISTOR WITH THIN LAYERS OF CONTROLLED ENERGY BAND.

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