JPS61158183A - Electrical field effect type semiconductor device - Google Patents
Electrical field effect type semiconductor deviceInfo
- Publication number
- JPS61158183A JPS61158183A JP27991684A JP27991684A JPS61158183A JP S61158183 A JPS61158183 A JP S61158183A JP 27991684 A JP27991684 A JP 27991684A JP 27991684 A JP27991684 A JP 27991684A JP S61158183 A JPS61158183 A JP S61158183A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gaas layer
- doping
- gaas
- superlattice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000000694 effects Effects 0.000 title abstract description 10
- 230000005684 electric field Effects 0.000 title 1
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 230000005669 field effect Effects 0.000 claims description 2
- 239000004047 hole gas Substances 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 19
- 238000000034 method Methods 0.000 abstract description 7
- 125000005842 heteroatom Chemical group 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 3
- 229910018885 Pt—Au Inorganic materials 0.000 abstract 1
- 238000005275 alloying Methods 0.000 abstract 1
- 239000000969 carrier Substances 0.000 abstract 1
- 238000002109 crystal growth method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 206010027783 Moaning Diseases 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000005247 gettering Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000003446 memory effect Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
- H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、バンドギャップが相違する2種類の半導体を
接合することによって形成される接合の近傍に発生する
キャリア(担体)蓄積層におけるキャリア濃度を制御電
極に印加する電圧によシ変化させ、該電子蓄積層からな
る導電路のインピーダンスを制御する形式の電界効果型
半導体装置に係る。そして、特に、前記2種類の接合(
ヘテロ接合)の近傍のキャリア金、咳ヘテロ接合に臨接
して設は九超格子構造から供給する高電子或いは正孔移
動度トランジスタに関する。Detailed Description of the Invention [Field of Industrial Application] The present invention is directed to reducing carrier concentration in a carrier accumulation layer generated near a junction formed by joining two types of semiconductors with different band gaps. The present invention relates to a field-effect semiconductor device in which the impedance of a conductive path made of the electron storage layer is controlled by changing the impedance of the electron storage layer according to a voltage applied to a control electrode. In particular, the two types of bonding (
The carrier gold in the vicinity of the heterojunction is related to a high electron or hole mobility transistor supplied from a superlattice structure adjacent to the heterojunction.
従来、高電子移動度トランジスタの電子供給層としては
N AiGaAa k用いる方法と、5−G5Ag/
AILGaAa超格子を用いるものとが提案されて−る
。Conventionally, as an electron supply layer of a high electron mobility transistor, a method using NAiGaAak and a method using 5-G5Ag/
A method using an AILGaAa superlattice has been proposed.
第6図にそのn−GaAa/AItGaAa超格子2を
用いた従来例のバンド構造を示す。図にお−て、ノン・
ドープ或は%凰ドーグのGa1n /ii 1に超格子
2が隣接して設けられ、該超格子のGa As層に%麗
不純物1例えばS4がドープされ5−GaAa層5とな
されており、これよシワイドギャップな半導体のAXG
aAa 4 F1ノン・ドープとされている。超格子2
は、例えばzoJのs GaAa層5とzoJのBG
aAa層4As層互に形成され、全層厚が5001に形
成される。この構成において、超格子のコンダクシヨ/
・バンド5LCBよj) A7Dだけ下がりたレペルに
S−ドーグによるドナーレベルDLが生じる。FIG. 6 shows the band structure of a conventional example using the n-GaAa/AItGaAa superlattice 2. In the figure, non-
A superlattice 2 is provided adjacent to the Ga1n/ii 1 of the doped or %-Dawg, and the GaAs layer of the superlattice is doped with an impurity 1 such as S4 to form a 5-GaAa layer 5. AXG, a semiconductor with a wide gap
It is said that aAa 4 F1 is non-doped. super lattice 2
For example, the s GaAa layer 5 of zoJ and the BG of zoJ
The aAa layer and 4As layers are formed alternately, and the total layer thickness is 5001 mm. In this configuration, the superlattice conduction/
・Band 5LCB j) Donor level DL due to S-Dawg occurs at the level lowered by A7D.
該S(ドナーよシミ子が供給され、A10641層4と
GcbAa層1とのヘテロ接合近傍のGa Am層1に
2次元電子ガス(2DEG )層が形成される。該2D
EGの電子濃度n、 ’fcゲート金属3に与える電圧
によって制御することによりトランジスタ動作が可能と
なる。A two-dimensional electron gas (2DEG) layer is formed in the Ga Am layer 1 near the heterojunction between the A10641 layer 4 and the GcbAa layer 1.
Transistor operation is possible by controlling the electron concentration n, 'fc of EG by the voltage applied to the gate metal 3.
ところが、従来の素子においては、N−AXGaAaを
電子供給層に用いた場合、N−AJGaAa K特有な
欠陥の九めに、例えば液体窒素温度において、光照射の
影響が数千時間も残るなどの問題があシ(PPCper
sistent photo oosdsottvit
y持続的光照射効果と呼ぶ)、ま九、第6図の3−Ga
Aa/AAGαAs起格子においては20λ程度のGc
Lha層の1部に不純物をドーグするために、不純物プ
ロファイルの制御が難しいという欠点がおる。例えば第
5図のように、本来SiドープしたいGcb As層4
0の一部40’のみにドープできず、斜線部のAJ G
a As 50にもS(のドープのプロファイルがか\
ってしまうことがらる。すると、前述のN AflG
aAaの持続的光照射効果が生じることになる。However, in conventional devices, when N-AXGaAa is used for the electron supply layer, one of the defects peculiar to N-AJGaAa K is that the effects of light irradiation remain for several thousand hours at liquid nitrogen temperature. There is a problem (PPCper
sistent photo oosdsottvit
y), 3-Ga in Figure 6)
In the Aa/AAGαAs origin lattice, Gc of about 20λ
Since impurities are doped into a portion of the Lha layer, there is a drawback that it is difficult to control the impurity profile. For example, as shown in FIG.
It is not possible to dope only part 40' of 0, and the AJ G in the shaded area
a As 50 also has a doping profile of S (\
There are things that happen. Then, the aforementioned N AflG
A continuous light irradiation effect of aAa will occur.
さらに従来の問題点として、 2DEGd度n1が十
分に得られないという問題がら9、ガを増大する工夫が
種々研究されている。Furthermore, as a conventional problem, the problem of not being able to obtain a sufficient 2DEGd degree n19 has led to various studies on ways to increase the degree of 2DEGd.
本発明においては、高電子移動度トランジスタ或は高正
孔移動度トランジスタのキャリア(担体)供給層として
、所gjl APD (!tomie 21a%ay
d+pisy ) k用いる。APD (以下界面ドー
ピングという)は、MflE (分子線結晶成長)中に
、一時エピタキシャル成長を中断し、不純物のみをデポ
ジットする方法でろシ、制御性が良く、プロファイルコ
ントロールが容易でおる。In the present invention, as a carrier supply layer of a high electron mobility transistor or a high hole mobility transistor,
d+pisy) k is used. APD (hereinafter referred to as interface doping) is a method in which epitaxial growth is temporarily interrupted during MflE (molecular beam crystal growth) and only impurities are deposited, and it has good controllability and easy profile control.
すなわち、本発明は、半導体層と、該半導体層に格子整
合し、これよシもワイドギャップの半導体層とのヘテロ
接合近傍に形成される2次元電子ガス或いは29元正孔
ガスを用いる高電子或いは正孔移動度トランジスタにお
いて、チャネルとなる前記ヘテロ接合に隣接して、超格
子が備えられ、該超格子のヘテロ接合界面にドナー成り
はアクセプタ不純物がドーグされ、該ドナー成いはアク
セプタ不純物から担体を供給するようにする。That is, the present invention provides a high-electron generation method using a two-dimensional electron gas or a Alternatively, in a hole mobility transistor, a superlattice is provided adjacent to the heterojunction serving as a channel, and an acceptor impurity is doped at the heterojunction interface of the superlattice, and the donor is doped from the acceptor impurity. Make sure to supply the carrier.
第4図に示すように本発明によれば、Si等の不純物を
0648層40とAAGtsAa /i田等のヘテロ界
面にドーピングすることができる。その結果次のような
作用が得られる。As shown in FIG. 4, according to the present invention, impurities such as Si can be doped into the hetero interface between the 0648 layer 40 and the AAGtsAa/i field. As a result, the following effects are obtained.
■ 従来のN−AAGaAaを電子供給層とする場合と
異なシAXGaAa層等の電子供給層ににドープされな
いので前記rpc (光照射のメモリ効果)が° 少
なくなる。(2) Unlike the conventional case where N-AAGaAa is used as an electron supply layer, the electron supply layer such as the AXGaAa layer is not doped, so the RPC (memory effect of light irradiation) is reduced.
■ 2次元電子ガス或いは2次元正孔ガス濃度が増大す
る。その理由を以下に述べる。(2) The two-dimensional electron gas or two-dimensional hole gas concentration increases. The reason for this is explained below.
一般に高電子移動度トランジスタ(HEMT)において
、不純物のレベルが浅くなるとキャリア濃度が増大する
ことは良く仰られている。It is generally said that in a high electron mobility transistor (HEMT), the carrier concentration increases as the impurity level becomes shallower.
(ス、lコ ^I Ga 入S)
第1図にGa Am/%/AIGaAa Ei扁4を備
える本発明例のバンド構造が示されておシ、これを用い
て本作用を説明する。図において、GaAs層11とG
aAs/%/Ai、Aa超格子層12の間にヘテロ接合
が形成され、該接合近傍に2 DEG蓄積層が形成され
ている。(S, lco ^I Ga S) Fig. 1 shows a band structure of an example of the present invention comprising Ga Am/%/AIGaAa Ei flat 4, and the present action will be explained using this. In the figure, a GaAs layer 11 and a G
A heterojunction is formed between the aAs/%/Ai and Aa superlattice layers 12, and a 2 DEG accumulation layer is formed near the junction.
該2DEG蓄積層の電子濃度はゲート金属13に印加さ
れる電圧で制御され、トランジスタ動作せしめる。The electron concentration of the 2DEG storage layer is controlled by the voltage applied to the gate metal 13 to operate the transistor.
超格子1i112はAJIAa層14とGa As層1
5が交互に形成され、界面にS(がドーグされている。The superlattice 1i112 has the AJIAa layer 14 and the GaAs layer 1
5 are formed alternately, and S( is doped) at the interface.
超格子層には超格子のコンダクシ冒ンバンド5LCBカ
存在し、 5LCBからED下がったレベルにS(のド
ナーレベルDL1がろる。これに対してDL2と図示さ
れているのが、従来法によυGa As層15だけにS
(ヲドーグした場合のドナーレベルでらる。図から明ら
かなように、界面ドーピングのDLlの方がDL2よシ
レベルが浅くなっている。したがって、上述のドナーレ
ベルとキャリア濃度の関係から、QDEG層の電子密度
は本発明において増大することになる。In the superlattice layer, there is a superlattice conduction-prone band 5LCB, and the donor level DL1 of S (decreased to a level ED lower than 5LCB) is shown as DL2. υGa S only in As layer 15
(This is the donor level when dogged. As is clear from the figure, the interface doped DL1 has a shallower level than DL2. Therefore, from the above relationship between the donor level and carrier concentration, the QDEG layer Electron density will be increased in the present invention.
この界面ドーピングとドナーの深さの関係は、文献G、
Ba5tard Phys Etv、 E24 No
8 (1981ンP4714に記載されておシ、第5
図に示すように、景子井戸の幅りを横軸にドナーの深さ
Ev fc縦軸にとったとき%量子井戸の幅が軸におい
て■の界面ドーピングの場合Eo =”” + ■の中
央ドーピングの場合EDmR,でアク、常に■の界面ド
ーピングの方が■の中央ドーピングよりドナーの深さE
Dが浅くなりている。なお、Roは約6mmVでらる。The relationship between this interfacial doping and donor depth can be found in Document G.
Ba5tard Phys Etv, E24 No.
8 (Listed in 1981 P4714, No. 5
As shown in the figure, when the width of the Keiko well is plotted on the horizontal axis and the depth of the donor Ev fc is plotted on the vertical axis, the width of the quantum well is plotted on the axis, and in the case of interface doping of ■, Eo = “” + central doping of ■. In the case of EDmR, the interfacial doping of ■ is always better than the central doping of ■.
D is shallow. Note that Ro is approximately 6 mmV.
第2図に本発明の一実施例のHEMTの断面要部を示し
ておシ、次の各部よシ構成されている。FIG. 2 shows a cross-sectional main part of a HEMT according to an embodiment of the present invention, and is composed of the following parts.
各層に通常のHEMTと同様にMBE法によシ半絶縁性
Ga Aa基板10の上に連続して形成される。Each layer is successively formed on a semi-insulating GaAa substrate 10 by the MBE method as in a normal HEMT.
11・・・ノ/・ドープ(高純度)GaAs層、厚さ6
000λ12°” Ga As/%/Aid 、46
超格子層、全層厚500Xこの超格子層12μ、第1図
のGa As/s/AJ! Aaに相当する。その細部
構成は次のとおシである。11... Doped (high purity) GaAs layer, thickness 6
000λ12°”GaAs/%/Aid, 46
Superlattice layer, total layer thickness 500X, this superlattice layer 12μ, Ga As/s/AJ in Figure 1! Corresponds to Aa. Its detailed structure is as follows.
14・・・GaAs層、ノン・ドープ、厚さ20λ15
・・・AI−Am層、ノン・ドープ、厚さzoJここで
、Ga As層14とAgAs層15のヘテロ界面には
前述のアトミック・ブレーナ・ドーピング(APD)に
よp、stのドーピングを行う。それには、 GaA
aとAlAmの界面において、成長を一旦中断し、 G
Gビームをオフとし、A1ビームのみオ/C’)i’l
、Stのビームを照射し、S(のドーピングのみを行な
う。ここでA1ビーム照射を続けるのは、GaAaのA
#の解離を防止する九めである。具体例を示すと、Ga
Aafi−成長しなからドーピングすると仮定したとき
、 I X 10” em−”のドーピング相当のS
イヒームt−18秒照射する。これによj5.6X1u
”01%−2のSt面密度を得る。なお、APDについ
ては文献J、 Appl、 Phya、 51(1)
、 pp、 583〜387 (1980,1)に詳記
されている。14...GaAs layer, non-doped, thickness 20λ15
...AI-Am layer, non-doped, thickness zoJ Here, the hetero interface between the GaAs layer 14 and the AgAs layer 15 is doped with p and st by the above-mentioned atomic brainer doping (APD). . For that, GaA
Growth is temporarily interrupted at the interface between a and AlAm, and G
Turn off the G beam and turn on only the A1 beam/C')i'l
, St beam is irradiated to perform only S (doping).Here, the A1 beam irradiation is continued because of the A
This is the ninth step to prevent the dissociation of #. To give a specific example, Ga
Aafi - assuming doping before growth, S equivalent to doping of I x 10"em-"
Iheem t-irradiate for 18 seconds. This j5.6X1u
Obtains a St surface density of 01%-2.For APD, see Reference J, Appl, Phya, 51(1).
, pp. 583-387 (1980, 1).
さらに、第2図において、21はコンタクトのための1
0641層で厚さ300Xに形成され、22,245は
ソース及びドレイン電極で6 ’) 、A%GJA鴬き
アコイして形成しておシ、ゲート金属13はAJLまた
F2T (−P t −Asで形成する。Furthermore, in FIG. 2, 21 is 1 for contact.
The 0641 layer is formed to a thickness of 300X, 22 and 245 are source and drain electrodes, which are formed by A%GJA and A%GJA, and the gate metal 13 is formed by AJL or F2T (-P t -As to form.
本実施例による2DEG濃度の増加を比較例とともに以
下に示す。The increase in 2DEG concentration according to this example is shown below along with a comparative example.
通常のHEMT (N −Aft GaAa ) −*
ng 〜6 X 10” cm−”超格子n −Ga
AJAJ−A #をキャリア供給層とするHEMT
呻ng 〜8 X 10 etn″′
5本発明の実施例 =ζ〜?X10 a濯−5
以上%世不純物の界面ドーピングによる実施例によシ説
明したが、p型不純物の界面ドーピングによシ、高正孔
移動度トラ/ジスタが形成できることは明らかでおろう
。Normal HEMT (N-Aft GaAa) -*
ng ~6 X 10"cm-" superlattice n-Ga
AJAJ-A HEMT with # as carrier supply layer
Moaning 〜8 X 10 etn″′
5 Examples of the present invention =ζ~? X10 a wash-5
Although the embodiments using interfacial doping with p-type impurities have been described above, it is clear that a high hole mobility transistor/distor can be formed by interfacial doping with p-type impurities.
本発明によれば次のような効果が得られる。 According to the present invention, the following effects can be obtained.
■ N Aid−GaAa t−電子供給層とするHE
MTに比べてμGαA#或いはAJilAgに34 f
ドーグしない為に低温における持続的光照射効果が少な
くなる。■ N Aid-GaAa t- HE used as electron supply layer
34 f for μGαA# or AJilAg compared to MT.
Since there is no douging, the effect of continuous light irradiation at low temperatures is reduced.
■ s −G6 Aa/AJ Am超格子を電子供給層
とするRENTに比べると、St等の不純物のドーピン
グ・プロファイルの制御性が高い(ヘテロ界面に不純物
をゲッターする効果があるため、バルク結晶にドープす
るよシ界面ドーピングの方が制御性が良い。)利点がら
る。■ Compared to RENT, which uses the s-G6 Aa/AJ Am superlattice as the electron supply layer, the doping profile of impurities such as St is more controllable (because it has the effect of gettering impurities at the hetero interface, it Compared to doping, interfacial doping has better controllability.) There are advantages.
■ Ga Am/A11.As等の超格子において、G
aA−中のSt等の不純物のレベルよシもヘテロ界面の
不純物のレベルの方が浅いため、同じドープ景ではチャ
ネルの2次元電子ガスの濃度ガが高くなる利点がある。■ Ga Am/A11. In a superlattice such as As, G
Since the level of impurities such as St in aA- is shallower at the hetero interface, there is an advantage that the concentration of two-dimensional electron gas in the channel becomes higher in the same doping pattern.
第1図は本発明の実施例の素子のバンド構造を示す図、
第2図は本発明の実施例の素子の断面図、第3図及び第
4図にそれぞれn−GaAs/AAGaAa及びGaA
g/%/All Ga Asのバンド構造による説明図
、第5図はヘテロ界面ドーピングと中央ドーピングのド
ナーレベルの深さを示す図、第6図は従来の5GaAs
/AJIGaAa超格子を用いたHH:MTのバンド構
造を示す図。
10・・・半絶縁性GaAa基板
11・・・Ga As層
12・・・(σαA8/%/Ai、Az)超格子層13
・・・ゲート金属
14・・・(超格子の)試A1層
15−(超格子の) GaAa N
21− RGaAs層
22・・・ソース電極
25・・・ドレイン電極
第 1 図
GaAs/’n z′ALAs s格+rl
GaAs J”12 11
τ
第2図
第3 図 第 4 口
笛 5 図
第 6 図FIG. 1 is a diagram showing the band structure of an element according to an embodiment of the present invention;
FIG. 2 is a sectional view of a device according to an embodiment of the present invention, and FIGS. 3 and 4 show n-GaAs/AAGaAa and GaA
An explanatory diagram of the band structure of g/%/All GaAs. Figure 5 is a diagram showing the depth of the donor level of heterointerface doping and central doping. Figure 6 is a diagram of conventional 5GaAs.
/AJI A diagram showing the band structure of HH:MT using the GaAa superlattice. 10...Semi-insulating GaAa substrate 11...GaAs layer 12...(σαA8/%/Ai, Az) superlattice layer 13
... Gate metal 14 ... (superlattice) sample A1 layer 15 - (superlattice) GaAa N 21 - RGaAs layer 22 ... Source electrode 25 ... Drain electrode 1st Figure GaAs/'nz 'ALAs s case + rl
GaAs J”12 11 τ Fig. 2 Fig. 3 Fig. 4 Whistle 5 Fig. 6
Claims (1)
ギャップの半導体層とのヘテロ接合近傍に形成される2
次元電子ガス或いは2次元正孔ガスを用いる高電子或い
は正孔移動度トランジスタにおいて、チャネルとなる前
記ヘテロ接合に隣接して、超格子が備えられ、該超格子
のヘテロ接合界面にドナー或いはアクセプタ不純物がド
ープされ、該ドナー或いはアクセプタ不純物から担体を
供給することを特徴とする電界効果型半導体装置。2 formed near a heterojunction between a semiconductor layer and a semiconductor layer that is lattice matched to the semiconductor layer and has a wider gap than the semiconductor layer.
In a high electron or hole mobility transistor using a dimensional electron gas or a two-dimensional hole gas, a superlattice is provided adjacent to the heterojunction serving as a channel, and a donor or acceptor impurity is provided at the heterojunction interface of the superlattice. 1. A field effect semiconductor device, characterized in that the device is doped with impurities, and a carrier is supplied from the donor or acceptor impurity.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27991684A JPS61158183A (en) | 1984-12-29 | 1984-12-29 | Electrical field effect type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP27991684A JPS61158183A (en) | 1984-12-29 | 1984-12-29 | Electrical field effect type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61158183A true JPS61158183A (en) | 1986-07-17 |
Family
ID=17617696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP27991684A Pending JPS61158183A (en) | 1984-12-29 | 1984-12-29 | Electrical field effect type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61158183A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6414971A (en) * | 1987-07-09 | 1989-01-19 | Agency Ind Science Techn | Heterojunction field-effect transistor |
JPH01166568A (en) * | 1987-12-23 | 1989-06-30 | Hitachi Ltd | Semiconductor device |
JPH01183163A (en) * | 1988-01-18 | 1989-07-20 | Fujitsu Ltd | High electron mobility field effect transistor |
US5091759A (en) * | 1989-10-30 | 1992-02-25 | Texas Instruments Incorporated | Heterostructure field effect transistor |
US5196359A (en) * | 1988-06-30 | 1993-03-23 | Texas Instruments Incorporated | Method of forming heterostructure field effect transistor |
JP2005302861A (en) * | 2004-04-08 | 2005-10-27 | Matsushita Electric Ind Co Ltd | Semiconductor device using group iii-v nitride semiconductor |
-
1984
- 1984-12-29 JP JP27991684A patent/JPS61158183A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6414971A (en) * | 1987-07-09 | 1989-01-19 | Agency Ind Science Techn | Heterojunction field-effect transistor |
JPH01166568A (en) * | 1987-12-23 | 1989-06-30 | Hitachi Ltd | Semiconductor device |
JPH01183163A (en) * | 1988-01-18 | 1989-07-20 | Fujitsu Ltd | High electron mobility field effect transistor |
US5196359A (en) * | 1988-06-30 | 1993-03-23 | Texas Instruments Incorporated | Method of forming heterostructure field effect transistor |
US5091759A (en) * | 1989-10-30 | 1992-02-25 | Texas Instruments Incorporated | Heterostructure field effect transistor |
JP2005302861A (en) * | 2004-04-08 | 2005-10-27 | Matsushita Electric Ind Co Ltd | Semiconductor device using group iii-v nitride semiconductor |
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