JPS60167475A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60167475A JPS60167475A JP59021766A JP2176684A JPS60167475A JP S60167475 A JPS60167475 A JP S60167475A JP 59021766 A JP59021766 A JP 59021766A JP 2176684 A JP2176684 A JP 2176684A JP S60167475 A JPS60167475 A JP S60167475A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- hetero junction
- mixed crystal
- fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 239000013078 crystal Substances 0.000 claims abstract description 12
- 239000012535 impurity Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 abstract description 9
- 125000005842 heteroatom Chemical group 0.000 abstract 4
- 239000000969 carrier Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000283984 Rodentia Species 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
直
本発明は、超高源の選択ドープヘテロ接合型ＦＥＴ （
電界効果トランジスタ）に係り、特に、高集積に好適な
トランジスタ構造に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an ultra-high source selectively doped heterojunction FET (
The present invention relates to field effect transistors (field effect transistors), and particularly to transistor structures suitable for high integration.
（１）
従来の選択ドープヘテロ接合型ＦＥＴ （例えば特開昭
５６−９４７７９ ）のエネルギーバンド図〔第１図〕
と、エンハンスメント型Ｆ Ｅ Ｔ （Ｅ−ＦＥＴ）と
デプレション型Ｆ Ｅ Ｔ （Ｄ−ＦＥＴ）の断面図を
第２図に示す。従来作成している例では、１１はアンド
ープＧ ａΔ８，１２はｎ型へＱ Ｘ Ｇ ａ、−、Ａ
ｓ層であった。１３．１３’はゲート電極、１７はｎ
型Ｇ ａ Ａ ｓ層、１９がソース・ドレイン電極、１
６がイオン化した不純物Ｅトはフェルミレベル、ＥＤは
Ａ Ｑ ｘＧ ａｌ−、Ａ ｓの伝導帯の１と不純物準
位とのエネルギー間隔を各々示す。１５は２次元状電子
ガス層である。(1) Energy band diagram of a conventional selectively doped heterojunction FET (for example, Japanese Patent Application Laid-Open No. 56-94779) [Fig. 1]
FIG. 2 shows cross-sectional views of an enhancement type FET (E-FET) and a depletion type FET (D-FET). In the conventional example, 11 is undoped Ga Δ8, 12 is n-type Q
It was the s layer. 13.13' is the gate electrode, 17 is n
type GaAs layer, 19 is source/drain electrode, 1
6 is the ionized impurity Et, and ED is the Fermi level, and ED is the energy interval between the conduction band 1 and the impurity level of AQxGal- and As, respectively. 15 is a two-dimensional electron gas layer.
従来のこのＦＥＴにおいては、Ａ Ｑ ｘ ＧａトｘＡ
ｓとＧ ａ Ａ ｓとの格子マツチングを良くする（
Ｘを小さくする）ことと二次元状担体１５をより効果的
にヘテロ界面に蓄積される（Ｘを大きくする）ことの相
矛盾する要請のためにＡＱの混晶化Ｘとには０．３前後
にとるのが通例であった。In this conventional FET, A Q x Ga x A
Improve the lattice matching between s and G a A s (
Due to the contradictory demands of (reducing It was customary to take it before and after.
ところが、不純物レベルＥｔ）はＡＱの混晶化Ｘに大き
く依存することが実験によって確認されて（２）
いる（例えばＳｉについては、Ｊ、Ｊ、Ａ、Ｐ、旦（１
９８２）Ｌ６７５− Ｌ６７６ 、 Ｔｅについては１
１．ｃ、ｃａｓｅｙ、Ｍ、Ｂ、Ｐａｎ１ｓ“Ｈｅｔｅｒ
ｏｓｔｒｕｃｔｕｒｅ Ｌａ５ｅｒｓ”Ａｃａｄｅｍｉ
ｃ Ｐｒｅａｓ １９７８ＰＡＲＴ Ａ Ｐ２Ｏ０を参
照）。However, it has been experimentally confirmed (2) that the impurity level Et) greatly depends on the mixed crystallization X of AQ (for example, for Si, J, J, A, P, Dan(1
982) L675- L676, 1 for Te
1. c, casey, M, B, Pan1s “Heter
structure La5ers”Academi
c Preas 1978 PART A P2O0).
一方、このＦ Ｅ Ｔは、Ａ Ｑ Ｘ Ｇａ、−、Ａ
ｓ層１２の膜厚ｄが５００人程度で不純物濃度Ｎ０とし
ては１０”ｃｍ−’ をとるのが普通である。On the other hand, this F ET is A Q
It is normal that the film thickness d of the S layer 12 is about 500 and the impurity concentration N0 is 10"cm-'.
ｑとすると という形がしきい値電圧ｖ０の中にあられれてくる。If q This form appears in the threshold voltage v0.
事情はＧａＡｓＭＥＳＦＥＴでも同様で、ｄとして能導
層厚とするば、Ｎ、〜１０ｃｍ−３程度ｄ〜１０００人
である。The situation is similar for GaAs MESFETs, where d is the thickness of the conductive layer, N is about 10 cm -3 and d is about 1000.
閾値電圧ｖＴが（１）式にあられれる量は選択ドープＦ
ＥＴの場合がＧａＡｓＭＥＳＦＥＴに比べ２，５倍大き
い値となる。このことは大略、ＧａＡｓＭ［ＥＳＦＨＴ
に比（３）
べて閾値制御がＧａＡｓＭＥＳＦＥＴに比べ２．５倍も
難かしいことを意味している。The amount by which the threshold voltage vT can be expressed in equation (1) is the selective doping F.
The value for ET is 2.5 times larger than that for GaAs MESFET. This roughly means that GaAsM[ESFHT
Compared to (3), this means that threshold control is 2.5 times more difficult than in GaAs MESFETs.
本発明の目的は、選択ドープヘテロ接合型ＦＥＴにおい
て、閾値制御が容易で、エンハンスメント型ＦＥＴとデ
プレション型ＦＥＴを同一基板内に作成するのに好適な
構造をもつ選択ドープヘテロ接合型ＦＥＴを提供するこ
とにある。An object of the present invention is to provide a selectively doped heterojunction FET that allows easy threshold control and has a structure suitable for manufacturing an enhancement type FET and a depletion type FET in the same substrate. It is in.
発明者たちは、ヘテロ接合界面に蓄積する電子シート濃
度ｎｓと不純物準位ＥＤ、閾値電圧ｖ０の間の関係を研
究しているうちに次の様な事実を見出した。The inventors discovered the following fact while studying the relationship between the electron sheet concentration ns accumulated at the heterojunction interface, the impurity level ED, and the threshold voltage v0.
価電子帯から測ったフェルミレベルをＥＦ、不純物レベ
ルをＥＶＤとし、統計力学の要請により電気的に活性に
なりうるｎ型不純物の数をＮｏ、イオン化した不純物の
数をＮＤ十とすると（４）
でＴは電子温度である。Let EF be the Fermi level measured from the valence band, EVD be the impurity level, No be the number of n-type impurities that can become electrically active as required by statistical mechanics, and let ND0 be the number of ionized impurities (4) where T is the electron temperature.
ところで簡単な逆考察から闇値電圧■３．に関与するの
はＮＤ十ではなくＮｏであることがわかる。By the way, from a simple inverse consideration, the dark value voltage ■3. It can be seen that it is No that is involved in this, not ND ten.
一方、ヘテロ接合界面に蓄積する電子シート濃度ｎ６は
ただし、
ｈ：ボルツマン常数
Ｔ：絶対温度
ΔＥ ｇ ： Ａ Ｑ Ｇ ａ Ａ ｓとＧａＡのエネ
ルギーギャップの差
（Ｎａ Ｎｖ ）ＧａＡｓ ： ＧａＡａの電子有効状
態密度と正孔有効状態密度
（Ｎｃ Ｎｖ ）ＡＱＧａＡｇ ： Ａ Ｑ Ｇ ａ
Ａ ｓの電子有効状態密度と正孔有効状態密度
（５）
として与えられ、Ｎ、十の関ηである。On the other hand, the electron sheet concentration n6 accumulated at the heterojunction interface is: h: Boltzmann constant T: absolute temperature ΔE g: A Q Ga A Difference in energy gap between s and GaA (Na Nv) GaAs: Electronic effective state of GaAa Density and hole effective state density (Nc Nv) AQGaAg: A Q Ga
It is given as the electron effective state density and hole effective state density of A s (5), and is a function η of N and 10.
即ち、不純物準位Ｅｖが小さいなど、同一のＮｏに対し
多くの電子を蓄積できることを見出した。That is, it has been found that many electrons can be accumulated for the same No because the impurity level Ev is small.
従来技術のところで示した様にｎ型ドーパントとしては
、Ｓ ｔ 、 Ｔ ａを用いるのが通例で、その場合、
ＥＤはＡＭの混晶比Ｘに大きく依存していることが知ら
れていた。即ち、
である。〔たとえばＪ 、 Ｊ 、 Ａ 、 Ｐ、旦（
１９８２）Ｌ６７５−Ｌ６７６）今までの議論から、同
一のＮＤ、即ち、同一のｖＴｂに対して有効にμ６を増
やすには、ＡΩのｍｏｌｒ ｆｒａｃｔｉｏｎ ｘを小
さくする方が良いことになる。As shown in the prior art section, it is customary to use S t and Ta as n-type dopants, in which case,
It was known that ED largely depends on the mixed crystal ratio X of AM. That is, [For example, J, J, A, P, Dan (
1982) L675-L676) From the discussion up to now, in order to effectively increase μ6 for the same ND, that is, the same vTb, it is better to reduce the molr fraction x of AΩ.
しかし今までの議論ではへテロ接合界面での伝導帯のエ
ネルギーの″とびΔＥｃの大きさを無視していた。ΔＥ
Ｃは大きいほど良いので、この場合は＾Ｑ ｍｏｌｅ
ｆｒａｃｔｉｏｎ ｘが大きい方がよいことになる。However, the discussion up to now has ignored the magnitude of the conduction band energy jump ΔEc at the heterojunction interface.ΔE
The larger C is, the better, so in this case ^Q mole
It follows that the larger the fraction x, the better.
（６）
つまり、以上をまとめると同一の■Ｔｂを与えたときに
は、ヘテロ接合型面ではΔＥａの大きいノンドープＡ
Ｑ ｘ Ｇ ａ、、、ｘＡ ｓ層を用い、界面から離れ
たところではＡＱの混晶比の小さいｎ型Ａ Ｉ２ ｘ
Ｇ ｓ １−、 Ａ ｓ層を形成してＦＥＴを作ると最
もよいＦＥＴができることになる。(6) In other words, to summarize the above, when the same ■Tb is given, non-doped A with a large ΔEa on the heterojunction type surface
Using Q
The best FET can be produced by forming G s 1- and As layers.
即ち、本発明は上記の構造のへテロ接合を用いて選択ド
ープヘテロ接合型ＦＥＴを設計すると、同一の閾値電圧
を与えたときに最大の電流をとることができる。That is, in the present invention, if a selectively doped heterojunction FET is designed using a heterojunction having the above structure, the maximum current can be obtained when the same threshold voltage is applied.
別の言い方をすれば、同一の電流をとるには少ない量の
不純物１ニーピングで良いために、閾値制御がＧｕＡｓ
肚Ｓ Ｆ Ｌｊ Ｔ端間程度にまでなる。In other words, threshold control is better with GuAs because it only takes one kneading of a small amount of impurity to obtain the same current.
Approximately between the T edges.
本発明の半導体装置の断面図を第３図（ａ）に示す。１
０は半絶縁性Ｇ ａ Ａ ｓ基板又はＰ型ＧａＡｓ基板
、１１はアンドープＧ ａ Ａ ｓ層、１２′はＡＱの
混晶比Ｘで０．２５≦Ｘ≦０．４の範囲のノンドープＡ
ＱＸＧａ１−ｘＡｓ層、２２はＡＱの混晶比Ｘが０．０
５≦Ｘ≦０．２の範囲のｎ型ＡＱ３Ｇａａ−８Ａｓ層、
１９はソース・ドレイン電極、（７）
１３はゲート電極。第１３（ｂ）は、断面Ａ−ＢでのＡ
Ｑの混晶比の範囲を示すグラフである。A cross-sectional view of the semiconductor device of the present invention is shown in FIG. 3(a). 1
0 is a semi-insulating GaAs substrate or a P-type GaAs substrate, 11 is an undoped GaAs layer, and 12' is a non-doped A with a mixed crystal ratio X of AQ in the range of 0.25≦X≦0.4.
QXGa1-xAs layer, 22 has AQ mixed crystal ratio X of 0.0
n-type AQ3Gaa-8As layer in the range of 5≦X≦0.2,
19 is a source/drain electrode, (7) 13 is a gate electrode. 13(b) is A at cross section A-B.
It is a graph showing the range of the mixed crystal ratio of Q.
以下本発明を実施例を用いて要に詳しく説明する。 The present invention will be explained in detail below using examples.
実施例１
半絶縁性Ｇ ａ Ａ ｓ基板１０上に、分子線エピタキ
シー法（ＭＢＥ）を用いて、不純物を故意にはドープし
ない高純度Ｇ ａ Ａ ｓ層１１を約１μｍ。Example 1 On a semi-insulating GaAs substrate 10, a high purity GaAs layer 11 which is not intentionally doped with impurities is formed to a thickness of approximately 1 μm using molecular beam epitaxy (MBE).
同じく不純物を故意にはドープしないＡＱｘＧａ、、Ａ
ｓｓ層２’ （ｘ〜０．３）を６０人成長させた。通常
このＡ Ｑ ｘ Ｇ ａｔ−、Ａ ｓ層１２′は、Ａ
Ｄ、の混合比ヲ０．２８≦Ｘ≦０．４０の範囲で用いる
。次にＡＱの混晶比を０．２２にしたＡＱｘ Ｇ ａｌ
−ｘＡ ｓ層２２をＩ８
４００人成長させ、このときＳｉ原子を１×１０ｃｍ
”’ ”の濃度でドープした。次に、Ｇ ａ Ａ ｓ層
１７を２００人成長させ、このときＳｉ原子をＩＸｌｏ
ｃｍ−’の濃度でドープした（第４図（、）。Similarly, AQxGa, which is not intentionally doped with impurities, A
Sixty ss layer 2' (x~0.3) were grown. Usually, this A Q x G at-, A s layer 12' is
The mixing ratio of D is used within the range of 0.28≦X≦0.40. Next, AQx Gal with the mixed crystal ratio of AQ set to 0.22
-xA s layer 22 is grown by I8 400 people, and at this time, Si atoms are grown to 1×10 cm.
It was doped at a concentration of ``'''. Next, 200 Ga As layers 17 are grown, and at this time, Si atoms are
cm-' concentration (Fig. 4(a)).
このｎ型Ｇ ａ Ａ ｓ層の不純物濃度は、あまり高く
すると、ショットキーゲート電極の順方向バリア（８）
を小さくし、逆耐圧を小さくするという効果をも極を形
成するときに、イオン注入法等でｎ＋層を形成する必要
がある。If the impurity concentration of this n-type GaAs layer is too high, it will reduce the forward barrier (8) of the Schottky gate electrode and reduce the reverse breakdown voltage. It is necessary to form an n+ layer by a method or the like.
結晶成長をした後、通常の工程と同じく、フォトリソグ
ラフィーと、リフトオフ法を用いて、ソース・ドレイン
電極１９、ゲート電極１３．１３’を形成した。After crystal growth, source/drain electrodes 19 and gate electrodes 13 and 13' were formed using photolithography and a lift-off method as in the usual process.
ただし、ゲート電極１３′を形成するときには、ＣＣΩ
ＲＦ２とＨｅの混合ガスを用いてＧ ａ Ａ ｓ層１７
を選択的にエツチングをした後、ゲート電極１３′を形
成した（第４図（ｂ））。ＦＥＴ動作の面では、１３′
をゲートにもつＦＥＴはエンハンスメント型ＦＥＴであ
り、ゲート電極１３の部分は、デプリション型ＦＥＴで
ある。However, when forming the gate electrode 13', CCΩ
G a As layer 17 using a mixed gas of RF2 and He
After selectively etching, a gate electrode 13' was formed (FIG. 4(b)). In terms of FET operation, 13'
The FET having the gate electrode 13 is an enhancement type FET, and the gate electrode 13 is a depletion type FET.
ゲート電極としてはＴ ｉ ／ Ｐ ｔ ／ Ａ ｕを
用い、ソース・ドレイン電極とにはＡ ｕ Ｇ ａ ／
Ｎ ｉ ／Ａｕを用いた。Ti/Pt/Au is used as the gate electrode, and AuGa/Au is used as the source/drain electrode.
N i /Au was used.
本実施例では、ｎ型Ａ Ｑ ｘ Ｇａ、−、Ａｓ （ｘ
−０，２２）（９）
層のＡ Ｑ ｍｏｌｅ ｆｒａｃｔｉｏｎ ｘ として
は、Ｓｉドープした場合には０．０５≦Ｘ≦０．２５程
度の範囲で用いている。In this example, n-type A Q x Ga, -, As (x
-0,22)(9) The A Q mole fraction x of the layer is used in the range of about 0.05≦X≦0.25 when Si-doped.
閾値制御だけから考えるどＡＱ混晶比Ｘの小さいｎ型Ａ
Ｑ Ｘ Ｇ ａｓ−、Ａｓ層の代りにｎ型Ｇ ａ Ａ
ｓ層の方が有利である。しかしこの構造では、同一基
板内にＥ型とＤ型を構成することが難かしいという欠点
を有している。即ち、本実施例の様にｎ−ＧａＡｓ／ｎ
−ＡＱＸＧａｌ−、Ａｓのへテロ接合を利用した選択エ
ツチングを利用できるという利点がある。Considering only from threshold control, n-type A with small AQ mixed crystal ratio X
Q X G as-, n-type Ga A instead of As layer
The s-layer is more advantageous. However, this structure has the drawback that it is difficult to construct E-type and D-type in the same substrate. That is, as in this example, n-GaAs/n
-AQXGal-, has the advantage of being able to utilize selective etching using a heterojunction of As.
本発明ま効果をまとめると次の様になる。 The effects of the present invention can be summarized as follows.
（１）アンドープＧａＡｓ層と直接へテロ接合を形成す
るアンドープＡＵｘＧａ Ａｓ層ではＡＱ−ｘ
ｍｏｌｅ ｆａｃｔｉｏｎ ｘを０．２８≦Ｘ≦０．４
０程度にしたことにより、両者の伝導帯のエネルギー差
ΔＥｃを大きくすることができ、ヘテロ接合界面に多数
の電子を閉じこめることができる。(1) In the undoped AUxGaAs layer that forms a direct heterojunction with the undoped GaAs layer, AQ-x mole fraction x is 0.28≦X≦0.4.
By setting it to about 0, the energy difference ΔEc between the two conduction bands can be increased, and a large number of electrons can be confined at the heterojunction interface.
（２）ｎ型Ａ Ｑ Ｘ Ｇ ａｌ−、Ａ ｓ層のＡ Ｑ
ｍｏｌ、ｅ（１０）
ｆｒａｃｔｉｏｎ ｘでは、ドナーレベルの浅くなる０
、０５≦Ｘ≦０．２５の値を選んだことによりｎ型にド
ープする不純物濃度を大となすことができ、このＡ Ｑ
Ｇ ａ Ａ ｓ層の膜厚制御性が容易になる。その結
果として閾値電圧■７．の制御性が改善された。(2) n-type AQXGal-, AQ of As layer
mol, e(10) At fraction x, the donor level becomes shallower at 0
, by selecting the value of 05≦X≦0.25, it is possible to increase the impurity concentration for n-type doping, and this A Q
The film thickness of the GaAs layer can be easily controlled. As a result, the threshold voltage ■7. Improved controllability.
第１図は従来の選択ドープヘテロ接合型ＦＥＴのエネル
ギーバンド構造を示す図、第２図は従来のエンハンスメ
ント型ＦＥＴとデプレション型ＦＥＴの同一基板上への
作り分けを示す断面図、第３図（ａ）、（ｂ）は各々本
発明トランジスタの断面図と各層のＡＱの混晶比を示す
図、第４図は本発明のトランジスタの製造工程の例を示
す断面図である。
１５−２次元状担体、１２− ｎ型Ａ Ｑ ｘ Ｇａ１
−ｘＡｓ、１１・・・ノンドープＧ ａ Ａ ｓ、１０
・・・半絶縁性Ｇ ａ Ａ ｓ、１３・・・ゲート電極
、１９・・・ソース・ドレイン電極、１７・・・ｎ型Ｇ
ａ Ａ ｓ層、１２′・・・ノンドープＡ Ｑ Ｘ
Ｇ ａｌ−ｘＡ ｓで０．２８≦Ｘ≦０．４０、（１１
）
（１２）
第１図
７２図
冨３図
１ヶ？１ＪＡ−６Figure 1 is a diagram showing the energy band structure of a conventional selectively doped heterojunction FET, Figure 2 is a cross-sectional view showing how a conventional enhancement type FET and depletion type FET are fabricated on the same substrate, and Figure 3 ( 4A and 4B are cross-sectional views of the transistor of the present invention and diagrams showing the mixed crystal ratio of AQ in each layer, respectively, and FIG. 4 is a cross-sectional view showing an example of the manufacturing process of the transistor of the present invention. 15- Two-dimensional carrier, 12- n-type A Q x Ga1
-xAs, 11...Non-doped GaAs, 10
... Semi-insulating Ga As, 13... Gate electrode, 19... Source/drain electrode, 17... N-type G
a A s layer, 12'...non-doped A Q X
Gal-xA s is 0.28≦X≦0.40, (11
) (12) Figure 1, Figure 72, Figure 3, Figure 1? 1JA-6
Claims (1)
−’以下の不純物濃度）ＧａＡｓ層と不純物を故意に
はドープしない八Ｑの混晶化Ｘが０．２５≦Ｘ≦０．４
の範囲にあるＡＱｘＧａｌ−ｘＡｓ層とがヘテロ接合を
形成し、更にｎ型にドープされ。 ＡＱの混晶比Ｘが０．０５≦Ｘ≦０．２の範囲にあるＡ
ＱＸＧａ、−！Ａｓ層からなる半導体において、ｆｉｉ
ｔｉ記へテロ接合界面に生じる二次元状担体を制御する
電極を有し、少なくとも１対、二次元状担体と電子的に
接続する電極をもつことを特徴とする半導体装置。[Claims] ■. Do not intentionally dope with impurities (10+111cm
−' impurity concentration below) GaAs layer and 8Q mixed crystal that is not doped with impurities intentionally is 0.25≦X≦0.4
forms a heterojunction with the AQxGal-xAs layer in the range of , and is further doped n-type. A whose mixed crystal ratio X of AQ is in the range of 0.05≦X≦0.2
QXGa,-! In a semiconductor consisting of an As layer, fii
1. A semiconductor device comprising: an electrode for controlling a two-dimensional carrier generated at a heterojunction interface; and at least one pair of electrodes electrically connected to the two-dimensional carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59021766A JPH0714054B2 (en) | 1984-02-10 | 1984-02-10 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59021766A JPH0714054B2 (en) | 1984-02-10 | 1984-02-10 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60167475A true JPS60167475A (en) | 1985-08-30 |
| JPH0714054B2 JPH0714054B2 (en) | 1995-02-15 |
Family
ID=12064190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59021766A Expired - Lifetime JPH0714054B2 (en) | 1984-02-10 | 1984-02-10 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714054B2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59968A (en) * | 1982-06-25 | 1984-01-06 | Fujitsu Ltd | Semiconductor device |
-
1984
- 1984-02-10 JP JP59021766A patent/JPH0714054B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59968A (en) * | 1982-06-25 | 1984-01-06 | Fujitsu Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0714054B2 (en) | 1995-02-15 |
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