JPH04333242A - Field-effect transistor - Google Patents

Abstract

PURPOSE:To improve a carrier mobility by a method wherein a ternary compound semiconductor, which has a comparatively large band gap, or larger is used as the material for a first semiconductor layer and a binary compound semiconductor, which has a comparatively small grating constant and a small band gap, is used as the material for a channel layer. CONSTITUTION:Such a high-carrier mobility binary compound semiconductor material as GaSb or InAs is used as the material for a channel layer 3 and as the material for a buffer layer 2, a material, which has a difference of 2%, for example, or thereabouts between the grating constant of the layer 3 consisting of such the semiconductor material as In(Ga, Al)As or (Al, Ga)(As, Sb) and the grating constant of the material, is used. That is, even if an InP substrate 1 is used when In is substituted by 30% or thereabouts, a difference in grating constant between the substrate 1 and the layer 2 is close to 2% and in the case a GaAs substrate is used, there is a difference of 5% or thereabouts between the grating constants of the GaAs substrate and the layer 2. However the distortion of the substrate 1 is relaxed by making thin the layer 2 and the substrate 1 is used as if a substrate of the same grating constant as that of the layer 2 is utilized. Thereby, a carrier mobility is improved.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor manufactured by epitaxial growth, and more particularly to a compound semiconductor field effect transistor capable of high speed operation.

0002

[Prior art] F manufactured by epitaxial growth
ET (Field Effect Transiste)
r) has a structure using a lattice-matched system, as described, for example, in JP-A No. 62-298181. Furthermore, in systems with different lattice constants, a ternary system such as InGaAs has been used for the channel layer, as described in, for example, Japanese Patent Laid-Open No. 1-66972.

0003

[Problems to be Solved by the Invention] Carrier mobility is one of the parameters that influences the performance of FETs. For example, the electron mobility in a low impurity concentration region of GaAs is about 8500 cm2/Vs, which is about six times larger than that of Si. Against this background, research on the application of GaAs to ultra-high-speed devices is active. Furthermore, higher electron and hole mobilities have been confirmed in materials such as InAs and GaSb, and high performance devices using these materials have been expected. However, these materials are GaAs
The lattice constant is approximately 7% larger than that of the InP substrate, and also approximately 3% larger than that of the InP substrate, making it difficult to achieve lattice matching to the substrate or requiring the use of an expensive substrate, making it impractical. It did not lead to change. Therefore, ternary materials such as InGaAs have been used, but InGaAs, which is expected to have high mobility, may even have a lower mobility than GaAs, and its performance has been significantly suppressed.

The purpose of the present invention is to solve the above-mentioned conventional problems, and the first purpose is to improve the mobility of electrons and holes, which greatly contribute to the performance of devices such as FETs, and to The second object of the present invention is to provide a structure that can be applied to devices, and a second object is to provide a structure that can provide high performance even when using a relatively inexpensive substrate material.

[0005]

[Means for solving the problem] The first objective is to
A binary compound semiconductor material with high carrier mobility such as Sb or InAs is used as the channel, and the buffer layer is I
n(Ga,Al)As or (Al,Ga)(As,
By using a material with a lattice constant difference of about 3% or less with the channel layer, such as Sb), the second objective is to
This is achieved by using an aAs substrate and setting the thickness of the buffer layer to 1 μm or more.

[0006]

[Operation] One means for improving the performance of FETs is to improve carrier mobility. Ga
The mobilities of As and InAs at low concentrations are each 850
0.22000 cm2/Vs, and the mobility in InGaAs was generally smaller than the weighted average value based on the composition ratio. One of the reasons for this is considered to be scattering due to mixed crystals. In order to avoid this, it is preferable that at least the channel layer is not a mixed crystal. Therefore, performance can be expected to be improved by using InAs for N-channel and GaSb or InAs for P-channel, instead of InGaAs that has been used conventionally.

[0007] HEMT (High Electro
When adopting a n Mobility Transistor type structure, a high resistance material with a large band gap is required as an electron or hole supply layer. Conventional Ga
In As or InGaAs channel HEMT, AlG
We have used aAs. In InAs and GaSb channels, if In(Ga,Al)As is used, a large bandgap suitable for device applications can be achieved, but as the concentration of Ga or Al increases, the difference in lattice constant between the channel and the channel increases. , dislocations occur in the channel layer. That is, Ga
There are restrictions on the concentration of aluminum and aluminum. That is, 5 out of In
When replacing approximately 0%, the channel thickness is 5n.
When substituting about 30% of the thickness, the thickness must be 8 nm or less. For example, when the lattice constant between the channel and the buffer layer is about 2%, that is, when In is replaced by about 30%, In
Even if a P substrate is used, the lattice constant difference between the substrate buffer layers is 2%.
It is close to 5% for GaAs substrates. However, by making the buffer layer thicker, the strain is alleviated, making it as if a substrate with the same lattice constant as the buffer layer was used.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be specifically described below with reference to the drawings. Hereinafter, as a material description, InAlAs is a material in which some of the In atoms in InAs are replaced with Al, and In(Al,Ga)As is a material in which some of the In atoms in InAs are replaced with Al.
Those in which some atoms are replaced with Al or Ga atoms, (Al,
Ga) (Sb, As) is a part of Ga atoms of GaAs
L atom means an As atom partially replaced with an Sb atom.

Example 1. FIG. 2 shows a cross-sectional view of one embodiment of the present invention. First, MBE is applied onto a semi-insulating GaAs substrate 1.
(Molecular Beam Epitaxy)
lAs buffer layer (Al composition 0.3, thickness: 1.5 μm
) 2, undoped InAs channel layer (5 nm) 3, undoped InAlAs spacer layer (Al composition 0.4, 2
nm) 4, p-InAlAs carrier supply layer (Al composition 0.4, 10 nm, Be concentration: 5 x 1018/cm2)
5, Undoped InAlAs layer (Al composition 0.4, 10
5 nm) 6 and finally deposit an undoped GaAs cap layer (5 nm) 7. Undoped InAlA
The s-layer 4 is a layer that suppresses the diffusion of p-type impurity atoms (Be) in the p-type InAlAs layer 5, and normally has an appropriate thickness of 2 to 10 nm. Next, deposit SiO2 and Van d
An er Pauw pattern was formed. For the ohmic region, SiO2 was etched, InZn was applied, and heat treatment (350° C., 3 minutes) was performed. In this way, a semiconductor device having the structure shown in FIG. 2 was realized.

In order to investigate the influence of the material of the channel layer, an InGaAs (In composition: x) channel was also fabricated with a similar device structure. x is varied from 0.3 to 1, and corresponding to x, the Al concentration of the buffer layer 2 is set to x-0.3, and the Al concentration of the other InAlAs layers 4, 5, and 6 is set to x-0.4. Furthermore, in order to directly compare the measured carrier mobilities, the Be concentration of the carrier supply layer 5 was adjusted so that the sheet carrier concentration was 1×10 12 /cm 2 .

FIG. 3 shows hole mobility for channel materials. As shown in the figure, the mobility in InAs is GaA
The mobility tends to increase as the In composition x increases, reflecting the fact that it is larger than that in Ta.

In epitaxial crystal growth in the manufacturing process, similar results can be obtained by using a device capable of controlling growth in units of atomic layers, such as MOCVD, instead of the MBE shown here.

In this example, the difference in the In composition ratio between the channel layer and the carrier supply layer was set to 0.3, but this is not an absolute value, and a value of about 0.2 to 0.5 may be good. Get results. At this time, it is necessary to pay attention to the thickness of the channel layer 3 and the impurity concentration of the carrier supply layer 5. Furthermore, the results shown in Figure 3 show that the sheet carrier concentration is 1×
1012/cm2, but this concentration is 1×10
Similar results were obtained from about 11/cm2 to about 2×1012/cm2. Although InGaAs is used for the channel layer, GaAsSb may also be used, and the layer structure is not limited to In(Al,Ga)As, for example, (Al,Ga)
) (Sb, As), a similar result can be obtained with a combination of materials such that the difference in lattice constant from the channel layer is about 0.02 nm. In this embodiment, an example of P channel is shown, but similar results can be obtained with N channel. Needless to say, this can be achieved by replacing the P-doped layer of this embodiment with an N-doped layer.

Example 2. FIG. 1 shows a cross-sectional view of one embodiment of the present invention. First, MBE (
Undoped In(A
l, Ga) As buffer layer (Al composition 0.3, Ga composition 0.2, thickness: 0.6 μm) 2, undoped InAs channel layer (5 nm) 3, undoped InAlAs spacer layer (Al composition 0.6, 2 nm) )4,p-InAlAs
Carrier supply layer (Al composition 0.6, 10 nm, Be concentration: 5 x 1018/cm2) 5, undoped InAlAs
A layer (Al composition: 0.6, 10 nm) 6 is grown, and finally a p-GaAs cap layer (concentration: 3 x 1019/cm2) is grown.
, 160 nm) 7.

The undoped InAlAs layer 4 is a p-type InAlAs layer 4.
This is a layer that suppresses the diffusion of p-type impurity atoms (Be) in the AlAs layer 5, and normally has an appropriate thickness of 2 to 10 nm. Also,
The undoped InAlAs layer 6 is a layer in contact with the gate, and is provided to suppress gate leakage current.

Next, after isolation between elements is performed by mesa etching, a SiO2 film 11 is deposited, and holes for the source electrode 8 and drain electrode 9 are formed by a normal photolithography process. SiO2 on the surface of this hole
The film 11 is removed by dry etching, and then p-GaA
A hole of approximately 40 nm is formed in the s-cap layer 7 by wet etching. Further, the side of the SiO2 film 11 is etched by wet etching to give it a shape that facilitates lift-off. Au/Mo/AuZn/Mo/Au was deposited on top of this,
Heat treatment (400°C, 2 minutes) is performed. Furthermore, a gate pattern is formed using an EB (electron beam) lithography method. Next, wet etching and selective dry etching were performed to remove the undoped AlGaAs layers 4 and 10 with good controllability. Furthermore, by lift-off after depositing Al, the gate length is 0.1 μm and the gate width is 50 μm.
m gate electrodes 16 were formed. In this way, Figure 1
We have realized an FET with the structure shown in .

The device according to this embodiment has a hole mobility of 65
0cm2/Vs, withstand voltage: 6V, mutual conductance g
m: 420mS/mm, source resistance Rs: 5.0Ω・m
It exhibited high performance with m and K values of 5.3 mS/V and 10 μm.

FIG. 4 shows the relationship between drain voltage and drain current using gate voltage as a parameter. Good characteristics as shown in the figure were obtained. In addition, during epitaxial crystal growth in the manufacturing process, the MB shown here
Similar results can be obtained by using a device that can control growth on an atomic layer basis, such as MOCVD, instead of E. Further, the thickened cap layer 7 may be formed later using a technique such as MOCVD selective growth, for example. Further, the cap layer 7 is not limited to GaAs, but may also be made of a material that easily makes ohmic contact, such as InGaAs. Further, the undoped InAlAs layer 6 directly under the gate may be made of p-InAlAs with a thickness of 1×10 18 /cm 2 or less, as long as the withstand voltage is not reduced.

In this example, the Al composition x of the InAlAs layer is 0.6, and the Al composition x of the In(Al,Ga)As layer is 0.6.
Although 0.3 and 0.2 were used as the composition y and Ga composition z, respectively, x was about 0.4 to 0.6, and the combination of y and z was 0.2, 0.3 to 0.5. , 0 can also be used to obtain similar results. However, if the Al concentration is too low, the buffer layer 2 will have low resistance and its characteristics will deteriorate. Moreover, the InAlAs layers 4 to 6 have the same I
In(Al,Ga)As having an n composition may also be used. In this case, the value of energy discontinuity in the valence band becomes small, but good results can be obtained with an Al composition of about 0.3 to 0.5. In addition, although InAs was used for the channel layer, GaSb may also be used, and the layer structure may also be In(Al,
Not limited to Ga) As, for example (Al, Ga) (Sb, A
s), the difference in lattice constant from the channel layer is 0.0
A similar result can be obtained when combining materials such that the thickness is about 2 nm. In addition, GaAs is cheaper than InP.
A substrate may also be used. At this time, a lattice mismatch occurs between the buffer layer 2 and the buffer layer 2, but it can be used by making the thickness of the buffer layer 2 1 μm or more.

Although this embodiment shows an example of a P-channel field effect transistor, good results can also be obtained with an N-channel field effect transistor. Needless to say, this can be achieved by replacing the P-doped layer of this embodiment with an N-doped layer.

Example 3. FIG. 5 shows a cross-sectional view of one embodiment of the present invention. First, MBE (
Undoped In(A
l, Ga) As buffer layer (Al composition 0.3, Ga composition 0.2, thickness: 0.6 μm) 2, undoped InAs channel layer (5 nm) 12, undoped InAlAs spacer layer (Al composition 0.6, 2 nm) )13,n-InAl
As carrier supply layer (Al composition 0.6, 10 nm, Si
Concentration: 5 x 1018/cm2) 14, undoped InA
lAs layer (Al composition 0.6, 10 nm) 15, undoped GaAs element isolation layer (thickness: 0.2 μm) 16, undoped In(Al,Ga)As buffer layer (Al composition 0.3, Ga composition 0. 2, Thickness: 0.6 μm) 17, Undoped InAs channel layer (5 nm) 3, Undoped InAlAs spacer layer (Al composition 0.6, 2 nm) 4
, p-InAlAs carrier supply layer (Al composition 0.6,
10 nm, Be concentration: 5 x 1018/cm2) 5, undoped InAlAs layer (Al composition 0.6, 10 nm) 6
Finally, a p-GaAs cap layer (concentration: 3
x1019/cm2, 160 nm)7.

Next, after performing isolation between elements by mesa etching, by a normal photolithography process,
The P-type region is masked, and the N-type region is etched halfway through the GaAs isolation layer 12 by wet etching, and then etched to the front of the InAlAs layer 6 by selective dry etching. After removing the resist, a hole for the n-type ohmic contact layer 18 is formed again by photolithography process. The opening is made of InAlAs
After etching and removing part of buffer layer 2, MOCVD
By selective growth, an n-InAs layer (thickness: 160 nm)
Grow 18. Next, a SiO2 film (thickness: 30
0 nm) 11 is formed, and holes for the source electrode 8 and drain electrode 9 of the P-type region are formed by a photolithography process. The SiO2 film 11 on the surface of this hole is removed by dry etching, and then a hole of about 40 nm is formed in the p-GaAs cap layer 7 by wet etching. Further, the side of the SiO2 film 11 is etched by wet etching to give it a shape that facilitates lift-off. On top of this, Au/Mo/AuZn/Mo/Au is deposited as a P-type layer. Next, source and drain electrodes of N-type layers are formed by a similar photolithography process. Au/Ni/AuGe was vapor-deposited as an electrode material and heat-treated (400
℃, 2 minutes), and the source electrode 8 and drain electrode 9
form. Furthermore, using the EB (electron beam) lithography method,
Form a gate pattern. Next, wet etching and selective dry etching are performed to undope the InAl with good controllability.
The As layer 6 was removed by etching. Next, by lift-off after depositing Al, the gate length is 0.1
A gate electrode 10 having a gate width of 50 μm and a gate width of 50 μm was formed.

The device according to this embodiment is a P-channel FET.
Hole mobility: 650cm2/Vs, breakdown voltage: 6V,
Mutual conductance gm: 420mS/mm, source resistance Rs: 5.0Ω・mm, K value 5.3mS/V・1
0μm, electron mobility in N channel FET part: 1850
0cm2/Vs, withstand voltage: 10V, mutual conductance g
m: 1630mS/mm, source resistance Rs: 1.0
It showed high performance with Ω・mm and K value of 21.5 mS/V・10 μm.

In epitaxial crystal growth in the manufacturing process, similar results can be obtained by using a device capable of controlling growth in units of atomic layers, such as MOCVD, instead of the MBE shown here. Further, the thickened cap layer 7 can be formed using a method such as MOCVD selective growth, for example.
It may be formed later. Further, the cap layer 7 is made of G
In addition to aAs, a material that can easily form ohmic contact, such as InGaAs, may also be used. In addition, the undoped InAlAs layers 6 and 15 directly under the gate each have a p of 1×10 18 /cm 2 or less to the extent that the withstand voltage is not reduced.
- and n-InAlAs may also be used.

In this example, the Al composition x of the InAlAs layer is 0.6, and the Al composition x of the In(Al,Ga)As layer is 0.6.
Although 0.3 and 0.2 were used as the l composition y and the Ga composition z, respectively, x was about 0.4 to 0.6, and the combination of y and z was 0.2, 0.3 to 0. Similar results can be obtained using a value of about 5.0. However, if the Al concentration is too low, the buffer layer 2 will have low resistance and its characteristics will deteriorate. InAlAs layers 4 to 6 and 13 to 15 may be made of In(Al,Ga)As having the same In composition. In this case, although the value of energy discontinuity in the valence band becomes small, good results can be obtained with an Al composition of about 0.3 to 0.5. Also, the channel layer is InA
Although GaSb was used, GaSb may also be used, and the layer structure is not limited to In(Al,Ga)As, for example, (Al,Ga).
) (Sb, As), a similar result can be obtained with a combination of materials such that the difference in lattice constant from the channel layer is about 4% nm or less. Furthermore, a GaAs substrate, which is cheaper than InP, may be used. At this time, a lattice mismatch occurs between the buffer layer 2 and the buffer layer 2, but good results are obtained by setting the thickness of the buffer layer 2 to 1 μm or more.

In this embodiment, the P-channel FET was placed on the side farther from the substrate, but the N- and P-channel FETs
Similar results can be obtained by reversing the arrangement of both ETs. Good results can also be obtained with N channels. In addition, if InGaAs or GaAs is used for the N-channel part, a complementary type FET with similar performance to the N- and P-channel FETs can be used.
ET is possible. At this time, a semi-insulating GaAs substrate was used, and layers 2 to 17 in this example were composed of an undoped GaAs buffer layer (thickness: 0.6 μm) 2, an undoped GaAs channel layer (15 nm) 12, an undoped A
lGaAs spacer layer (Al composition 0.3, 2 nm) 13
, n-InAlAs carrier supply layer (Al composition 0.3,
10 nm, Si concentration: 5 x 1018/cm2) 14, undoped InAlAs layer (Al composition 0.3, 10 nm)
15, Undoped GaAs element isolation layer (thickness: 0.2
μm) 16, undoped In(Al,Ga)As buffer layer (Al composition 0.3, Ga composition 0.2, thickness: 0.6
μm) may be set to 17.

[0027]

[Effects of the Invention] According to the present invention, carrier mobility can be improved by suppressing alloy scattering using a strained channel of a binary compound semiconductor, and a great effect can be obtained when applied to a field effect transistor. It will be done.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a field effect transistor showing one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a semiconductor device showing an embodiment of the present invention.

FIG. 3: Dependence of carrier mobility on channel material.

FIG. 4 is a characteristic curve diagram showing the drain voltage dependence of drain current.

FIG. 5 is a cross-sectional view of a complementary field effect transistor showing an embodiment of the present invention.

[Explanation of symbols]

1... Semi-insulating InP substrate, 2... Undoped InAlAs
Buffer layer, 3... Undoped InAs channel layer, 4...
Undoped In(Al,Ga)As layer, 5...p-In(
Al, Ga) As layer, 6... undoped In(Al, Ga)
) As layer, 7... p-GaAs cap layer, 8... source electrode, 9... drain electrode, 10... gate electrode, 11... Si
O2 film, 12... Undoped InAs channel layer, 13
...Undoped In(Al,Ga)As layer, 14...p-I
n(Al,Ga)As layer, 15... undoped In(Al
, Ga)As layer, 16... undoped GaAs element isolation layer, 17... undoped InAlAs buffer layer, 18...
n-InAs ohmic layer.

Claims (8)

[Claims] 1. A field effect transistor, comprising: a first semiconductor layer formed on a semiconductor substrate or an epitaxial layer grown on the substrate; and a channel layer formed on the first semiconductor layer. A field effect transistor characterized in that the first semiconductor layer uses a ternary or higher compound semiconductor with a relatively large band gap, and the channel layer uses a binary compound semiconductor with a relatively small lattice constant and a small band gap. 2. The channel layer is an undoped layer that does not consciously contain impurities, and has a HEMT structure that is spatially separated from a carrier supply layer that contains N- to P-type impurities. Item 1. Field effect transistor according to Item 1. 3. The field effect transistor according to claim 1, wherein the channel layer is InAs when the channel layer is an N channel, and InAs or GaSb when the channel layer is a P channel. 4. The carrier supply layer and the first semiconductor layer are made of In(Al,Ga)As in which a part of In atoms in InAs are replaced with Ga or Al atoms, or Sb in AlGaSb.
AlGa(As,Sb) in which some of the atoms are replaced with As atoms
) The field effect transistor according to any one of claims 1 to 3, characterized in that: 5. The field effect transistor according to claim 1, wherein the substrate is made of GaAs or InP, and the first semiconductor layer has a thickness of 1 μm or more. 6. In(Al, Ga), wherein the substrate is made of GaAs or InP, and the first semiconductor layer has an In concentration varying from a composition lattice-matched to the substrate to a composition lattice-matched to the carrier supply layer. 5. The field effect transistor according to claim 1, wherein the field effect transistor is made of As. 7. In(Al, Ga) used for the buffer layer.
) The composition ratio of In atoms in As, or the composition ratio of In atoms in AlGa(A
7. The field effect transistor according to claim 3, wherein the composition ratio of Sb in S, Sb) is 0.7 or more, and the thickness of the channel layer is 20 nm or less. 8. The field effect transistor according to any one of claims 1 to 7 is used as either or both of an N channel and a P channel field effect transistor, and
A complementary field effect transistor characterized in that a channel field effect transistor and a P channel field effect transistor are formed on the same substrate.