JP2773782B2 - Compound semiconductor heterojunction structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a compound semiconductor heterojunction structure suitable for forming an FET-type semiconductor device, in which a compound semiconductor crystal grown on an InP substrate has a high resistance characteristic. A compound semiconductor heterojunction structure comprising: an InP crystal substrate; and a first compound semiconductor layer lattice-matched to the InP substrate, wherein the InP substrate and the first compound semiconductor layer are provided. A second compound semiconductor layer is formed between the first compound semiconductor layer and the first compound semiconductor layer. The second compound semiconductor layer is made of a material that is lattice-mismatched with the InP substrate. The film thickness and composition are selected so that dislocations do not occur due to lattice mismatch between the InP substrate and the effective bandgap energy is larger than that of the InP substrate. Configuration.

The present invention relates to a compound semiconductor heterojunction structure,
The present invention relates to a compound semiconductor heterojunction structure suitable for forming an FET type semiconductor device.

InGaAs has attracted attention as a material of a semiconductor device which has a higher carrier mobility than GaAs and operates at high speed. However, there are still problems to be solved for practical use.

[Prior Art] High Electron Mobility Transistor (HE) using AlGaAs layer and GaAs layer on GaAs substrate
Field effect transistors called MT) are known.
This transistor has a very high electron mobility in a two-dimensional electron gas and operates at high speed.

When a large number of elements are integrated on a common substrate, an interference effect between elements called a side gate effect becomes a serious obstacle to the operation of an integrated circuit. This is simply an effect that a voltage applied to an electrode connected to a certain element affects the operation of an adjacent element (deterioration of threshold characteristics). Ga
In the case of an As-AlGaAs-based semiconductor device, the side gate effect can be suppressed by inserting a layer having a sufficiently high resistance as a buffer layer between a channel layer in which a two-dimensional carrier gas runs and the substrate. Are known. Such a high-resistance layer is formed when the crystal growth method is MOCVD.
It is obtained by doping a transition metal or oxygen into aAs or AlGaAs crystal.

Recently, to improve the performance of the HEMT, a structure in which an InP substrate is used instead of the conventional GaAs and a channel layer is formed of an InGaAs layer has been attempted. InGaAs has a higher mobility than GaAs. However, this InGaAs material system has a small band gap energy under the condition of lattice matching with the InP substrate, and it is difficult to obtain a sufficiently high resistance layer.

If a high resistance cannot be obtained, the pinch-off characteristics of the transistor deteriorate. That is, a voltage difference between when the transistor is turned off and when the transistor is turned on increases.

Further, when manufacturing an integrated circuit of a compound semiconductor using such an InP substrate, there is a problem in suppressing the side gate effect described above. That is, even if InAlAs or the like is used, it is difficult to form a high-resistance layer on an InP substrate, which is a major obstacle to the manufacture of a semiconductor integrated circuit device.

[Problems to be Solved by the Invention] As described above, according to the conventional technique, it is difficult to form a sufficiently high-resistance region on an InP substrate when it is used.

An object of the present invention is to provide a compound semiconductor heterojunction structure in which a compound semiconductor crystal grown on an InP substrate has high resistance characteristics.

[Preliminary Study] To suppress the side gate effect, it is considered effective to insert a high-resistance layer between the substrate and the channel layer in which the two-dimensional electron gas travels, as described above. Such a high resistance layer is made of AlGaAs in a material system using a GaAs substrate.
Can be obtained by injecting a material having a deep level such as a transition metal or oxygen into the substrate. Empirically, when the specific resistance is about 10 ¹¹ Ωcm, the effect of suppressing the side gate effect is large.
The achievable specific resistance value is determined by the amount of material that forms a deep level and the hand gap energy of the semiconductor material.

In the case of In _0.52 Al _0.48 As lattice-matched to the InP substrate, according to experiments performed by the present inventors, even if doped with a transition metal or oxygen that forms a deep level, it is large enough to completely suppress the side gate effect. A specific resistance value could not be obtained. The reason for this has not been completely elucidated, but it is probably due to the fact that In constituting the crystal plays a role of inhibiting the formation of deep levels and the band gap energy of the InAlAs crystal is small. Therefore, according to the data obtained by the present inventors, it is extremely difficult to suppress the side gate effect as long as the compound semiconductor material is lattice-matched to the InP substrate.

[Means for Solving the Problems] In the present invention, based on the findings of the inventor, a crystal having an In composition ratio as small as possible and a bandgap energy as large as possible is used for a buffer layer between an InP substrate and an active layer. This makes it possible to suppress the side gate effect. However, such crystals cannot be obtained under the condition that they are lattice-matched with the substrate, as described above.

It is known that even in the case of lattice mismatch, dislocation does not occur even if lattice mismatch occurs unless a certain film thickness determined by the degree of lattice mismatch, that is, a critical film thickness is exceeded. Therefore, a crystal layer having a high resistance value can be obtained by selecting a crystal having as small an In composition ratio as possible and having as large a band gap energy as possible for the buffer layer within the range of the critical film thickness.

FIG. 1 is a diagram illustrating the principle of the present invention. InP crystal substrate 1
Buffer layer 11 of compound semiconductor lattice-mismatched with InP on 0
Is formed, and a layer 12 of a compound semiconductor that lattice-matches with InP is formed on the buffer layer 11.

For example, a lattice-mismatched compound semiconductor has a lattice mismatch of about 1% or more with InP, and a lattice-matched compound semiconductor has a lattice mismatch of about 0.1% or less with InP. Here, the thickness and composition of the buffer layer 11 are selected so that dislocations due to lattice mismatch do not occur, the band gap energy is larger than that of the substrate InP, and the buffer layer 11 is doped with a transition metal or oxygen.

[Operation] Since the buffer layer is formed on the InP substrate using a material that does not lattice-match with InP, the range of selection is expanded, and a material that easily realizes high resistance can be used. Therefore, a desired high resistance can be realized.

Even if there is a lattice mismatch with the substrate, generation of dislocations can be prevented by controlling the composition and thickness, so that an active layer with good crystallinity can be obtained.

Example First, the fact that the effect of forming a lattice-mismatched layer on InP was experimentally confirmed will be described.

As a compound semiconductor crystal in which the In composition ratio is as small as possible and the band gap is as large as possible, for example, In
_{There is 0.52-x} Al _{0.48 + x} As. Although lattice matching with InP occurs when x = 0, lattice matching with InP occurs as x increases. An In _0.52 Ga as both sides of the layer shown in FIG. 2 upper right
_The current / voltage characteristics were measured while changing the value of x with _0.48 As. The specific resistance obtained from the experimental results is shown in the graph of FIG. It was observed that the resistivity increased significantly with increasing x value. Thus, a high-resistance layer can be formed between the InP substrate and the InGaAs active layer. this is
This may be because, as In decreases and Al increases, first, a deep level is easily formed, and second, carriers on the conduction band decrease due to an increase in band gap energy. If the x value is set too large, In _0.52-x Al
As the critical thickness of the _{0.48 + x} As layer becomes smaller, the thickness must be reduced accordingly. Then, the resistance value decreases. In such a case, what is necessary is just to increase the film thickness of the high resistance layer as a whole by forming a so-called strained superlattice structure in which the layer structure is stacked in multiple layers.

When an AlGaAs layer is selected as the high-resistance layer, the critical thickness is only 3.5n due to the large 3% lattice mismatch with InP.
m, and this thickness does not provide a sufficiently high resistance. In such a case, a desired resistivity can be obtained by using a superlattice structure having a period of In _0.52 Ga _0.48 As / AlGaAs as a buffer layer.

Hereinafter, an embodiment of the HEMT will be described with reference to FIG. FIG. 3 shows a configuration in which a HEMT is formed using a compound semiconductor hetero-bond structure on an InP substrate. In FIG. 3, a high-resistance buffer layer 32 is formed on an InP substrate 31, and an InGaAs
A channel layer 33 is formed. Buffer layer 32 is 10 ¹⁵ cm
^-3 or more, for example, 10 ¹⁶ cm ^-3 , is doped with a transition metal or oxygen, has a sufficiently high resistance, and prevents the side gate effect from occurring. On the InGaAs channel layer 33, an n-type for supplying carriers (electrons) to this channel layer
An InAlAs carrier supply layer 34 is formed, forming a basic structure of the HEMT. An n-type InGaAs enhancement / depletion difference voltage generation layer 35 and an n-type InAl
As etching stop layer 36 and n-type InGaAs cap layer 37 are laminated. The etching stop layer 36 is a layer for automatically stopping the etching when forming the gate of the depletion mode HEMT, and the cap layer 37 is a layer for covering the Al-containing layer and facilitating the formation of the ohmic catalyst. is there. In the figure, 39 is a source electrode, 40 is a drain electrode, 41 is a gate electrode of a depletion mode HEMT, and 42 is a gate electrode of an enhancement mode HEMT. Oxygen is ion-implanted around each HEMT to form an isolation region 38. When the difference voltage generation layer 35 is removed, the channel of the channel layer 33 due to the two-dimensional electron gas disappears, and the enhancement mode HEMT
Becomes A broken line in the channel layer 33 indicates a two-dimensional electron gas.

 Here, a structural example of this embodiment will be described below.

(1) Buffer layer 32 material: In _0.52 Ga _0.48 As and oxygen doped (10 ¹⁶ cm ^-3 ) In _0.3 Al _0.7 As Thickness: In _0.52 Ga _0.48 As layer is 100 nm In _0.3 Al _0.7 As layer is 100 nm ( 2) Channel layer 33 material: In _0.52 Ga _0.48 As Thickness: 100 nm (3) Carrier supply layer 34 material: In _0.52 Al _0.48 As Thickness: 30 nm Impurity: Si Impurity concentration: 1.5 × 10 ¹⁸ cm ⁻³ ( 3) Differential voltage generation layer 35 Material: In _0.52 Ga _0.48 As Thickness: 7 nm Impurity: Si Impurity concentration: 1.5 × 10 ¹⁸ cm ^-3 (5) Etch stop layer 36 Material: In _0.52 Al _0.48 As Thickness: 3 nm impurity: Si impurity concentration: 1.5 × 10 ¹⁸ cm ⁻³ (6) Cap layer 37 Material: In _0.52 Ga _0.48 As Thickness: 50 nm impurity: Si impurity concentration: 1.5 × 10 ¹⁸ cm ^{−3 In} this structure, The source and drain electrodes 39 and 40 are formed of Au / AuGe, and the gate electrodes 41 and 42 are formed of Al. The enhancement mode FET and the depletion mode FET are separately formed depending on the presence or absence of the difference voltage generation layer 35. C
In dry etching using H ₃ Br + O ₂ mixed gas as an etchant, InGsAa and InAlAs are subjected to selective etching by utilizing the fact that they have a large selective etch rate ratio when irradiating ultraviolet rays, thereby accurately etching the difference voltage generation layer. it can.

In a HEMT according to another embodiment of the present invention, the buffer layer of FIG. 3 is formed of a superlattice. When AlGaAs is used as a material having a wide band gap, the thickness of one layer has to be reduced because of large lattice mismatch. Therefore, the resistance as a whole is increased by increasing the number of layers. For example, buffer layer
32 is made as follows.

Material: Al _0.3 Ga _0.7 As / In _0.52 Ga _0.48 As Thickness: 50 nm strained superlattice with 3 nm in each layer Impurity: O (oxygen atom) Impurity concentration: 1 × 10 ¹⁶ cm ^-3 Oxygen is doped into the InGaAs layer. Although it is not necessary, it is doped for convenience of the manufacturing process. The other points are the same as in the first embodiment.

In any of the above embodiments, the buffer layer 32 may be doped with a transition metal such as Fe, Cr, Ti, Ta, V, etc., for example, Fe instead of oxygen doping.

Further, the compound semiconductor heterojunction structure according to the present invention can be used for a field effect transistor other than HEMT, for example, MESF.
Also applicable to ET, MISFET, HET, etc.

Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. For example, it will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

[Effect of the Invention] As described above, according to the present invention, the InP substrate and the InP
A buffer layer having a high resistance value can be provided between the semiconductor layer and the compound semiconductor layer that lattice-matches.

Therefore, a high-speed compound semiconductor device in which the side gate effect is suppressed can be realized.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of the present invention, FIG. 2 is a graph for explaining the effect of lattice mismatch, and FIG. 3 is a sectional view of a main part of an HEMT according to an embodiment of the present invention. In the figure, 10, 31... InP substrate 11, 32... Buffer layer 12... Compound semiconductor layer lattice-matched with InP 33... InGaAs channel layer 34. / Depletion difference voltage generation layer 36 n-type InAlAs etching stop layer 37 n-type InGaAs cap layer 38 element isolation region 39 source electrode 40 drain electrode 41 42 gate electrode

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 29/812 (58) Investigated field (Int.Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27/095 -27/098 H01L 29/775-29/778 H01L 29/80-29/812 H01L 21/70-21/74 H01L 21/76-21/765 H01L 21/77

Claims (3)

(57) [Claims] An InP crystal substrate (10) and said InP substrate (10)
And a first compound semiconductor layer (12) lattice-matched with the compound semiconductor heterojunction structure, a buffer layer including a second compound semiconductor layer between the InP substrate and the first compound semiconductor layer ( 11) is formed, wherein the second compound semiconductor layer is made of a material that is lattice-mismatched with the InP substrate, and has a lattice mismatch between the InP substrate and the first compound semiconductor layer. A compound semiconductor heterojunction structure in which the film thickness and composition are selected so that dislocations are not caused, the effective band gap energy is larger than that of the InP substrate, and a transition metal or oxygen is doped. 2. A compound semiconductor heterojunction structure including an InP crystal substrate (10) and a first compound semiconductor layer (12) lattice-matched to the InP substrate, wherein the InP substrate (10) and the A super-structure in which a plurality of unit structures are stacked with a unit period of a heterostructure composed of an element layer of the first compound semiconductor and an element layer of a second semiconductor lattice-mismatched with InP between the first compound semiconductor layer (12). A buffer layer (12) having a lattice structure, wherein the thickness and composition of each element layer of the superlattice are adjusted to the InP substrate (10).
And the first compound semiconductor element layer and the first compound semiconductor layer (12) are selected so as not to cause dislocation due to lattice mismatch between the first compound semiconductor element layer and the first compound semiconductor element layer in the superlattice structure. 2. A compound semiconductor heterojunction structure in which at least one of the compound semiconductor element layers 2 is doped with a transition metal or oxygen. 3. The method according to claim 1, wherein the first compound semiconductor is InGaAs,
3. The compound semiconductor heterojunction structure according to claim 1, wherein said second compound semiconductor is InAlAs.