JPH04725A - Compound semiconductor heterojunction structure - Google Patents

Abstract

PURPOSE:To provide a compound semiconductor heterojunction structure capable of restraining side gate effects by a method wherein crystal in which an In composition rate is as small as possible and concurrently band gap energy is as large as possible is utilized in a buffer layer existing between an InP substrate and an active layer. CONSTITUTION:An InP and a buffer layer 11 of a lattice mismatching chemical compound semiconductor are formed on an InP crystal substrate 10, and further a layer 12 of a chemical compound semiconductor having a lattice matching characteristic with InP is formed on the buffer layer 11. For instance, the lattice mismatching chemical compound has about 1% or more of lattice mismatching against InP, and the lattice matching chemical compound semiconductor has only about 0.1% or less of lattice mismatching against InP. Hereupon, in the buffer layer 11, a film thickness and a composition are selected so as not to cause transition caused by lattice mismatching, and band gap energy is larger than that of InP which is a substrate, and a transition metal or oxygen is doped.

Description

[Detailed Description of the Invention] ΣSummary; Concerning a compound semiconductor heterojunction structure suitable for forming the FET type semiconductor device 1, a compound semiconductor in which a compound semiconductor crystal grown on an InP substrate has high resistance characteristics is provided. For the purpose of providing a heterojunction structure, an InP crystal substrate and a first layer lattice matched with the InP substrate are provided.
In the compound semiconductor heterojunction structure including a layer of a compound semiconductor, a second compound semiconductor layer is formed between the InP substrate and the first compound semiconductor layer, and a second compound semiconductor layer is formed between the InP substrate and the first compound semiconductor layer.
The compound semiconductor layer is made of a material that is lattice mismatched with the InP substrate, and is formed between the compound semiconductor layer and the first compound semiconductor layer.
The film thickness and composition are selected so as not to generate dislocations due to lattice mismatch with the compound semiconductor layer, and the effective band gear lag energy is larger than that of the InP substrate,
It is configured to be doped with a transition metal or oxygen.

εIndustrial Application Field The present invention relates to the heterojunction structure of compound semiconductors, particularly F
The present invention relates to a compound semiconductor heterojunction structure suitable for forming an ET type semiconductor device.

InGa83 has higher carrier mobility than GaAs and is attracting attention as a material for semiconductor devices that operate at high speed. However, there are still issues to be solved in order to put it into practical use.

εPrior art] High electron mobility transistor (Hiah Electro
n Nobility Transistor, HE
A field effect transistor called M T ) is known. This transistor has extremely high electron mobility in the two-dimensional electron scum and operates at high speed.

When a large number of elements are integrated on a common substrate, an interference effect between elements called a side gate effect becomes a serious obstacle to the operation of the integrated W circuit. Simply put, this is an effect in which the voltage applied to the 8ii connected to a certain element affects the operation of the adjacent element (deterioration of threshold preference).

In the case of GaAS-AlGaAs-based semiconductor devices, this side gate effect can be suppressed by inserting a layer with sufficiently high resistance as a buffer layer between the channel layer through which the two-dimensional carrier gas travels and the substrate. It has been known. Such a high resistance layer is obtained by doping a transition metal or oxygen into a GaAS or AIGaAS crystal when the crystal growth method is MOCVD.

Recently, conventional GaAS has been used to improve the performance of HEMT.
Instead, an InP substrate is used, and the channel layer is made of InGa.
A structure consisting of A3 layers has been attempted. 1nGaAs
has higher mobility than GaAS. However, this InGaAS material system has a small band gap energy under the condition of lattice matching with the InP substrate.
It is difficult to obtain layers of sufficiently high resistance.

If high resistance cannot be obtained, the pinch-off characteristics of the transistor will deteriorate. In other words, the voltage difference between when the transistor is turned off and when it is turned on increases.

Furthermore, when manufacturing a compound semiconductor integrated circuit using such an InP substrate, there is a problem of suppressing the above-mentioned side gate effect. In other words, even if InAlAs or the like is used, it is difficult to form a high resistance layer on an InP substrate, which poses a major obstacle to the manufacture of semiconductor integrated circuit devices.

Problems to be Solved by the Present Invention] As explained above, according to the conventional techniques, when an InP substrate is used, it is difficult to form a sufficiently high resistance region thereon.

An object of the present invention is to provide a compound semiconductor heterojunction structure in which a compound semiconductor crystal grown on an InP substrate has high resistance characteristics.

[epsilon] Preliminary Consideration] As described above, inserting a layer with high resistance between the substrate and the channel layer through which the two-dimensional electronic debris travels is considered to be effective in suppressing the side gate effect. Such a high resistance layer is made of Al in a material system using a GaAS substrate.
It can be obtained by implanting deep-level materials such as transition metals and oxygen into GaAs, and empirically it has a resistance of 1011 Ω.
The specific resistance value that can be achieved, which is highly effective in suppressing the side gate effect, is determined by the amount of material that forms a deep level introduced and the band gear pump energy of the semiconductor material.

Ino, 52Alo, 4aA lattice matched to InP substrate
In the case of S, according to experiments conducted by the present inventors, even when doped with transition metals, oxygen, etc. that form deep levels, it was not possible to obtain a resistivity value large enough to completely suppress the side gate effect. The reason for this has not been completely elucidated, and is probably due to the fact that In, which constitutes the crystal, plays a role in inhibiting the formation of deep levels, and the band gap energy of the InAIAS crystal is small. Therefore, according to the data obtained by the present inventor, InP
As long as it is limited to compound semiconductor materials that are lattice matched to the substrate,
Suppression of side gate effects is extremely difficult.

Means for Solving the Two Problems] In the present invention, based on the knowledge of the above inventor, a crystal having as small an In composition ratio as possible and as large a band gear pump energy as possible is used for the buffer layer between the InP substrate and the active layer. This makes it possible to suppress side gate effects. However, as described above, such a crystal cannot be obtained under the condition of lattice matching with the substrate.

It is known that even in the case of lattice mismatch, dislocations do not occur even if there is lattice mismatch, as long as the film thickness does not exceed a certain film thickness determined by the degree of lattice mismatch, that is, a critical film thickness. Therefore, a crystal layer with a high resistance value can be obtained by selecting a crystal for the buffer layer that has an In composition ratio as low as possible and a band gear pump energy as large as possible within this critical film thickness range.

FIG. 1 is a diagram explaining the principle of the present invention. This structure has a structure in which a buffer layer 11 of a compound semiconductor that is lattice-mismatched with InP is formed on an InP crystal substrate 10, and a compound semiconductor layer 12 that is lattice-matched with InP is further formed on the buffer layer 11.

For example, a lattice-mismatched compound semiconductor has a lattice mismatch of about 1% or more with respect to JnP, and a lattice-matched compound semiconductor has a lattice mismatch of about 0.1% or less with respect to JnP. Here, the thickness and composition of the buffer layer 11 are selected so as not to generate dislocations due to lattice mismatch, the band gap energy is larger than that of the substrate InP, and the buffer layer 11 is doped with a transition metal or oxygen.

7. Effect; Since the buffer layer is formed on the InP substrate using a material that does not lattice match with InP, the range of selection is expanded, and materials that can easily achieve high resistance can be used. Therefore, it becomes possible to achieve a desired high resistance.

Even if there is a lattice mismatch with the substrate, the generation of dislocations can be prevented by controlling the composition and thickness, so it is possible to obtain an active layer with good crystallinity.

5 Example 1 First, it will be explained that the effect of forming a lattice mismatched layer on InP was experimentally confirmed.

) As a compound semiconductor crystal whose n composition ratio is as small as possible and whose node gap is as large as possible,
There is n0.52-x"0.48+xAS. At x=0 I
It is either lattice matched to nP or becomes lattice mismatched to InP as X increases. Both sides of this layer were sandwiched between In, 52GaO, and 4sAs as shown in the upper right corner of FIG. 2, and the current/voltage characteristics were measured while changing the X value. The specific resistance obtained from the experimental results is shown in the graph of FIG. 2. It was observed that the specific resistance increased significantly as the X value increased. In this way, it became possible to form a high resistance layer between the InP substrate and the InGaAs active layer.

This is probably because, as In decreases and A1 increases, firstly, deep levels are more likely to be formed, and secondly, as the band gear pump energy increases, carriers above the conduction band decrease. If the X value is set too large, In
0.52-x"0.48+xAs the critical thickness of the AS layer becomes smaller - the II thickness must be reduced accordingly, which will reduce the resistance value. In such a case, the layer structure The high-resistance layer may have a so-called strained superlattice structure in which it is laminated in multiple layers to increase the thickness of the high-resistance layer as a whole.

If an AlGaAs layer is selected as the high resistance layer, InP
In such a case, the critical film thickness is only 3.5 nm because the lattice mismatch with In is as large as 3%, and a sufficiently high resistance cannot be obtained with this thickness.

A desired resistivity can be obtained by using a superlattice structure with a period of 52 Ga and 48 AS/AIGaAS as a buffer layer.

Hereinafter, an embodiment of the HEMT will be described with reference to FIG.

Figure 3 shows a configuration in which a HEMT is formed using a compound semiconductor heterojunction structure on an InP substrate.
A high resistance buffer layer 32 is formed on the P substrate 31,
An InGaAS channel layer 33 is formed thereon. The buffer layer 32 has a thickness of 1015■-3 or more, for example l
Q16. -3, is doped with a transition metal or oxygen, has a sufficiently high resistance, and prevents the side gate effect from occurring. On the InGaAs channel layer 33, there is an n-type 1 layer for supplying carriers (electrons) to this channel layer.
An nAIAs carrier supply layer 34 is also formed, forming the basic structure of the HEMT. On top of this, further n-type 1n
GaAs enhancement, ・'depletion voltage difference generation layer 35, n-type 1nAIAs processing stop layer 36
, an n-type InGaAS cap layer 37 are stacked.

The mechanical and y-ching stop layer 36 is in depression mode HE.
The cap layer 37 is a layer to automatically stop etching when forming the gate of MT, and the cap layer 37 is a layer to cover the layer containing ^1 and facilitate the formation of ohmic contact. 39 is a source electrode, 40 is a drain electrode,
41 is the gate electrode of the depression mode HEMT;
2 is a gate electrode of the enhancement mode HEMT. An isolation region 38 is formed around each HEMT by implanting oxygen or ions. When the differential voltage generation layer 35 is removed, the channel created by the two-dimensional electronic debris in the channel layer 33 disappears, resulting in an enhancement mode HEMT. Broken lines in the channel layer 33 indicate two-dimensional electron debris.

Here, a structural example of this embodiment is shown below.

(1) Buffer layer 32 Material: In(352Gao, 4sAS and oxygen doped (1016CI+-3) In0, 3AIo
, 78S thickness: Jno, 52Gao, 4sAS
Layer is 100n100n, 381o, S layer to 7 is 1
00n100n Channel layer 33 Material: Ino, 52Ga□, 48AS Thickness:
100n1 00n Carrier supply layer 34 Material: In0.52AI0.46AS Thickness:
30nm Impurity: Si Impurity concentration: 1, 5 x 1018c+' (3)
Difference - Household stratification 35 Material: In□, 52Ga□, 4aAS Thickness near nm Impurity: Si Impurity concentration = 1.5x101B (to) -3 (5)
・Ching stop layer 36 Material: Ino, 52Alo, 4aAS thickness: 23 nm Impurity: Si Impurity concentration: 1.5XIQIB■-3 (6) Cap layer 37 Material: Ino, 52Gao, 4aAS thickness: 50 nm Impurity: Si impurity concentration: 1,5 x 10'am-3 In this structure, the source and drain electrodes of 39.40 are formed of AU/AUGe, and the gate electrodes of 41.42 are made of 81.
to form. Furthermore, the enhancement FET and the depression mode FET are distinguished by the presence or absence of the differential voltage generation layer 35. In dry etching using CH3Br+02 mixed scum as an etchant, InGaAs and In
Al^S is selectively etched by taking advantage of its large selective etch rate ratio when irradiated with ultraviolet rays.

The differential voltage generation layer can be etched with high precision.

In a HEMT according to another embodiment of the present invention, the buffer layer of FIG. 3 is formed of a superlattice. When AlGaAs is used as a material with a wide bandgap, the thickness of one layer due to large lattice mismatch must be made thin. Therefore, the number of calendars is increased to increase the overall resistance. For example, the buffer layer 32 is made as follows.

Material: ＾IGaAs/In, 52
Ga, 48^SO, 30,7 Thickness: 50 period strained superlattice impurity of 3 nm each layer 20 (
Oxygen atom) Impurity concentration: I X I Q16ao-3 oxygen is In
The GaAS layer may not be doped, or may be doped for convenience in the manufacturing process. Note that other points are the same as in the first embodiment.

In any of the above embodiments, instead of doping the buffer layer 32 with oxygen, it may be doped with a transition metal such as Fe, Cr, Ti, Ta, or V, such as Fe.

Furthermore, the compound semiconductor heterojunction structure according to the present invention is
Field effect transistors other than HEMT, such as ME
Can be used for 1:Jaa for SFET, MI 5FET, HET, etc.

Although the present invention has been described above along with examples, the present invention is not limited to these. For example, various changes,
It will be obvious to those skilled in the art that improvements, combinations, etc. are possible.

Effects of the Invention] As explained above, according to the present invention, an InP substrate and an I
A buffer layer with a high resistance value can be provided between the nP and the compound semiconductor layer that is lattice matched.

This makes it possible to create a compound semiconductor device that operates at high speed and suppresses the side gate effect.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a graph explaining the effect of lattice mismatch, and FIG. 3 is a sectional view of a main part of a HEMT according to an embodiment of the present invention. In the figure, 10.31 11.32 41 , 42 InP substrate buffer layer InP and lattice-matched compound semiconductor layer InGaAs channel layer n-type 1nAIAs carrier supply layer n-type]nGaAs enhancement/intergression voltage generation layer n-type 1n AIAS process Tsuching stop layer n-type 1nGaAs cap layer element isolation region source electrode drain electrode gate electrode

Claims (3)

[Claims] (1), an InP crystal substrate (10), and the InP substrate (
a first compound semiconductor layer (12) lattice-matched to (10);
In a compound semiconductor heterojunction structure comprising:
A buffer layer (11) including a second compound semiconductor layer is formed between the nP substrate and the first compound semiconductor layer, and the second compound semiconductor layer is made of a material that is lattice mismatched with the InP substrate. The film thickness and composition are selected so as not to generate dislocations due to lattice mismatch with the InP substrate and with the first compound semiconductor layer, and the effective band gap energy is A compound semiconductor heterojunction structure that is larger than an InP substrate and doped with transition metals or oxygen. (2) In a compound semiconductor heterojunction structure including an InP crystal substrate (10) and a first compound semiconductor layer (12) lattice-matched to the InP substrate, the InP substrate (10) and the first A second compound semiconductor layer (12) that is lattice mismatched with the first compound semiconductor element layer and InP.
A buffer layer (12) including a superlattice structure in which a large number of heterostructures consisting of semiconductor element layers are laminated as a unit period.
The thickness and composition of each element layer of the superlattice are determined by the In
The first compound semiconductor in a superlattice structure is selected so that no dislocation occurs due to lattice mismatch with the P substrate (10) and with the first compound semiconductor layer (12). A compound semiconductor heterojunction structure in which at least one of the element layer and the second compound semiconductor element layer is doped with a transition metal or oxygen. (3) The compound semiconductor heterojunction structure according to claim 1 or 2, wherein the first compound semiconductor is InGaAs and the second compound semiconductor is InAlAs.