JPH01225368A - Semiconductor device - Google Patents

Abstract

PURPOSE:To minimize a gate leakage current, by causing this device to be composed of the first, second, and third semiconductor layers together with a gate electrode in such a way that the third semiconductor layer has a Schottky barrier which is higher than that of the second semiconductor layer; besides, a part of the third semiconductor layer is doped with an n-type impurity and then, its layer not only supplies electrons to the first semiconductor layer but also involves the gate electrode which controls the electrochannel conductivity of the first semiconductor layer. CONSTITUTION:An non-doped Al0.48In0.52As layer 12 which performs lattice matching is formed as a buffer layer on a semi-insulating InP substrate 11 and this device allows a high purity Al0.47In0.53As layer 14 which performs lattice matching to the foregoing layer 12 to grow as an operating layer on the layer 12 and, an undoped Al0.48In0.52As layer 15 which is free from lattice matching to grow further. An Si-doped n-type (n=1X10<18>cm<-3>) Al0.3Ga0.7As layer 16 grows on the layer 15 to form a two-dimensional electron gas in a Ga0.47In0.53As layer 13. Source and drain electrodes 17 and 18 are formed on crystals obtained and then, a gate electrode 19 is formed by using Al.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to ultra-high frequency and ultra-high speed semiconductor devices, particularly field effect transistors.

[Conventional technology]

Conventional field effect transistors (hereinafter referred to as FETs) using heterojunctions with different electron affinities were described in IEI!E Electron Device Letters (IEI!E) by C, Y, Cben et al.
Electron Device Letters)
, Vol. 3, p. 152, 1982, the structure was as shown in FIG. 3.

This FET is made of high-purity GA0.47Ino, which is provided on a semi-insulating InP substrate 11 in lattice matching with the semi-insulating InP substrate 11.
So-called modulation doped Afo, 5sIno, which forms a heterojunction with the q3A 8 layer 13 and conduction band discontinuity.
The two-dimensional electron gas 14 formed by providing the 52As layer 21 is controlled by the gate electrode 19.

[Problem to be solved by the invention]

However, in conventional field effect transistors, a gate electrode is provided directly on a modulation-doped semiconductor layer that is at least partially doped with an n-type impurity.
Taking the system as an example, AI! (2) Since the Schottky barrier height φ between the nAs layer and the gate electrode is as low as about 0.6 eV, there are drawbacks such as low gate breakdown voltage and non-pinch-off characteristics with large leakage current between the source electrode and the gate electrode.

[Means to solve the problem]

The semiconductor device of the present invention includes a first semiconductor layer provided on a high-resistance substrate and serving as an electron channel layer, and a first semiconductor layer provided on the first semiconductor layer in lattice matching therewith. a second semiconductor layer having a lower electron affinity; and a second semiconductor layer provided on the second semiconductor layer and having a higher Schottky barrier than the second semiconductor layer and doped with an n-type impurity at least in part. The semiconductor device includes a third semiconductor layer that supplies electrons to the first semiconductor layer, and a gate electrode that is formed in the third semiconductor layer and controls the conductivity of the electron channel of the first semiconductor layer.

[Effect]

FIG. 2 is an energy band diagram under the gate electrode of the FET according to the present invention in a thermal equilibrium state.

Conventional A e 0.48I no, szA s/G
ao, 47I n. 53 Taking a s-based modulation doped structure as an example, Gao as the first semiconductor layer, 47
I n 6.53 A second layer with lattice matching on the S layer
By forming an AJ'0.48Ino, 5zAs layer as a semiconductor layer, a good heterointerface with a predetermined band discontinuity can be obtained. For example, if an Aex Ga1-x As layer is formed as the third semiconductor layer having a higher Schottky barrier than the third semiconductor layer, Aex Gal-x As has a Schottky barrier height of 1.0 at x=0.3. Since it has a high value of OeV, it is possible to reduce gate leakage current, improve reverse breakdown voltage, and improve forward turn-on voltage. The effect of lattice mismatch between the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer on the active layer is that compared to forming the third semiconductor layer directly on the first semiconductor layer, This can be reduced by the presence of the semiconductor layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Non-doped A 120.48I n 0.52A is lattice matched to the semi-insulating InP substrate 11 by the MBE method.
The s-layer 12 is provided as a buffer layer with a thickness of 1 μm, and high-purity AfO, 47InO, 5 lattice-matched to the s-layer 12 is provided on the s-layer 12 as a buffer layer.
The 3AS layer 14 is grown to a thickness of 1 μm as an active layer,
Furthermore, lattice-matched non-doped A e 6.4B
Ino, 52A 9 layers 15 are grown to a thickness of 3 nm. On top of this, Si-doped n-type (n=lX1018
cm-3) Affn,s Ga0.7 As layer 16 is grown to a thickness of 30 nm and Gao,4? I no, H
A two-dimensional electron gas is formed in the As layer 13. A source electrode 17 and a drain electrode 18 made of AuGe/Ni are formed on the obtained crystal by a usual method, and then Af
A gate electrode 19 is formed using.

The obtained FET has a lattice-matched Gao47I n
6. A two-dimensional electron gas is formed at a good interface between g2A S and Aln4sI nO, 52AS, and the gate electrode 19 is made of A e o, 3 G ao7A with a high barrier height.
Since it is formed on eight layers 16, a high-speed, high-frequency FET with low gate leakage current and high breakdown voltage can be realized.

FIG. 4 shows the IV characteristics between the source and gate electrodes according to the present invention together with a conventional example. As is clear from FIG. 4, a reduction in gate leakage current, an increase in reverse breakdown voltage, and an increase in forward turn-on voltage were observed, and the FET also operated well.

In this example, the third semiconductor Affx Ga1-X
Although the AS composition ratio x=0.3, this can be changed or the film thickness of each layer can be changed.

Moreover, it is not limited to the Af I nAs/I nGaAs system, but can be applied to other systems as well.

〔Effect of the invention〕

The present invention has low gate leakage current, high breakdown voltage,
Good high frequency and high speed FET with two-dimensional electron channel
The effect is that it can be realized.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an embodiment of the present invention, FIG. 2 is an energy band diagram in a thermal equilibrium state under the gate electrode of the semiconductor device shown in FIG. 1, and FIG. 3 is a sectional view of an example of a conventional FET.
FIG. 4 is a characteristic diagram showing the current-voltage relationship between the gate and source electrodes of the present invention and the conventional example. 11... Semi-insulating InP substrate, 12... Non-doped Ae InAs layer, 13-... High purity Ga InA
s layer, 14... two-dimensional electron gas, 15... AN I
nAs layer, 16...-n type Aj'GaAs layer, 17
-... Source electrode, 18... Drain electrode, 19...
- Gate electrode, 21... n-type A47I nGa layer.

Claims (1)

[Claims] A first semiconductor layer provided on a high-resistance substrate and serving as an electron channel layer, and a second semiconductor layer provided on the first semiconductor layer in lattice matching with the first semiconductor layer and having a smaller electron affinity than the first semiconductor layer. a semiconductor layer provided on the second semiconductor layer, which has a higher Schottky barrier than the second semiconductor layer and is doped with an n-type impurity at least in part, and which directs electrons to the first semiconductor layer. 1. A semiconductor device comprising: a third semiconductor layer; and a gate electrode formed on the third semiconductor layer to control conductivity of an electron channel of the first semiconductor layer.