JP2765607B2 - Tunnel effect type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tunnel effect type semiconductor device such as a tunnel diode having a tunnel effect by a lateral pn junction.

[0002]

2. Description of the Related Art Conventionally, GaAs, AlGaAs, Si or G is formed on a conductive semiconductor substrate by using various dopants.
By forming a pn junction in the crystal growth direction, for example, a direction perpendicular to the semiconductor substrate (longitudinal direction) by a crystal growth method such as a molecular beam epitaxial method, a tunnel diode called a so-called Esaki diode is formed. I have made it.

[0003]

In a tunnel diode, it is important to increase a tunnel current that can be actually controlled. The tunnel current is generally given by a product of a tunnel probability and a carrier supply function. In the conventional junction between the heavily doped n-type and p-type bulk materials, the potential energy changes sharply, and the depletion layer width becomes thin enough to allow electrons to tunnel (for example, less than 100 °). , The tunnel probability increases. However, since it is a bulk material, the number of states per unit energy is low from the state density function of the carriers of electrons or holes, and the number of electrons that can contribute to the tunnel from the highly doped conduction band to the valence band ( That is, the supply function) is small, and the tunnel current density is small. Therefore, there has been a problem that large current amplification cannot be performed and large power cannot be obtained.

Further, since the distribution of the number of states with respect to the energy of electrons and holes is relatively wide, the negative differential resistance is small,
As a result, there is a problem that high-speed switching characteristics of several tens of picoseconds or less cannot be obtained.

Further, since the conventional tunnel diode is a device in which a current flows in a vertical direction, a device for driving a current in a horizontal direction (horizontal direction) is used.
There has been a problem that high-frequency devices such as MESFETs and HEMTs cannot be formed on the same semi-insulating semiconductor substrate.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, to obtain a high output by performing a large current amplification, and to obtain a faster switching characteristic than a conventional one, and to obtain a semi-insulating property. An object of the present invention is to provide a tunnel effect type semiconductor device which can be formed on a semiconductor substrate.

[0007]

SUMMARY OF THE INVENTION A tunnel effect type semiconductor device according to the present invention is characterized in that an electron is grown by a crystal growth method on a semi-insulating compound semiconductor substrate having a step formed so that a slope is formed between flat portions. A compound semiconductor layer doped with an amphoteric impurity as a planar doped layer, a modulation doping layer, a multiple quantum well layer, or a semiconductor superlattice type well layer is formed so that the state density of the compound increases. By forming a contact layer and an electrode made of a semiconductor, a lateral direction p-n is formed between a flat portion and a slope portion of the active layer formed by the step due to a difference in conduction type.
It is characterized in that a junction is formed and a tunnel effect appears in the lateral pn junction.

[0008]

In the semiconductor device configured as described above,
The present inventor can increase the density of states of electrons by doping a narrower region with an amphoteric impurity having a very low impurity concentration, a high purity, and a relatively high doping amount equal to or more than a predetermined value. As described below, it has been found that a tunnel effect can be caused in the semiconductor device according to the present invention.

In the semiconductor device having the above configuration,
By applying a forward voltage to the lateral pn junction, when a forward current flows through the pn junction, the conduction band sub-band is shifted from the conduction band sub-band to the valence band sub-band at the pn junction. Electrons are tunneled into the band, and a tunnel current flows between the pn junctions, and the current-voltage characteristic has a negative differential resistance.

Generally, the number of electrons flowing in the pn matching portion depends on the energy distribution of the number of states of the carrier, and the energy distribution function of the number of states of the carrier is a product of the density of states of the carrier and the Fermi distribution function. expressed.

The major difference between the bulk semiconductor used in the conventional example and the quantum structure such as the planar doped layer, the modulation doping layer, the multiple quantum well layer and the semiconductor superlattice type well layer which are the active layers used in the present invention is as follows. As detailed below,
That is, the density of states functions are different from each other. The density of states function of a bulk semiconductor is a parabolic function proportional to the square root of the electron energy. On the other hand, the density of states of carriers in a one-dimensional confined structure such as a triangular potential well layer, a multiple quantum well layer, or a semiconductor superlattice type well layer having a planar doping layer, a modulation doping structure, is a step function or a pseudo step. Function. Here, in confinement in a two-dimensional direction such as a quantum wire, the density of states is inversely proportional to the square root of the energy of electrons. For example, confinement in a three-dimensional direction such as a quantum box becomes a δ function, and the number of states of holes and electrons becomes infinite or zero with respect to energy.
When the Fermi level is placed at the highest energy position where the density of states function is 0, the number of states of the structure confined in the one-dimensional direction is 10 times or more that of the bulk semiconductor, and 100 times or more for the quantum wires of the two-dimensional quantum well Becomes Therefore, the number of carrier states per unit energy greatly depends on the state density function.

As described above, a pn junction used in many conventional optoelectronic devices is a junction between p-type and n-type conductivity type materials having a state density function of a bulk semiconductor. Therefore, there is a problem that the number of carrier states is low as described above.

On the other hand, in the configuration of the tunnel effect type semiconductor device according to the present invention, since the lateral pn junction is realized by using the above quantum structure, the number of carrier states is much larger than that of the conventional bulk semiconductor. In addition, bonding of materials having p-type and n-type conductivity can be realized. This has the advantage that the electrical characteristics of a conventional pn junction device can be dramatically improved.
In the device according to the present invention, the electrical characteristics of an Esaki diode in which the tunnel effect appearing at the heavily doped p-type and n-type junctions is applied to the device can be greatly improved.

As described above, the number of electrons tunneling through the pn junction in the sub-band or mini-band is greatly increased, and a large tunnel current density is obtained as compared with the tunnel phenomenon in the conventional bulk semiconductor. Thus, a high-current driven high-output device can be realized. Conversely, the tunnel probability may be reduced by increasing the number of electrons to be tunneled, and increasing the effective band gap, which is the energy difference between the electron sub-band and the hole sub-band. it can. That is, by increasing the band gap, the diffusion current can be reduced, thereby increasing the peak / valley ratio, which is one of the electrical performance characteristics of the tunnel diode. Further, since the distribution of the number of states of electrons and holes with respect to energy becomes narrow, a slight change in the forward applied voltage causes a large change in the tunnel current, so that a large negative differential resistance can be obtained.

On the other hand, a conventional tunnel diode using a bulk semiconductor has a relatively low operating voltage. The applied voltage value indicating the maximum of the tunnel current is generally determined by the maximum energy position of the number of states of the carriers. As described above, the state functions of the conventional bulk semiconductor and the quantum structure used in the present invention are significantly different. In an Esaki diode using a pn junction in a sub-band or mini-band, the forward voltage indicating the maximum tunnel current is lower than that of a conventional example because the carrier state function is substantially a step function or a δ function. Tend to be higher than that of the bulk semiconductor. This is advantageous in device design and integration in that large power can be obtained.

Also, by applying a control voltage to the gate electrode formed on the upper surface of the pn junction, the energy potential of holes and electrons in the p-type region or the n-type region is changed. This makes it possible to realize a tunnel effect type semiconductor device such as a tunnel transistor which changes the tunnel probability and supply function of electrons and modulates the tunnel current at a high speed by the voltage control method.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of a lateral p-type transistor having a planar doped structure according to the present invention.
It is a longitudinal section showing the structure of a -n junction type tunnel diode.

In the tunnel diode of the planar doped structure according to the first embodiment, the slope portion 1 is located between the flat portions 1a and 1b.
semi-insulating GaAs with steps formed so that c is formed
On the substrate 1, the GaAs layer 2 of high purity, which is an impurity concentration less than 10 ¹⁴ cm ^-3 is grown, and the less growth is interrupted doping only subjected to thickness 100 Å, preferably planar doped layer of less than 50Å after 3 was formed, high-purity GaAs of even less than an impurity concentration of 10 ¹⁴ cm ^-3
The layers 4a, 4b and 4c are formed, and finally the GaAs contact layers 5a, 5b and 5c doped with Si are grown, and the n-type ohmic electrode 7 is formed over the slope 5c and the lower flat 5b. 5a is characterized in that a p-type ohmic electrode 6 is formed, thereby forming a lateral pn junction at the step and causing a tunnel effect at the pn junction.

As shown in FIG. 1, the (111) A plane which is the upper surface of the semi-insulating GaAs substrate 1 has a plane orientation (31).
1) Step processing is performed by a wet etching method so as to form the slope portion 1c having A, whereby flat portions 1a and 1b having a plane orientation (111) A are formed on both sides of the slope portion 1c. Si, which is an amphoteric impurity,
It can be both an acceptor and a donor depending on the crystal growth conditions and the plane orientation of the substrate. Therefore, the Si dopant is added to the GaAs substrate 1 having the step by the molecular beam epitaxy method.
1) A flat portion of the A surface becomes an acceptor and the plane orientation (3
11) A high-purity GaAs layer 2 having an impurity concentration of 10 ¹⁴ cm ⁻³ having a thickness of 5
2,000 and then interrupt the growth, Si
After doping only with a doping amount of 5 × 10 ¹² cm ⁻² to form a planar doped layer 3 having a thickness of less than 100 °, preferably less than 50 °, the impurity concentration is further reduced by a molecular beam epitaxy method to less than 10 ¹⁴ cm ^−3. GaAs layers 4a, 4b, 4c with high purity and a thickness of 1000 °
Finally, 200 ° GaAs contact layers 5a, 5b, 5c doped with Si were grown by molecular beam epitaxy.

Finally, the flat portion 5a of the p-type GaAs contact layer is formed by photolithography and vacuum evaporation.
On top, a p-type ohmic electrode 6 made of Zu / Ni / Au
Is formed, and AuGe / Ni / A is formed from the slope 5c of the n-type GaAs contact layer to the lower flat surface 5b.
An n-type ohmic electrode 7 made of u was formed and alloyed. Next, a part of the contact GaAs layers 5a and 5b between the ohmic electrodes 6 and 7 was removed by etching to obtain the diode device shown in FIG. And
A DC power supply 50 is connected between the ohmic electrodes 6 and 7 in the forward direction, and a predetermined voltage is applied in the forward direction.
The applied voltage-current characteristics shown in FIG.
As is clear from FIG. 2, it is possible to obtain a tunnel current and to have a negative differential resistance unique to the tunnel diode.

Si, which is an amphoteric impurity, becomes both an acceptor and a donor depending on crystal growth conditions and substrate plane orientation. From this, when the growth conditions are such that the Si dopant becomes an acceptor in the flat portion of the plane orientation (111) A and becomes a donor in the slope of the plane orientation (311) A, the triangular potential well of the planar doped layer 3 in the flat portion becomes The hole gas accumulates, and electrons accumulate in the triangular potential well of the planar doped layer 3 on the slope. Therefore, a lateral pn junction is formed between the planar doped layer 3 in the flat portion and the planar doped layer 3 in the inclined portion.

In the diode of this embodiment, since only the Si is doped at a doping amount of 5 × 10 ¹² cm ⁻² to form the planar doped layer 3 having a thickness of less than 100 °, an extremely thin region having a thickness of less than 100 ° is formed. Since the carriers are confined in the semiconductor, a quantum effect occurs, and the carrier supply function, that is, the state density of electrons per unit energy is increased as compared with the conventional bulk semiconductor. Therefore, even if the tunnel probability is the same as that of the bulk semiconductor, the tunnel current density increases. Therefore, a tunnel diode having current driving characteristics and high output characteristics that can be driven with a large current as compared with the conventional example can be obtained.

<Second Embodiment> FIG. 3 shows a second embodiment of the present invention.
FIG. 2 is a longitudinal sectional view showing a structure of a junction type tunnel transistor.

The modulation-doped structure type tunnel transistor of the second embodiment has a semi-insulating Ga with a step formed so that a slope 10c is formed between the flat portions 10a and 10b.
On the As substrate 10, carrier accumulation layers 11a and 11 made of high-purity GaAs having an impurity concentration of less than 10 ¹⁴ cm ^−3.
b, 11c to form, then undoped Al _{0. 3} G
a _{0. 7} comprising at As spacer layer 17a, to form 17b, a 17c, further, Al doped with _{Si 0. 3 Ga 0. 7} As
After the carrier supply layers 12a, 12b, and 12c are formed, the GaAs contact layers 13a, 13b, and 13c are formed.
And an n-type ohmic electrode 16 is formed over the slope portion 13c and the lower flat portion 13b.
a is characterized in that a p-type ohmic electrode 15 is formed, and a gate electrode 14 is formed on the upper surface of a pn junction located between the carrier supply layers 12a and 12c. Thereby, a lateral pn junction is formed at the step and a tunnel effect appears at the pn junction.

As shown in FIG. 3, the (111) A plane, which is the upper surface of the semi-insulating GaAs substrate 10, has a plane orientation of (3).
11) Step processing is performed by a wet etching method so as to form the slope 10c having A, whereby flat portions 10a and 10b having a plane orientation (111) A are formed on both sides of the slope 10c. Then, the GaAs substrate 10 having a step, a carrier accumulation layer 11a in which the impurity concentration is in a high-purity GaAs less than 10 ¹⁴ cm ^-3, 11b, and 11c thickness by molecular beam epitaxy of 5
000Å only grown, then, Al ₀ undoped by molecular beam epitaxy. ₃ Ga _0. Made at ₇ As spacer layer 17a, 17b, 17c was only grown to a thickness of 60 Å, and the Si molecular beam epitaxy 3 ×
10 ¹⁸ cm ^-3 or more 1 × Al ₀ doped with doping amount of less than _{^{10 19 cm -3. 3 Ga 0}} . 7 carrier supply layer 12a having a thickness of 1000Å with As, 12b, 12c is formed at the end 5 × 10 ¹⁸ cm of Si by molecular beam epitaxy
Doped G doped amount of less than ^-3 1 × 10 ¹⁹ cm ^-3
contact layer 13a, 1 having a thickness of 200.degree.
3b and 13c were grown. The carrier accumulation layers 11a, 11b, 11c formed as described above and the spacer layer 1
7a, 17b, 17c and carrier supply layers 12a, 12
b and 12c constitute a so-called modulation doped layer.

Finally, the flat portion 13 of the p-type GaAs contact layer is formed by photolithography and vacuum evaporation.
a, a p-type ohmic electrode 15 made of Zu / Ni / Au is formed, and the AuGe / n-type GaAs contact layer is formed from the slope 13c to the lower flat surface 13b.
An n-type ohmic electrode 16 made of Ni / Au was formed, and the electrode was alloyed. Next, ohmic electrodes 15,
A part of the contact layers 13a and 13c between the layers 16 is removed by wet etching, and a gate electrode 14 made of Au / Ti is formed on the pn junction located between the carrier supply layers 12a and 12c by photolithography and vacuum evaporation. Forming
The device of the transistor of FIG. 3 was obtained. By connecting a DC power supply 52 between the ohmic electrodes 15 and 16 to apply a forward voltage and connecting another DC power supply 51 between the gate electrode 14 and the n-type ohmic electrode 16, the p-type A forward voltage is applied to the ohmic electrode 15 and a reverse voltage is applied to the n-type ohmic electrode 16.

In the transistor configured as described above, when the Si dopant is used under the growth conditions of being an acceptor in the flat portion of the (111) A plane orientation and being a donor on the (311) A slope, the flat portion is obtained. Spacer layer 1
The hole gas accumulates at the interface between the carrier accumulation layer 11a and 7a, while the electron gas accumulates at the interface between the spacer layer 17c and the carrier accumulation layer 11c on the slope. Thereby, the flat portion 17a of the spacer layer in the modulation doping layer is formed.
A lateral pn junction is formed between the gate and the slope 17c.

In the transistor, the carrier supply layers 12a to 12c are doped with Si at a doping amount of 3 × 10
^By doping with an extremely high doping amount of ¹⁸ cm ^-3 or more and lowering the crystal growth temperature, the energy level at the pn junction interface can be changed sharply, whereby
A tunnel effect can be obtained.

Generally, a tunnel current is represented by a product of a tunnel probability function and a carrier supply function, that is, a density of states of electrons per unit energy. The tunnel probability depends on the effective band gap, electric field, and effective mass, and the electron density of states function is determined by the quantum well structure. Therefore, the tunnel current can be changed by changing these physical quantities. In the transistor of this embodiment, the gate electrode 14 formed above the pn junction
The quantum structure in the modulation doped layer is distorted by the electric field to change the position of the quantum level, using an electric field control method of controlling an electric field by changing a DC voltage applied to the substrate. As a result, the carrier supply function changes, and the tunnel current changes. That is, the tunnel current flowing through the pn junction can be modulated by the voltage applied to the gate electrode 14 by the tunnel effect.

The tunnel transistor of the present embodiment has a first
As in the embodiment of the present invention, a large current can be amplified, a large power can be obtained, and a large negative differential resistance can be obtained as compared with the conventional example, so that a high-speed switching characteristic can be obtained. .

<Third Embodiment> FIG. 4 shows a lateral pn junction type tunnel transistor having a multiple quantum well structure according to a third embodiment of the present invention, which is a third embodiment of the present invention. It is a longitudinal cross-sectional view which shows the structure of.

The multiple quantum well structure type tunnel transistor of the third embodiment has a semi-insulating G in which a step is formed so that a slope 20c is formed between the flat portions 20a and 20b.
After an undoped GaAs layer 21 is formed on an aAs substrate 20 and an Al _0.4 Ga _0.6 As layer 22 is formed, a one-period well layer 30 is formed on a GaAs layer 31 doped with Si and an undoped layer formed thereon. Al _0.3 Ga _0.7 As layer 32
15-period multiple quantum well layers 23a, 23b,
23c, and further, Al _0.4 not doped with Si
After the Ga _0.6 As barrier layer 24 is formed, GaAs contact layers 25a, 25b, 25c doped with Si are grown, and the p-type GaAs contact layers 25a, 25b, 25c are formed over the slope 25c and the lower flat portion 25b.
An ohmic electrode 28 is formed, an n-type ohmic electrode 27 is formed on the flat portion 25a, and a barrier layer 24 is formed.
The gate electrode 26 is formed on the upper surface of the pn junction. Thereby, a lateral pn junction is formed at the step and a tunnel effect appears at the pn junction.

As shown in FIG. 4, the plane orientation (31) is relative to the (100) plane which is the upper surface of the semi-insulating GaAs substrate 20.
1) Step processing is performed by a wet etching method so as to form the slope portion 20c having A, whereby flat portions 20a and 20b having a plane orientation (100) are formed on both sides of the slope portion 20c. Then, Al _0.4 after the impurity concentration is grown by a thickness 2000Å high purity GaAs layer of less than 10 ¹⁴ cm ^-3 by molecular beam epitaxy on GaAs substrate 20, which is not doped with a step
A Ga _0.6 As layer 22 is formed. Next, one cycle of the well layer 30 is doped with Si at a dose of 5 × 10 ¹⁸ cm ⁻³ or more and 1 × 1
GaAs layer 3 doped at less than 0 ¹⁹ cm ^-3 and having a thickness of 30 °
A 15-period multi-quantum well layer 23a, 23b, 23c composed of a 1 and an undoped Al _0.3 Ga _0.7 As layer 32 having a thickness of 200 ° formed thereon is formed. Then
Al _0.4 G not doped by molecular beam epitaxy
a _0.6 As barrier layer 24 is grown to a thickness of 1000 ° and finally GaAs doped with Si by molecular beam epitaxy.
s Contact layers 25a, 25b, 25c have a thickness of 200
Only grown.

Finally, by using photolithography and vacuum deposition, Zu / Ni / A is formed from the slope to the flat portion 25b of the p-type GaAs contact layer 25c.
In addition to forming a p-type ohmic electrode 28 made of u, an n-type ohmic electrode 27 made of AuGe / Ni / Au is formed on the upper flat surface 25a of the n-type GaAs contact layer.
Was formed and the electrodes were alloyed. Next, the GaAs contact layers 25a, 25 between the ohmic electrodes 27, 28
c is partially removed by etching, and p-n on the barrier layer 24 is removed.
A gate electrode 26 made of Au / Ti was formed on the junction by photolithography and vacuum deposition to obtain the transistor device shown in FIG. Then, a DC power supply 52 is connected between the ohmic electrodes 27 and 28 to apply a reverse voltage, and another DC power supply 51 is connected between the gate electrode 26 and the p-type ohmic electrode 28, so that the n-type Applying a reverse voltage to the ohmic electrode 27, and
A forward voltage is applied to the p-type ohmic electrode 28. Note that these voltage application directions may be reversed.

In the transistor of the third embodiment configured as described above, the AlGaAs barrier layer 24, the AlGaAs layer 32 and the GaAs layer 31 located immediately below the AlGaAs barrier layer 24.
In this case, Si, which is an amphoteric impurity, becomes a donor in the flat portion of (100) and becomes an acceptor in the (311) A slope portion, thereby performing the crystal growth condition, as shown in FIG. The electrons 60 are accumulated in the flat portion 23b, and the holes 70 are accumulated in the slope portion 23c. Thereby, the flat part 23a and the slope part 2 of the multiple quantum well layer are formed.
3c forms a lateral pn junction between the flat portion 23b and the slope portion 23c.

In the transistor, in the multiple quantum well layers 23a to 23c, the doping amount of Si is 5 × 10
^By doping with an extremely high doping amount of ¹⁸ cm ^-3 or more and lowering the crystal growth temperature, the energy level at the pn junction interface can be changed sharply, whereby
A tunnel effect can be obtained.

As is known, subbands are formed in the multiple quantum well layer, and a tunnel current flows in the conduction band side subband and the valence electron side subband. When a predetermined DC voltage is applied to the multiple quantum well layer, the shape of the well is distorted, the energy level of the sub-band changes, and the effective band gap decreases. Since the tunnel probability depends on the effective band gap, the electric field, and the effective mass, the tunnel probability can be changed by reducing the effective band gap by changing the subband. In the transistor according to the present embodiment, the shape of the quantum well is changed by using an electric field control method in which an electric field is controlled by changing a DC voltage applied to the gate electrode 26 formed above the p-n junction. Change the position of the place. As a result, the carrier supply function changes, and the tunnel current changes. That is, the tunnel current flowing through the pn junction can be modulated by the voltage applied to the gate electrode 26 by the tunnel effect.

The tunnel transistor of this embodiment has a first
Similarly to the second embodiment, a large current can be amplified, a large power can be obtained, and a large negative differential resistance can be obtained as compared with the conventional example, so that high-speed switching characteristics can be obtained. be able to.

In the third embodiment, Al _0.3 Ga _0.7 As is used as the layer 32 in the one-period multiple quantum well layer 30.
However, the present invention is not limited to this, and AlAs may be used.

In the above third embodiment, the multiple quantum well layers 23a, 23b and 23c are formed. However, the present invention is not limited to this, and the semiconductor superlattice type A well layer may be formed. In this case, the same operation as in the third embodiment can be obtained. That is, an undoped AlAs layer having a thickness of 6 ° is formed.
A 200-period semiconductor superlattice-type well layer with a total thickness of 30 ° is formed using GaAs doped with i at a doping amount of 5 × 10 ¹⁸ cm ⁻³ , and an Al _0.5 with a thickness of 1000 ° which is not doped by molecular beam epitaxy. A Ga _0.5 As layer is grown. In the case of the GaAs / AlAs semiconductor superlattice structure, a mini band is formed by a quantum effect. Si, which is an amphoteric impurity, tends to be a donor in a flat portion having a plane orientation of (100) and electrons are accumulated in the GaAs well layer in the flat portion. On the other hand, Si tends to be an acceptor in a slope portion. Holes accumulate. A junction with p-type and n-type minibands is formed just in the horizontal direction of the flat part and the slope part.

In the above embodiment, the GaAs layer and the A
Although the lGaAs layer is grown by molecular beam epitaxy, the present invention is not limited to this, and may be formed by other crystal growth methods such as metal organic chemical vapor deposition or liquid phase growth.

[0043]

As described above in detail, according to the tunnel effect type semiconductor device of the present invention, a crystal is formed on a semi-insulating compound semiconductor substrate having a step formed such that a slope is formed between flat portions. Forming a compound semiconductor layer doped with an amphoteric impurity as a planar dope layer, a modulation doping layer, a multiple quantum well layer, or a semiconductor superlattice type well layer so as to increase the density of states of electrons by the growth method, By forming a contact layer made of a compound semiconductor and an electrode thereon, the lateral direction pn between the flat portion and the slope portion of the active layer formed by the step due to the difference in conduction type. A junction is formed and a tunnel effect appears at the lateral pn junction. Therefore, it has the following specific advantages.

(A) Since the active layer is formed so as to increase the state density of electrons, the number of electrons can be increased and the tunnel current density can be increased as compared with the conventional example. Amplification can be performed. (B) Further, since the active layer is formed so as to increase the density of states of electrons, the distribution of the number of states of electrons and holes with respect to energy is narrowed, and the tunnel current is slightly changed by the applied voltage in the forward direction. Greatly changes, so that a large negative differential resistance can be obtained as compared with the conventional example. Therefore, it is possible to obtain high-speed switching characteristics as compared with the related art. (C) Since the semiconductor device according to the present invention can be formed on a semi-insulating semiconductor substrate, MOS, HESFET,
Alternatively, it can be formed simultaneously with HEMT or the like.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a structure of a lateral pn junction type tunnel diode having a planar doped structure according to a first embodiment of the present invention.

FIG. 2 is a graph showing current characteristics with respect to an applied voltage of the tunnel diode of FIG.

FIG. 3 is a longitudinal sectional view showing a structure of a lateral pn junction type tunnel transistor having a modulation doping structure according to a second embodiment of the present invention.

FIG. 4 is a longitudinal sectional view showing the structure of a lateral pn junction type tunnel transistor having a multiple quantum well structure according to a third embodiment of the present invention.

5 is an energy level diagram of each layer for explaining the operation of the tunnel transistor of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating GaAs substrate, 1a, 1b ... Flat part of GaAs substrate, 1c ... Slope part of GaAs substrate, 2 ... GaAs
Layers, 3 ... planar doped layers, 4a, 4b, 4c ... GaAs
s layer, 5a, 5b, 5c ... GaAs contact layer, 6 ...
p-type ohmic electrode, 7 ... n-type ohmic electrode, 10 ...
Semi-insulating GaAs substrate, 10a, 10b ... flat portion of GaAs substrate, 10c ... sloped portion of GaAs substrate, 11a, 1
1b, 11c: carrier accumulation layer, 17a, 17b, 17
c: spacer layer, 13a, 13b, 13c: contact layer 14: gate electrode, 15: p-type ohmic electrode, 16
... n-type ohmic electrode, 20 ... semi-insulating GaAs substrate,
20a, 20b: flat portion of GaAs substrate, 20c: Ga
Slope of As substrate, 21: GaAs layer, 22: Al _0.4
Ga _0.6 As layer, 23a, 23b, 23c: multiple quantum well layer, 24: Al _0.4 Ga _0.6 As barrier layer, 25a, 25
b, 25c: GaAs contact layer, 26: gate electrode, 27: n-type ohmic electrode, 28: p-type ohmic electrode, 50, 51, 52: DC power supply.

Continuation of front page (56) References JP-A-2-15687 (JP, A) L. MILLER, "Later AL P-N JUNCTION FORMATION IN GAAS MO LECULAR BEAM EPITA XY BY BY CRYSTAL PLAN E DEPENDENT DOPING G", APPL. PHYS. LETT. 47 (12), December 15, 1985, p. 1309- 1311 Makoto Inai, Teiji Yamamoto, Mototada Fujii, Toshihiko Takebe, Norio Kobayashi, "EFFECT OF GA ADATOM NIGRATION ON ELECTRICAL C CHARACTERISTICS OF LATERAL P-N INTERNAL ACCESS LOGON GLOBAL SON GOVERN SON GOVERN SON GOVERN SON GALLON SON GOVERN SON GOVERN SON GOVERN SON GOVERNAL 19TH INT ERNATIONAL SYMPOSI UM ON GALLIUM ARSE NIDE AND RELATED C OMPOUNDS ABSTRACT S, 19th Organizing Committee of Gallium Arsenide Compound Semiconductor International Symposium, June 29, 1992, p. 57 (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/88 H01L 21/203 H01L 21/205 H01L 29/68

Claims (1)

(57) [Claims] An active layer is formed on a semi-insulating compound semiconductor substrate on which a step is formed so that a slope is formed between flat portions, so that a state density of electrons is increased by a crystal growth method. By forming a compound semiconductor layer doped with amphoteric impurities as a layer, a modulation doping layer, a multiple quantum well layer, or a semiconductor superlattice type well layer, and forming a contact layer and an electrode made of a compound semiconductor thereon, A lateral pn junction is formed between a flat portion and a slope portion of the active layer formed by the step due to a difference in conduction type, and a tunnel effect appears at the lateral pn junction. A tunnel effect type semiconductor device characterized by the above-mentioned.