JP2000138235A - Field effect transistor and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of a step produced by mesa etching by providing a specific oxidized AlGaAs layer between a buffer layer and an active layer and reducing the parasitic capacitance, thereby eliminating decrease in the resistance in the buffer layer. SOLUTION: A recess G having flat bottom is formed in the surface of a high resistance silicon substrate 1 by anisotropic etching, for example, using a mask 2 of an insulating film. The mask 2 is then removed and thin films 3-6 of a compound semiconductor are grown heteroepitaxially on the entire surface of the substrate 1 and the surface is polished to expose and planarize the Si surface at the upper part of a terrace. Subsequently, an AlxGa1-xAs layer 4 is oxidized to obtain an AlxGa1-xAs layer (0.9<=x<=1) oxide layer 4'. Thereafter, an insulation film 8 is formed on the entire surface and subjected to continuous etching, including a contact layer 6 and a part of an active layer 5 using a mask for gate pattern. Finally, a gate metal film 9 is formed, the insulation film 8 is removed through patterning and a source/drain metal 10 is deposited.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor used in a microwave band, a millimeter wave band, and the like, and a method of forming the same.

[0002]

2. Description of the Related Art A conventional method for forming a field effect transistor using a heteroepitaxial compound semiconductor will be described with reference to FIG.

First, as shown in FIG. 1A, MOCVD, VPE, MB
Compound semiconductor thin films 22 to 24 such as gallium arsenide, aluminum gallium arsenide, and indium phosphide are heteroepitaxially grown by the E method or the like. For example, in a MESFET, the high resistance buffer layer 22 has a carrier density of 1 × 1
An active layer 23 of 0 ¹⁶ to 10 ¹⁷ cm ⁻³ is grown in the order of a contact layer 24 of 1 × 10 ¹⁸ cm ⁻³ or more. The thickness and carrier density of each layer are selected to be optimal according to the desired device characteristics. This growth step is continuously performed by the same apparatus.

Next, as shown in FIG. 1B, mesa separation between elements is performed. Photolithography of the mesa separation pattern is performed, and the elements are electrically separated by wet etching of a sulfuric acid or the like up to the middle of the contact layer 24, the active layer 23, and the buffer layer 22.

[0005] Next, as shown in FIG.
An insulating film 25 such as ₂ is formed to a thickness of about 100 to 500 nm by a sputtering method, a CVD method, or the like.

Next, as shown in FIG. 1D, a gate pattern mask 26 is formed of a photoresist, and using this, an insulating film 25, a contact layer 24, and an active layer 2 are formed.
3 is continuously etched. At this time, the contact layer 24 is etched so as to be over-etched by about 1 μm so that the gate does not contact the contact layer. The etching of the contact layer 24 is preferably wet etching suitable for over-etching.

Next, as shown in FIG. 1E, a metal film 27 serving as a gate is formed by a vapor deposition method, and lift-off is performed. The metal film has a laminated structure of a barrier metal such as Ti and a low-resistance metal such as Al, and has a thickness of 100 to 500 nm.

Next, as shown in FIG. 1F, a mask (not shown) for a source / drain pattern is formed with a photoresist. Thus, after the insulating film 25 is patterned and removed, a metal 28 serving as a source / drain is formed by a vapor deposition method or the like, and lift-off is performed. This metal is Au / A
It is a laminated film of uGe or the like. Finally, heat treatment is performed so that the source / drain metal becomes an ohmic contact with the contact layer. The heat treatment is performed, for example, in a nitrogen atmosphere at 450.
C. for about 8 minutes. Also, if necessary, Au plating is performed on the gate electrode and the source / drain electrodes to form an A layer having a thickness of several μm.
A u electrode is formed to improve power durability.

[0009]

However, in the field-effect transistor manufactured by the above method, silicon atoms are auto-doped from the substrate in the compound semiconductor buffer layer 22 during growth, and it is difficult to increase the resistance. Therefore, the electrodes are formed on the low-resistance buffer layer, and the insulation is not sufficient, and the high-frequency characteristics deteriorate.

The step due to the mesa etching is usually 0.5 μm or more, and the step causes a reduction in the yield due to the thinning or disconnection of the wiring and the variation in the characteristics between the transistors.

In Japanese Patent Application Laid-Open No. 3-49239, after bonding a GaAs substrate including an element forming region and a Si substrate,
By polishing and removing the GaAs substrate from the back surface, it is possible to eliminate steps due to mesa etching and to increase the resistance of the buffer layer. However, in this method, an expensive compound semiconductor substrate must be used, which is costly. Further, it is inevitable that polishing damage is left on the element surface, and the state of the interface with the electrode is deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and eliminates the low resistance of the buffer layer, does not cause a step due to the mesa etching, and thus has a disconnection of wiring and a variation in performance. It is an object of the present invention to provide a method for forming a field-effect transistor which does not bring about.

[0013]

In order to achieve the above object, in the field effect transistor according to the first aspect, a concave portion is provided on one main surface side of a silicon substrate, and a buffer layer and an active layer are provided in the concave portion. in the field effect transistor having a gate electrode and source and drain electrodes on the active layer, it is oxidized between the buffer layer and the active layer was Al _x
A Ga _1-x As (0.9 ≦ x ≦ 1) layer was provided.

In the field effect transistor, it is preferable that the oxidized Al _x Ga _{1 -x} As layer has a thickness of 500 ° or more.

According to a third aspect of the present invention, there is provided a method for manufacturing a field effect transistor, comprising: providing a buffer layer and an active layer on a silicon substrate; and providing a gate electrode and source / drain electrodes on the active layer. In the method, a concave portion is formed on one main surface side of the silicon substrate, and a GaAs layer serving as a buffer layer is
Al _x Ga _{1 -x} As having the above thickness (0.9 ≦ x ≦
1) forming a layer and a semiconductor layer to be an active layer, and polishing the semiconductor layer protruding from the inside of the concave portion to form the Al _x
A part of the Ga _1-x As layer is exposed and wet-oxidized, and then the gate electrode and the source / drain electrodes are formed.

[0016]

SUMMARY OF] By configuring as above, the active layer and the contact layer to be electrically isolated from the silicon substrate by Al _x Ga _1-x As layer oxidized, it is possible to reduce the parasitic capacitance, high-frequency characteristics Is improved. Also, by polishing the surface, it is possible to separate the elements without performing mesa etching, and to eliminate the mesa steps,
Problems such as variations in electrode width and disconnection can be reduced.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the structure of a vehicle according to an embodiment of the present invention; FIG. 1 is a process diagram showing one embodiment of a field-effect transistor according to claim 1 and a method for forming the same according to claim 3. As shown in FIG. 1A, a surface of a high-resistance silicon
An insulating film of O ₂ , SiN, or the like is formed to a thickness of about 100 to 200 nm by a sputtering method, a CVD method, or the like, and is patterned by a resist or the like. Using the mask 2, a concave portion G having a flat bottom is formed by a method such as anisotropic etching. The size of the concave portion G is a groove having a depth of 2 to 5 μm, a width of 5 to 10 μm, and an interval of about 2 to 5 μm. This shape depends on the size of the target device.

Next, as shown in FIG. 1B, the mask 2 is removed, and MOCVD, VPE, M
Compound semiconductor thin films 3 to 6 such as gallium arsenide, aluminum gallium arsenide, and indium phosphide are heteroepitaxially grown by a BE method or the like. For example, in a MESFET, the buffer layer 3 is made of Al _x having a thickness of 500 ° or more.
Ga _1-x As (0.9 ≦ x ≦ 1) layer 4, active layer 5 having a carrier density of 1 × 10 ¹⁶ to 10 ¹⁷ cm ⁻³ , 1 × 10 ¹⁷
The contact layer 6 is grown in the order of 10 cm ^-3 to 10 ¹⁸ cm ^-3 . The thickness and carrier density of each layer are selected to be optimal according to the desired device characteristics. This growth step is continuously performed by the same apparatus. Further, the thickness of the growth layer is adjusted so as to be slightly lower than the depth of the concave portion G. This is to prevent damage to a region where a transistor is formed when the surface is polished in a later step.

Next, the surface is polished by a mechanical method and a chemical etching method as shown in FIG. The polishing process is performed until the Si surface on the terrace is exposed. At this time, since the surfaces of the compound semiconductor layers 3 to 6 formed in the concave portions G are formed to be lower than the upper portions of the terraces T, the surfaces of the compound semiconductor layers 3 to 6 are not damaged and the upper portions of the terraces T are not damaged. Almost the entire surface is flattened at the surface height of the Si substrate 1. By this step, the active layer 5 and the contact layer 6 in the region where the field effect transistor is formed are electrically separated.

Next, the Al _x Ga _{1 -x} As layer 4 is exposed 7
More oxidized. Oxidation in a steam atmosphere at 4 to 500 ° C. for about 1 to 10 hours to form Al _x Ga _{1 -x} As
It becomes an oxide layer 4 '. In this case, what is oxidized is Al _x G
The other part of the a _1-x As layer 4 is not oxidized. Since the oxidation temperature is as low as 4 to 500 ° C., the silicon substrate 1 is hardly oxidized. Also, Al _x Ga _1-x As
If the thickness of the layer 4 is less than 500 °, the cross-sectional area where oxidation proceeds will be small, and if the Al composition x is less than 0.9, the number of compounds to be oxidized will be small, and the oxidation time will be long, and the Not a target.

Next, as shown in FIG.
An insulating film 8 of O ₂ or the like is formed to a thickness of about 100 to 500 nm by a sputtering method, a CVD method, or the like.

Next, as shown in FIG. 1E, a gate pattern mask is formed of a photoresist (not shown), and is used to form the insulating film 8, the contact layer 6, and a part of the active layer 5. Are continuously etched. The etching of the contact layer 6 and the active layer 5 is preferably wet etching of a phosphoric acid system, a nitric acid system, or the like. Next, a metal film 9 serving as a gate
Is formed by vapor deposition, and lift-off is performed. Metal film is T
It has a laminated structure of a barrier metal such as i and a low-resistance metal such as Al, and has a thickness of 100 to 500 nm.

Next, as shown in FIG. 1F, a source / drain pattern mask is formed of a photoresist (not shown). After the insulating film 8 is thereby removed by patterning, the metal 10 serving as a source / drain is formed by a vapor deposition method or the like, and is formed by performing lift-off or the like. This metal is a laminated film of Au / AuGe or the like.
Finally, heat treatment is performed so that the source / drain metal 10 becomes an ohmic contact with the contact layer. The heat treatment is performed, for example, at 450 ° C. for about 8 minutes in a nitrogen atmosphere. Au plating is performed on the gate electrode 9 and the source / drain electrode 10 as necessary to form an Au electrode having a thickness of several μm, thereby improving power durability.

[0024]

As described above, according to the field effect transistor of the first aspect, the oxidized Al _x Ga between the buffer layer and the active layer in the concave portion formed on one main surface side of the substrate.
_{Since the 1-x} As (0.9 ≦ x ≦ 1) layer is provided, the active layer and the contact layer are electrically insulated from the silicon substrate. In addition, since the gate electrode and the source / drain electrodes are electrically insulated from the silicon substrate by the insulating film, the parasitic capacitance between the pad portion of these electrodes and the compound semiconductor buffer layer or the silicon substrate is reduced. And the high frequency characteristics can be greatly improved.

According to a third aspect of the present invention, a plurality of recesses are formed on a silicon substrate to contain Al _x Ga _{1 -x} As (0.9 ≦ x ≦ 1). After depositing the compound semiconductor, the compound semiconductor film between the concave portions is polished to form a transistor, so that Al _x Ga _{1 -x} As (0.9 ≦ x ≦ 1) is easily oxidized. In addition, the device can be separated without introducing mesa etching, and the step can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a field-effect transistor according to the present invention and a method for forming the same.

FIG. 2 is a cross-sectional view showing steps of a conventional method for manufacturing a field-effect transistor.

[Explanation of symbols]

1 ... silicon substrate, 2 ... mask, 3 ... buffer layer, 4 ... Al _x Ga _{1 -x} As layer, 4 '... oxidized Al _x Ga _{1 -x} As layer, 5 ... active layer, 6 ...
... contact layer, 7 ... exposed portion of Al _x Ga _1-x As layer, 8 ... insulating film, 9 ... gate electrode, 10 ...
... Source / drain electrodes

Claims (3)

[Claims] A concave portion provided on one main surface side of a silicon substrate;
In a field effect transistor in which a buffer layer and an active layer are provided in the concave portion, and a gate electrode and a source / drain electrode are provided on the active layer, Al _x Ga ₁ -oxidized between the buffer layer and the active layer _{x as (0.9 ≦ x ≦ 1} ) field effect transistor, characterized in that a layer. 2. The method according to claim 1, wherein said oxidized Al _x Ga _{1 -x} As layer has a thickness of 500 ° or more.
3. The field-effect transistor according to claim 1. 3. A method of forming a field effect transistor comprising: providing a buffer layer and an active layer on a silicon substrate; and providing a gate electrode and source / drain electrodes on the active layer.
A concave portion is formed on one main surface side of the silicon substrate, a GaAs layer serving as a buffer layer is formed on the semiconductor substrate, and Al _x Ga _{1 -x} As having a thickness of 500 ° or more (0.9 ≦ x ≦ 1)
Forming a layer and a semiconductor layer to be an active layer, and polishing the semiconductor layer protruding from the inside of the concave portion to form the Al _x Ga
_A method for forming a field effect transistor, comprising exposing a part of a _1-x As layer to wet oxidation, and thereafter forming said gate electrode and source / drain electrodes.