JP3210354B2 - Method for manufacturing heterojunction bipolar transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a heterojunction bipolar transistor having a planar structure suitable for miniaturization and high integration.

[0002]

2. Description of the Related Art Conventionally, a heterojunction bipolar transistor using a GaAs-based compound semiconductor is configured as shown in FIG. It is made as follows. On a semi-insulating GaAs substrate 21, n ⁺ Type GaAs
Sub-collector layer 22, n-type GaAs collector layer 23, p
⁺ -Type GaAs base layer 24, n-type AlGaAs emitter layer 25, n ⁺ Mold cap layer 26 by MBE or MOCVD
The layers are sequentially formed by a method. Next, the base layer 24 and the sub-collector layer 22 are exposed, and an emitter electrode 27, a base electrode 28, and a collector electrode 29 are formed on the emitter cap layer 26, the base layer 24, and the sub-collector layer 22, respectively.

As described above, in the heterojunction bipolar transistor manufactured by the conventional method, since the surface is formed by mesa etching for forming an electrode, irregularities are formed on the surface. When the fine heterojunction bipolar transistor is integrated, the unevenness causes disconnection of the wiring and the like, which is an adverse effect of the integration.

Therefore, in order to promote integration of a heterojunction bipolar transistor, a planar structure has been considered. For example, after each semiconductor layer is grown, an insulating region is formed in the base-collector separation region (collector extraction region) and the device separation region by ion implantation.
Then, an opening is made in the insulating region of the collector extraction region to expose the sub-collector layer, and a collector electrode is formed here.

[0005] Even in this method, a step of about 1 to 1.3 μm is formed in a portion where the collector electrode is formed. Therefore, in this state, when the collector electrode is connected to the wiring, the step disconnection is still a problem. To solve this,
It has been proposed that a collector electrode metal is buried in an opening formed in an insulating region by a selective chemical vapor deposition method (for example, JP-A-1-166558).

However, when using the chemical vapor deposition method, it is necessary to keep the substrate at a high temperature of about 500 ° C.
There was a problem that a good collector electrode having sufficiently low contact resistance could not be obtained.

[0007]

As described above, when a chemical vapor deposition method is used to bury a collector electrode in order to make a heterojunction bipolar transistor planar, the collector contact resistance becomes large and an excellent contact resistance is obtained. There was a problem that characteristics could not be obtained. The present invention has been made in view of the above circumstances, and has as its object to provide a method for manufacturing a flattened heterojunction bipolar transistor having excellent characteristics.

[0008]

According to the present invention, there is provided a method of manufacturing a heterojunction bipolar transistor, comprising the steps of: first, forming a first conductive type high-concentration bipolar transistor on a semiconductor substrate such that at least one of a collector junction and an emitter junction becomes a heterojunction; A sub-collector layer, a first conductivity type collector layer, a second conductivity type base layer, and a first conductivity type emitter layer are sequentially epitaxially grown. In the collector take-out region, ion implantation is performed to form an insulating region having a depth reaching the collector layer. Then, the insulating region is selectively etched to form a tapered opening having a depth reaching the subcollector layer. Next, by forming an electrode metal by physical deposition and lift-off processing, a collector electrode higher than its depth is formed in the opening with a gap left around it, and then an insulating film is deposited so that the surface becomes flat. By etching this, an insulating film is buried in the gap around the collector electrode.

The step of forming the collector electrode is preferably performed as follows. Forming a first electrode metal film for an ohmic contact with a mask left, forming a thick second electrode metal film for wiring connection via a barrier metal film on the first electrode metal film, and then removing the mask; Lift-off processing.

[0010]

According to the present invention, since the collector electrode metal is formed by the physical deposition method, the substrate does not need to be heated to a high temperature, and a collector electrode having good ohmic characteristics can be obtained.
In addition, the collector electrode metal is formed in the tapered opening by a lift-off process so as to have a thickness equal to or greater than its depth, and then the gap around the collector electrode is filled with an insulating film.
Therefore, a heterojunction bipolar transistor having a completely planarized structure can be obtained.

[0011]

Embodiments will be described below with reference to the drawings.

FIGS. 1 to 3 show Ga according to an embodiment of the present invention.
This is a manufacturing process of an As-based heterojunction bipolar transistor. In this embodiment, both the emitter junction and the collector junction are heterojunctions.

As shown in FIG. 1A, semi-insulating GaAs
On the substrate 1, 50 MBE or MOCVD is performed.
0 nm n ⁺ Type GaAs subcollector layer, n of 2,600 nm
Type AlGaAs collector layer 3, 100 nm p ⁺ GaAs
s base layer 4, 150 nm n-type AlGaAs emitter layer 5, 100 nm n ⁺ -Type GaAs emitter cap layer 6
Are sequentially deposited.

Next, B ⁺ Of the insulating region 7 having a depth reaching the substrate 1 in the element isolation region by selective ion implantation of
To form H ⁺ Is formed in the base-collector separation region to a depth reaching the collector layer 3 by selective ion implantation.

Thereafter, as shown in FIG. 1B, a silicon oxide film mask corresponding to the emitter pattern is formed by using a usual lithography technique, and unnecessary portions of the emitter cap layer 6 and the emitter layer 5 are etched. Then, the base layer 4 is exposed. A is applied to the exposed base layer 4.
The uZn base electrode 9 is connected to the emitter cap layer 6 by Au.
Each of the Ge emitter electrodes 10 is formed using a lithography technique and a spacer lift-off method. The etching step of patterning the emitter and exposing the base layer may be performed before the step of forming the insulating regions 7 and 8.

Next, as shown in FIG. 2A, a silicon oxide film 11 having a thickness of 500 to 600 nm is deposited on the surface of the substrate by a CVD method, and a photoresist pattern 12 having a window in a collector extraction region is formed thereon. Form. And CF
The oxide film 11 is etched by a reactive ion etching method using a gas such as 4 and then side etched by about 200 nm by chemical etching.

Next, as shown in FIG. 2 (b), using the photoresist pattern 12 and the oxide film 11 as a mask, the sub-collector layer 2 reaches the insulated region 8 by chemical etching using tartaric acid or the like. Opening 13 in depth
To form The opening 13 is tapered as shown.

Next, using a physical deposition method such as a vacuum evaporation method or a sputtering method, A
A first collector electrode metal film 14 such as uGe is formed, and a thin barrier metal such as Mo is formed thereon.
A second collector metal film 15 for wiring connection such as t / Au is formed thick. First and second collector electrode metal films 14,
The total thickness of 15 is not less than the depth of the opening 13 and is, for example, 100 to 200 nm higher than the substrate surface. And
Lift-off processing is performed by removing the photoresist pattern 12, and the collector electrode metal film 1 is formed in the opening 13.
Leave 4,15. Next, as shown in FIG. 3A, an insulating film 16 of polyimide or the like is formed so that the surface becomes flat.

Then, the entire surface of the insulating film 16 is etched by a reactive ion etching method using an O 2 gas to expose the surface of the collector electrode metal film 15. As shown in FIG. 3B, the polyimide insulating film 16 is left so as to fill the gap around the collector electrode metal films 14 and 15. Then, after the silicon oxide film 11 is removed by etching,
By heat treatment at 20 ° C. for 20 minutes, the polyimide insulating film 16 is formed.
Is cured, and then the collector electrode is alloyed by heat treatment at 350 ° C. for 30 seconds.

Thus, according to this embodiment, a heterojunction bipolar transistor in which the collector contact opening having a large step is completely buried and flattened can be obtained. Therefore, an integrated circuit having highly reliable wiring without disconnection of wiring can be obtained. Further, since the collector electrode metal film is formed by a physical deposition method, it is not necessary to keep the substrate at a high temperature during film deposition, and good ohmic contact characteristics can be obtained. The present invention is not limited to the above embodiment.

For example, in the embodiment, the emitter and base electrodes are formed before the formation of the collector electrode. However, the emitter electrode and the base electrode may be formed after the collector electrode is formed and its periphery is buried with an insulating film. In the base electrode part,
Since there is a step, although not as large as that of the collector electrode portion, it can be buried flat by using the same process as the collector electrode portion forming process of the embodiment, and further flattening can be achieved. In the embodiments, the emitter junction and the collector junction are both heterojunctions, but the present invention is also effective when either one is a heterojunction. In the embodiment, the polyimide insulating film is used for embedding the collector opening, but another organic insulating film or an inorganic insulating film may be used. The collector electrode metal film does not have a multilayer structure as in the embodiment, but may be a single layer. In addition, the present invention can be variously modified and implemented without departing from the spirit thereof.

[0022]

As described above, according to the present invention, it is possible to obtain a heterojunction bipolar transistor having a flattened structure which is excellent in ohmic contact characteristics of a collector electrode and suitable for high integration.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of a heterojunction bipolar transistor according to one embodiment of the present invention.

FIG. 2 is a diagram showing a manufacturing process of a heterojunction bipolar transistor according to one embodiment of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the heterojunction bipolar transistor according to one embodiment of the present invention.

FIG. 4 is a diagram showing a conventional mesa heterojunction bipolar transistor.

[Explanation of symbols]

1 ... semi-insulating GaAs substrate, 2 ... n ⁺ -Type GaAs sub-collector layer 3 ... n-type AlGaAs collector layer, 4 ... p ⁺ -Type GaAs base layer, 5 ... n-type AlGaAs emitter layer, 6 ... n ⁺ Type GaAs emitter cap layer, 7: insulating region (element isolation region), 8: insulating region (collector extraction region), 9: base electrode, 10: emitter electrode, 11: silicon oxide film, 12: photoresist -Pattern, 13 ... Opening, 14: First collector electrode metal film, 15: Second collector electrode metal film, 16: Polyimide insulating film.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/33-21/331 H01L 21/44-21/445 H01L 21 / 8232 H01L 27/06-27/06 101 H01L 27/08-27/08 101 H01L 27/082 H01L 29/68-29/737 H01L 29/40-29/51 H01L 29/872

Claims (1)

(57) [Claims] 1. A semiconductor device comprising: a semiconductor substrate on which at least one of a collector junction and an emitter junction is a hetero junction;
Forming a first-concentration high-concentration subcollector layer, a first-conductivity-type collector layer, a second-conductivity-type base layer, and a first-conductivity-type emitter layer; and forming a first insulating film on the semiconductor substrate. A step of forming a tapered opening having a depth reaching the sub-collector layer; and forming a metal electrode by a physical deposition method and performing lift-off processing to form a collector electrode metal having a depth higher than the depth in the opening and a gap around the collector electrode metal. Forming a second insulating film so that the surface is flat, and etching the second insulating film so as to bury the second insulating film in a gap around the collector electrode metal. comprising the steps of, a, in the etching step of the second insulating film, the first insulation
A method for manufacturing a heterojunction bipolar transistor, wherein an edge film covers the surface of the semiconductor substrate .