JP4316597B2 - Semiconductor device - Google Patents

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JP4316597B2
JP4316597B2 JP2006250927A JP2006250927A JP4316597B2 JP 4316597 B2 JP4316597 B2 JP 4316597B2 JP 2006250927 A JP2006250927 A JP 2006250927A JP 2006250927 A JP2006250927 A JP 2006250927A JP 4316597 B2 JP4316597 B2 JP 4316597B2
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semiconductor device
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JP2008072027A (en
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久夫 川崎
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

本発明は、例えば高周波電力増幅素子として用いられる電界効果トランジスタなどの半導体装置に関する。   The present invention relates to a semiconductor device such as a field effect transistor used as a high frequency power amplification element.

近年、大電力用のインバータ回路やスイッチング素子などの高機能化に伴い、電界効果トランジスタ（以下Field Effect Transistor：ＦＥＴと記す）において、さらなる高周波特性、信頼性の向上が要求されている。   2. Description of the Related Art In recent years, with higher functionality of high-power inverter circuits and switching elements, field effect transistors (hereinafter referred to as field effect transistors: FETs) are required to be further improved in high-frequency characteristics and reliability.

一般に、ＧａＡｓ−ＦＥＴにおいては、ソース電極とグランド電極とをバイアホールを通して接続する方法により、ソースインダクタンスの低減を図っている。例えば、特許文献１において、図１（ｂ）などに記載されているように、主面上にソース電極１１２、ゲート電極１１３、ドレイン電極１１４がそれぞれ形成された半導体基板１１１の裏面側よりソース電極１１２に到達するバイアホール１１６が形成されており、ソース電極１１２は、このバイアホール１１６内部及び半導体基板１１１裏面に形成された金メッキ層１１５により接地されている。   In general, in a GaAs-FET, the source inductance is reduced by a method of connecting a source electrode and a ground electrode through a via hole. For example, in Patent Document 1, as described in FIG. 1B and the like, the source electrode is formed from the back side of the semiconductor substrate 111 in which the source electrode 112, the gate electrode 113, and the drain electrode 114 are formed on the main surface. A via hole 116 reaching 112 is formed, and the source electrode 112 is grounded by a gold plating layer 115 formed in the via hole 116 and on the back surface of the semiconductor substrate 111.

このように、各ソース電極をバイアホールにおいて接続することにより、ソースインダクタンスの低減を図ることができる。しかしながら、バイアホールの形成により、機械的強度が低下するため、特許文献１において、垂直方向の応力に対して機械的強度を向上させるために、バイアホールの位置を交互にずらす手法が提案されている。   In this way, the source inductance can be reduced by connecting each source electrode in a via hole. However, since the mechanical strength decreases due to the formation of the via hole, Patent Document 1 proposes a method of alternately shifting the position of the via hole in order to improve the mechanical strength against the stress in the vertical direction. Yes.

しかしながら、近年、このようなＦＥＴに用いられる半導体基板は、バイアホールのアスペクト比、ＦＥＴの放熱特性を考慮して、数十μｍ程度まで薄化されており、さらに、グランド電極の金属層が厚くなると、上述の手法では、垂直方向の応力を十分に緩和することができず、ハンドリング性の低下、ＦＥＴチップの割れなどによる歩留りの低下を抑えることが困難であるという問題がある。
特開２００４−５５８６９号公報 However, in recent years, semiconductor substrates used in such FETs have been thinned to about several tens of micrometers in consideration of the aspect ratio of via holes and the heat dissipation characteristics of FETs, and the metal layer of the ground electrode is thicker. In other words, the above-described method has a problem that the stress in the vertical direction cannot be sufficiently relieved, and it is difficult to suppress a decrease in yield due to a decrease in handling properties and a crack in the FET chip.
JP 2004-55869 A

本発明は、ソースインダクタンスの低減を図るとともに、ＦＥＴチップの反りと機械的強度の低下を抑えることが可能な半導体装置を提供することを目的とするものである。   An object of the present invention is to provide a semiconductor device capable of reducing the source inductance and suppressing the warpage of the FET chip and the decrease in mechanical strength.

本発明の一態様によれば、化合物半導体からなる基板と、前記基板の表面上に形成される半導体層と、それぞれ前記半導体層上に形成される複数のゲート電極、複数のソース電極、及び複数のドレイン電極と、前記基板側から前記複数のソース電極の裏面にそれぞれ到達する複数のバイアホールと、前記複数のバイアホール内壁及び前記基板の裏面に形成され、前記複数のソース電極をそれぞれ接続するグランド電極と、前記複数のソース電極の表面側に形成され、前記複数のソース電極をそれぞれ接続する第１のエアーブリッジ配線を備えることを特徴とする半導体装置が提供される。 According to one embodiment of the present invention, a substrate made of a compound semiconductor, a semiconductor layer formed on the surface of the substrate, a plurality of gate electrodes, a plurality of source electrodes, and a plurality of layers formed on the semiconductor layer, respectively. Drain electrodes, a plurality of via holes respectively reaching the back surfaces of the plurality of source electrodes from the substrate side, inner walls of the plurality of via holes and the back surface of the substrate, and connecting the plurality of source electrodes, respectively . and the ground electrode, is formed on the surface side of the plurality of source electrodes, a semiconductor device is provided, characterized in that it comprises a first air-bridge wiring that connects the plurality of source electrodes, respectively.

本発明の一実施態様によれば、ソース電極がバイアホールにより接続された半導体装置において、ソースインダクタンスの低減を図るとともに、ＦＥＴチップの反りと機械的強度の低下を抑えることが可能となる。   According to one embodiment of the present invention, in a semiconductor device in which source electrodes are connected by via holes, it is possible to reduce source inductance and to suppress warping of FET chips and reduction in mechanical strength.

以下本発明の実施形態について、図を参照して説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（実施形態１）
図１に本実施形態の半導体装置であるＦＥＴ素子の上面図を、図２にそのＡ−Ａ’断面図を示す。図に示すように、例えば数１０μｍまで薄く研削されたＧａＡｓからなる基板１上に半導体層２が形成されており、その表面に、ゲート電極３を挟んで交互にソース電極４、ドレイン電極５が平行に配列されたマルチフィンガー構造を有している。ソース電極４、ドレイン電極５は、例えばＰｔ／ＡｕＧｅなどのメタル層によりオーミックコンタクトを形成した後、例えばＡｕ／Ｐｔ／Ｔｉなどのメタル層が積層された構造を有している。基板１には、ソース電極４に到達するバイアホール６が形成されており、その内壁及び基板１裏面にはＡｕメッキにより形成された例えば５〜３０μｍ厚のグランド電極７が形成されている。 (Embodiment 1)
FIG. 1 shows a top view of an FET element which is a semiconductor device of the present embodiment, and FIG. As shown in the figure, a semiconductor layer 2 is formed on a substrate 1 made of GaAs thinly ground to, for example, several tens of micrometers, and source electrodes 4 and drain electrodes 5 are alternately formed on the surface with a gate electrode 3 interposed therebetween. It has a multi-finger structure arranged in parallel. The source electrode 4 and the drain electrode 5 have a structure in which an ohmic contact is formed by a metal layer such as Pt / AuGe, and then a metal layer such as Au / Pt / Ti is stacked. A via hole 6 reaching the source electrode 4 is formed on the substrate 1, and a ground electrode 7 having a thickness of, for example, 5 to 30 μm formed by Au plating is formed on the inner wall and the back surface of the substrate 1.

ゲート電極３は、ゲート配線８を介して外部とボンディングされ入出力するためのゲートパッド９と接続されている。また、ソース電極３、ドレイン電極４は、ゲート配線５或いはＳｉＮ層などのパシベーション膜（図示せず）と接することなく、Ａｕメッキにより形成された例えば５〜３０μｍ厚のエアーブリッジ配線１０により、それぞれ外部とボンディングされるソースパッド１１、ドレインパッド１２と接続されている。さらに、隣接するソース電極３を接続するように、Ａｕメッキにより形成されたエアーブリッジ配線１３が形成されている。   The gate electrode 3 is bonded to the outside via a gate wiring 8 and connected to a gate pad 9 for input / output. Further, the source electrode 3 and the drain electrode 4 are respectively formed by, for example, 5 to 30 μm thick air bridge wiring 10 formed by Au plating without being in contact with a passivation film (not shown) such as a gate wiring 5 or a SiN layer. It is connected to a source pad 11 and a drain pad 12 which are bonded to the outside. Further, an air bridge wiring 13 formed by Au plating is formed so as to connect adjacent source electrodes 3.

これらエアーブリッジ配線１０、１３は、浮遊容量が発生しないように、ゲート電極２との間に十分な距離を有している。また、エアーブリッジ配線１０、１３と、グランド電極６は、同程度の厚さのＡｕメッキ層により構成されている。   These air bridge wirings 10 and 13 have a sufficient distance from the gate electrode 2 so that stray capacitance does not occur. Further, the air bridge wirings 10 and 13 and the ground electrode 6 are configured by an Au plating layer having the same thickness.

上述したように、各ソース電極４は、基板１裏面側より形成されたバイアホール６においてグランド電極７と接続され、基板１表面側において、グランド電極７と同程度の厚さを有するエアーブリッジ配線１３により、隣接するソース電極４を接続される。そして、このような構成により、ソース電極４とグランド電極７の接触面積を減少させることなく、ソースインダクタンスが低減されるとともに、半導体基板が薄化し、グランド電極の金属層が厚膜化した場合においても、ソース電極４の上下に厚いＡｕ層が形成されることにより、垂直方向の応力を十分に緩和することができるため、ＦＥＴチップの反りを防止することができるとともに、機械的強度を高めることが可能となる。従って、半導体装置の製造プロセス中、或いは基板、ＦＥＴチップのハンドリング時に、基板に垂直方向から応力が加わった際に、基板、ＦＥＴチップの割れが抑制され、歩留まりを向上させることが可能となる。   As described above, each source electrode 4 is connected to the ground electrode 7 in the via hole 6 formed from the back side of the substrate 1, and the air bridge wiring having the same thickness as the ground electrode 7 on the surface side of the substrate 1. 13, adjacent source electrodes 4 are connected. With such a configuration, when the source inductance is reduced without reducing the contact area between the source electrode 4 and the ground electrode 7, the semiconductor substrate is thinned, and the metal layer of the ground electrode is thickened. However, since a thick Au layer is formed above and below the source electrode 4, the stress in the vertical direction can be sufficiently relaxed, so that the warp of the FET chip can be prevented and the mechanical strength can be increased. Is possible. Accordingly, when a stress is applied from the vertical direction to the substrate during the manufacturing process of the semiconductor device or during the handling of the substrate and the FET chip, cracking of the substrate and the FET chip is suppressed, and the yield can be improved.

尚、エアーブリッジ配線１２は、エアーブリッジ配線１０や、他のボンディング配線などの金属配線の形成時に、併せてメッキ法などを用いて形成することができるため、その形成のために新たな工程を設ける必要はない。   The air bridge wiring 12 can be formed using a plating method or the like at the time of forming the metal wiring such as the air bridge wiring 10 or other bonding wiring. There is no need to provide it.

このような構成は、例えば、ＨＥＭＴ（High Electron Mobility Transistor）の他、ＭＥＳＦＥＴ（Metal Semiconductor Field Effect Transistor）や、ＭＯＳＦＥＴ（Metal oxide、semiconductor field effect transistor）などのＦＥＴ素子に用いられる。そして、これらＦＥＴ素子を構成要素とするモノシリックマイクロ波集積回路に適用し、例えば電力変換装置として用いられる。   Such a configuration is used, for example, for FET elements such as HEMT (High Electron Mobility Transistor), MESFET (Metal Semiconductor Field Effect Transistor), and MOSFET (Metal oxide, semiconductor field effect transistor). And it applies to the monolithic microwave integrated circuit which uses these FET elements as a component, for example, is used as a power converter.

尚、本発明は、上述した実施形態に限定されるものではない。その他要旨を逸脱しない範囲で種々変形して実施することができる。   In addition, this invention is not limited to embodiment mentioned above. Various other modifications can be made without departing from the scope of the invention.

本発明の一態様によるＦＥＴ素子の上面図。1 is a top view of an FET device according to one embodiment of the present invention. 図１のＡ−Ａ’段面図。The A-A 'step view of FIG.

符号の説明Explanation of symbols

１…基板、２…半導体層、３…ゲート電極、４…ソース電極、５…ドレイン電極、６…バイアホール、７…グランド電極、８…ゲート配線、９…ゲートパッド、１０、１３…エアーブリッジ配線、１１…ソースパッド、１２…ドレインパッド DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Semiconductor layer, 3 ... Gate electrode, 4 ... Source electrode, 5 ... Drain electrode, 6 ... Via hole, 7 ... Ground electrode, 8 ... Gate wiring, 9 ... Gate pad, 10, 13 ... Air bridge Wiring, 11 ... source pad, 12 ... drain pad

Claims (5)

化合物半導体からなる基板と、
前記基板の表面上に形成される半導体層と、
それぞれ前記半導体層上に形成される複数のゲート電極、複数のソース電極、及び複数のドレイン電極と、
前記基板側から前記複数のソース電極の裏面にそれぞれ到達する複数のバイアホールと、
前記複数のバイアホール内壁及び前記基板の裏面に形成され、前記複数のソース電極をそれぞれ接続するグランド電極と、
前記複数のソース電極の表面側に形成され、前記複数のソース電極をそれぞれ接続する第１のエアーブリッジ配線を備えることを特徴とする半導体装置。 A substrate made of a compound semiconductor;
A semiconductor layer formed on the surface of the substrate;
A plurality of gate electrodes, a plurality of source electrodes, and a plurality of drain electrodes respectively formed on the semiconductor layer;
A plurality of via holes respectively reaching the back surfaces of the plurality of source electrodes from the substrate side;
Ground electrodes formed on the inner walls of the plurality of via holes and the back surface of the substrate, and connecting the plurality of source electrodes, respectively ;
Wherein the plurality of formed on a surface side of the source electrode, the semiconductor device characterized in that it comprises a first air-bridge wiring that connects the plurality of source electrodes, respectively. 前記ソース電極及び前記ドレイン電極は、前記ゲート電極を挟んで交互に形成され、
外部回路と接続されるためのボンディングパッドと、
前記ソース電極及び前記ドレイン電極と、前記ボンディングパッド間を接続する第２のエアーブリッジ配線を備えることを特徴とする請求項１に記載の半導体装置。 The source electrode and the drain electrode are alternately formed across the gate electrode,
A bonding pad for connection to an external circuit;
The semiconductor device according to claim 1, further comprising a second air bridge wiring that connects the source electrode and the drain electrode and the bonding pads. 前記第１のエアーブリッジ配線及び前記グランド電極は、隣接する前記ソース電極を接続することを特徴とする請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the first air bridge wiring and the ground electrode connect adjacent source electrodes. 前記グランド電極、前記第１のエアーブリッジ配線及び前記第２のエアーブリッジ配線は、Ａｕメッキにより形成されることを特徴とする請求項１から３のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the ground electrode, the first air bridge wiring, and the second air bridge wiring are formed by Au plating. 前記基板はＧａＡｓ基板であることを特徴とする請求項１から４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the substrate is a GaAs substrate.
JP2006250927A 2006-09-15 2006-09-15 Semiconductor device Expired - Fee Related JP4316597B2 (en)

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