JP2004158700A - Electronic controller and method for manufacturing the same - Google Patents

Electronic controller and method for manufacturing the same Download PDF

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Publication number
JP2004158700A
JP2004158700A JP2002324042A JP2002324042A JP2004158700A JP 2004158700 A JP2004158700 A JP 2004158700A JP 2002324042 A JP2002324042 A JP 2002324042A JP 2002324042 A JP2002324042 A JP 2002324042A JP 2004158700 A JP2004158700 A JP 2004158700A
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Japan
Prior art keywords
ceramic substrate
ceramic
semiconductor element
control device
electronic control
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JP2002324042A
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Japanese (ja)
Inventor
Masahito Kirigatani
雅人 桐ヶ谷
Arihiro Kamiya
有弘 神谷
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Denso Corp
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Denso Corp
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Priority to JP2002324042A priority Critical patent/JP2004158700A/en
Priority to US10/701,443 priority patent/US20040089943A1/en
Publication of JP2004158700A publication Critical patent/JP2004158700A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

<P>PROBLEM TO BE SOLVED: To increase the connection reliability and heat dissipation property of a semiconductor element. <P>SOLUTION: A ceramic substrate 10 on which electronic components 11, 12 and 13 are mounted is housed in a case 1. A second ceramic substrate 20 is adhered to the back face of the semiconductor element 13 mounted on the first ceramic substrate 10. Electronic components 22 and 23 are mounted on the lower face of the second ceramic substrate 20. A ceramic member 30 equipped with wiring materials 31 is arranged between the first ceramic substrate 10 and the second ceramic substrate 20, and the first ceramic substrate 10 is electrically connected through wiring materials 31 of the ceramic member 30 to the second ceramic substrate 20. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は電子制御装置に関するものである。
【０００２】
【従来の技術】
複数の接続端子を有する半導体素子を回路基板上に実装した構造において、半導体素子の接続信頼性や放熱性を向上させる構成として、特許文献１に示すものがある。これは、複数の接続端子のうち、少なくとも角部に位置する接続端子の外周表面を非導電性樹脂層で被覆するものである。
【０００３】
【特許文献１】
特開２００１−７７５２７号公報
【０００４】
【発明が解決しようとする課題】
しかしながら、周囲環境が高温・多湿である場合、被覆樹脂が温度や湿度の影響で劣化する。劣化した樹脂では保護効果が無くなり、ハンダ内でのクラック伸長や基板ランドが剥離することがある。また、温度変化の大きい環境では、これらの減少は顕著になる。即ち、半導体素子の長期接続信頼性が満足されない。さらに、半導体素子で発生した熱は、ハンダバンプからのみ基板に放散される構造のため熱抵抗が高く、半導体素子温度が上昇しやすく、誤動作する場合がある。
【０００５】
本発明はこのような背景の下になされたものであり、その目的は、半導体素子の接続信頼性と熱放散性を高めることができるようにすることにある。
【０００６】
【課題を解決するための手段】
請求項１に記載の発明によれば、半導体素子の背面にセラミック基板（第２のセラミック基板）を接着するので、半導体素子の見かけの熱膨張率がセラミック基板の熱膨張率に近似させることができ、これにより、ハンダ接合部にかかる熱応力が軽減され、接続信頼性を高くすることができる。また、背面に接着したセラミック基板がヒートシンクの役割を果たし、半導体素子の急激な発熱に対する熱放散性を高くすることができる。このようにして半導体素子の接続信頼性と熱放散性を高めることができる。
【０００７】
請求項２に記載の発明によれば、第２のセラミック基板の両面のうちの少なくともいずれかの面に電子部品を実装することにより、電子制御装置の小形化を図ることができる。
【０００８】
請求項３に記載の発明によれば、第１と第２のセラミック基板を電気的に接続することにより、大規模な回路を構成することが可能になる。
請求項４に記載の発明によれば、第１と第２のセラミック基板の電気的接続を図る部材に、基板材料と同じセラミックを使用することにより、ハンダ接合部にかかる熱応力が軽減され、接続信頼性を高めることができる。
【０００９】
請求項５に記載の発明によれば、第１と第２のセラミック基板の電気的接続を図る部材に、フレキシブル基板を使用することにより、ハンダ接合部にかかる熱応力が軽減され、接続信頼性を高めることができるとともに、製造工程を簡略化することができる。
【００１０】
請求項６に記載の発明によれば、台座用フリップチップ型電子部品により半導体素子の背面が第１のセラミック基板に実装する他の電子部品よりも高くなり、第２のセラミック基板を配置しやすくなる。
【００１１】
請求項７に記載の発明によれば、台座用フリップチップ型電子部品の材料としてセラミック材料を用いることにより、台座用フリップチップ型電子部品の熱膨張率がセラミック基板の熱膨張率に近いため台座用フリップチップ型電子部品と基板との間にかかる熱応力が軽減され、接続信頼性を高めることができる。
【００１２】
請求項８に記載の発明によれば、半導体素子の背面に第２のセラミック基板を接着した後に第１のセラミック基板に半導体素子を実装する場合に比べて、はじめに、半導体素子を第１のセラミック基板に実装するため、ハンダ溶融に伴なうセルフアライメント効果が実現され、厳密な位置合わせを行う必要がなくなり、そのため、製造工程を簡略化することができる。
【００１３】
請求項９に記載の発明によれば、一括リフローするため、工程が少なくなるので、製造原価を安くすることが可能となる。
【００１４】
【発明の実施の形態】
以下、この発明を具体化した一実施の形態を図面に従って説明する。
図１には、本実施形態における車載用電子制御装置（ＥＣＵ）の縦断面図を示す。図２には、車載用電子制御装置（ＥＣＵ）の斜視図を示す。ただし、図２はケースの内部におけるＥＣＵの斜視図である。図３にはケース内におけるＥＣＵの分解斜視図を示す。本ＥＣＵは、エンジン制御用ＥＣＵである。
【００１５】
図１においてケース１はケース本体２とカバー３とからなる。ケース本体２はアルミよりなり、全体構成として上面が開口した箱型をなしている。ケース本体２の上面開口部はカバー（蓋）３にて塞がれている。
【００１６】
ケース１内においてケース本体２の底面には、セラミック基板（第１のセラミック基板）１０が配置（収納）され、接着剤にて固定されている。セラミック基板１０は回路基板として用いており、詳しくはセラミック基板１０はセラミック多層基板よりなる。図３に示すように、セラミック基板１０の上面には電子部品１１，１２，１３が搭載（表面実装）されている。電子部品１１はチップコンデンサであり、電子部品１２はフリップチップ型電子部品である。電子部品１３は半導体素子、具体的にはチップサイズパッケージ（ＣＳＰ）であり、台座用フリップチップ型電子部品としてのインターポーザ１４を介して実装されている。詳しくは、セラミック基板１０の上面においてインターポーザ（台座用フリップチップ型電子部品）１４がハンダ付けされ、このインターポーザ１４の上に半導体素子（ＣＳＰ）１３がハンダにて接合されている。また、インターポーザ１４は配線用部材としても機能し、電子部品（ＣＳＰ）１３のバンプ（ハンダボール）とセラミック基板１０のパッドとを電気的に接続している。この半導体素子（ＣＳＰ）１３はセラミック基板１０上に多数（図３では４つ）配置されている。
【００１７】
このように、第１のセラミック基板１０に対し台座用フリップチップ型電子部品としてのインターポーザ１４を介して半導体素子（ＣＳＰ）１３を実装することにより、第１のセラミック基板１０に表面実装する他の電子部品１１，１２よりも半導体素子１３の背面（上面）を高くしている。インターポーザ１４の材料としてセラミック基板１０の材料（例えば、アルミナ）と同じセラミック材料（例えば、アルミナ）を用いている。これにより、インターポーザ１４の熱膨張率がセラミック基板１０の熱膨張率に近いためインターポーザ１４とセラミック基板１０との間にかかる熱応力が軽減され、接続信頼性を高めることができる。
【００１８】
さらに、図１に示すように、第１のセラミック基板１０に実装した半導体素子（ＣＳＰ）１３の背面（上面）にはセラミック基板（第２のセラミック基板）２０が配置され、接着層２１にて固定（接着）されている。セラミック基板２０は回路基板として用いており、詳しくはセラミック基板２０はセラミック多層基板よりなる。ここで、前述したようにインターポーザ１４により半導体素子１３の背面がセラミック基板１０に実装する他の電子部品１１，１２よりも高くなっているので、第２のセラミック基板２０を配置しやすい。また、図３に示すように、セラミック基板２０の下面には電子部品２２，２３が搭載（実装）されている。電子部品２２はチップコンデンサである。電子部品２３はベアチップであり、図１の接着層２４にてセラミック基板２０に固定されるとともにＡｕワイヤ２５にてボンディングされている（電気的に接続されている）。なお、ベアチップを第１のセラミック基板１０に実装してもよい。
【００１９】
また、図１に示すように、第１のセラミック基板１０と第２のセラミック基板２０との間において電気接続部材としてのセラミック部材３０が配置されている。セラミック部材３０は四角枠状をなし、その内方に電子部品１１，１２，１３，２２，２３が位置している。セラミック部材３０は母体がセラミック材料（絶縁体）よりなり、その内部には多数の配線材（導体）３１が上下方向に延びている。このようにセラミック部材３０は配線材３１を具備している。セラミック部材３０の配線材３１は上下のセラミック基板１０，２０に対しハンダ付けされ、両基板１０，２０はセラミック部材３０を介して電気的に接続されている。このようにして、第１と第２のセラミック基板１０，２０を電気的に接続して大規模な回路を構成することが可能になる。また、第１と第２のセラミック基板１０，２０の電気的接続を図る部材３０に、基板材料と同じセラミックを使用しているので、ハンダ接合部３２（図１参照）にかかる熱応力が軽減され、接続信頼性を高めることができる。
【００２０】
さらに、図２に示すように、セラミック基板１０の上面において左端部と右端部に、多数のパッド１５が形成されている。また、ケース本体２におけるセラミック基板１０の配置領域の左側と右側には、図１に示すように、コネクタ取付用透孔４が設けられている。この各透孔４にコネクタ４０が差し込まれ、この状態で固定されている。コネクタ４０はコネクタハウジング（ソケット）４１とコネクタピン（外部接続用ピン）４２からなる。コネクタハウジング４１は有蓋筒状をなし、コネクタハウジング４１の蓋部にはコネクタピン４２が貫通した状態で支持されている。さらに、図２に示すように、セラミック基板１０のパッド１５とコネクタピン４２とはワイヤ４３によるボンディングにて電気的に接続されている。
【００２１】
コネクタ４０は相手方コネクタを介してワイヤ（図示略）の端部と連結される。このワイヤにはバッテリー、各種センサ、エンジン制御用アクチュエータが接続される。そして、ＥＣＵはセンサ信号にてエンジンの運転状態を検知し各種の演算を実行してインジェクタやイグナイタといったアクチュエータを駆動してエンジンを最適な状態で運転させる。
【００２２】
次に、電子制御装置の製造方法（組み立て方法）を説明する。
まず、第１工程として、第１のセラミック基板１０の上面に半導体素子１３を含めた各電子部品１１，１２，１３を実装する。同様に、第２のセラミック基板２０に電子部品２２，２３を実装する。さらに、第１のセラミック基板１０の上面にセラミック部材３０を配置する。そして、第２工程として、半導体素子１３の背面に第２のセラミック基板２０を接着する。ここで、半導体素子１３の背面に第２のセラミック基板２０を接着した後に第１のセラミック基板１０に半導体素子１３を実装する場合に比べて、はじめに、半導体素子１３を第１のセラミック基板１０に実装するために、ハンダ溶融に伴なうセルフアライメント効果が実現され、厳密な位置合わせを行う必要がなくなるために、製造工程を簡略化することができる。
【００２３】
また、上下のセラミック基板１０，２０間にセラミック部材３０を設置する際、電子部品１１，１２，１３，２２，２３のハンダ付けと、電気的接続用のセラミック部材３０の配線材３１の第１と第２のセラミック基板１０，２０へのハンダ付けとを一括リフローにて行う。このように一括リフローすることにより、工程が少なくなるので、製造原価を安くすることが可能となる。
【００２４】
引き続き、ケース１のケース本体２に第１のセラミック基板１０を固定するとともにコネクタ４０を取り付ける。さらに、セラミック基板１０のパッド１５とコネクタピン４２とをワイヤ４３にてボンディングする。さらには、ケース本体２に対しカバー３を取り付けて電子制御装置の製造（組み立て）が完了する。
【００２５】
このような手順にて、第２のセラミック基板２０を、第１のセラミック基板１０上に実装した高集積半導体素子（ＣＳＰ）１３に接着する。この際、図１の接着層２１には鉛フリーハンダを用いると、環境負荷低減を図る上で好ましいものとなる。また、チップコンデンサ１１，２２をセラミック基板１０，２０に実装する際に、ハンダ接合には、環境負荷低減のために鉛フリーハンダを用いるのが好ましい。同様に、ベアチップ２３を固定する接着層２４は環境負荷低減のために鉛フリーハンダを用いるとよい。
【００２６】
また、半導体素子（ＣＳＰ）１３はセラミック基板と同じ材料からなるインターポーザ１４を介して第１のセラミック基板１０に実装されているので、第１のセラミック基板１０とインターポーザ１４にアルミナを使用した場合、熱膨張率は約７×１０−６／℃で同じであるため、ハンダ接合部１４ａ（図１参照）に作用する熱応力は小さい。
【００２７】
一方、インターポーザ１４と半導体素子（ＣＳＰ）１３間のハンダ接合部１３ａ（図１参照）に作用する熱応力は大きい。なぜなら、半導体素子（シリコン）の熱膨張率が約２×１０−６／℃であり、約５×１０−６／℃の熱膨張率差を含んでいるからである。この熱応力は、半導体素子１３の角部もしくは周辺バンプで特に大きく、また、大形な半導体素子１３において大きい。
【００２８】
近年、半導体素子に高い機能が求められるに従い素子サイズは大型化の傾向にあるため、接続信頼性に関して、前述の熱応力起因の接続寿命が問題となる状況である。
【００２９】
そこで、本実施形態のように半導体素子（ＣＳＰ）１３の背面に第２のセラミック基板２０を接着することで、半導体素子（ＣＳＰ）１３の見かけの熱膨張率が大きくなりセラミック基板１０の熱膨張率に近似させることができる。そのため、図１のハンダ接合部１３ａにかかる熱応力を軽減することができる。これにより、ハンダ内クラック伸展、及び、基板側ランド剥離を防止でき、半導体素子１３の長期接続信頼性を高めることができる。
【００３０】
また、第２のセラミック基板２０がヒートシンクの役割を果たすため、半導体素子１３の急激な発熱に対する熱放散性が高まり、誤動作を防止することができる。つまり、半導体素子（ＣＳＰ）１３内の発熱が、その背面から第２のセラミック基板２０に放散するため、半導体素子１３と周辺部間の熱抵抗が減少する。これにより、周囲温度が高温な場合においても高放熱で接続信頼性に優れ、より高温の使用環境下でも誤作動させないことが可能となる。
【００３１】
図１に示すごとく第２のセラミック基板２０の下面にチップコンデンサ２２を実装したが、第２のセラミック基板２０の上面に実装することも可能である。また、図１に示すごとく第２のセラミック基板２０の下面にベアチップ２３を実装したが、第２のセラミック基板２０の上面にも実装可能である。このように、第２のセラミック基板２０の両面のうちの少なくともいずれかの面に電子部品２２，２３を実装することができ、電子制御装置の小形化を図る上で好ましいものとなる。
【００３２】
また、インターポーザ１４を介さずに半導体素子（ＣＳＰ）１３を直接第１のセラミック基板１０に実装することも可能である。ただし、小形な半導体素子に限定することが望ましい。なぜなら、前述と同様な理由で、ハンダ接合部１３ａに熱応力が生じやすく、接続信頼性が懸念されるからである。
【００３３】
上述したように上下のセラミック基板１０，２０間の電気的接続は、セラミック部材３０内の多数本の配線材（導体）３１を介したハンダ付けにて行っているが、このとき、ハンダ接続後のハンダ接合部３２（図１参照）の隙間を、低融点のガラス材料でハーメチックシールするとよい。シールすることで外部からの湿気の流入を防止できるために、接続寿命、及び、部品寿命を延長することができる。また、シール構造を採用することで、図１のハンダ接合部３２，１４ａ，１３ａ，１２ａ，１１ａ等に鉛共晶（Ｓｎ−３７Ｐｂ）ハンダを用いても、外界に流出する危険性はなくなり、環境負荷低減の効果も期待できる。
【００３４】
上下のセラミック基板１０，２０の接続方法および構造は、図示した形態に限定されるものではない。すなわち、第１と第２のセラミック基板１０，２０間の電気的接続に（コンタクト用部材３０に）フレキシブル基板を用いることも可能である。このように第１と第２のセラミック基板１０，２０の電気的接続を図る部材に、フレキシブル基板を使用すると、ハンダ接合部にかかる熱応力が軽減され、接続信頼性を高めることができるとともに、製造工程を簡略化することができる。
【００３５】
なお、半導体素子１３としてＣＳＰ（チップサイズパッケージ）を用いたが、これに限定されるものではなく、他の半導体素子、特にフェースダウンボンディング型の半導体素子であるＢＧＡ（ボールグリッドアレイ）やフリップチップ型電子部品を用いてもよい。
【図面の簡単な説明】
【図１】実施の形態における車載用電子制御装置（ＥＣＵ）の縦断面図。
【図２】車載用電子制御装置（ＥＣＵ）の斜視図。
【図３】車載用電子制御装置（ＥＣＵ）の分解斜視図。
【符号の説明】
１…ケース、２…ケース本体、３…カバー、１０…第１のセラミック基板、１１，１２…電子部品、１３…半導体素子、１４…台座用フリップチップ型電子部品、２０…第２のセラミック基板、２２，２３…電子部品、３０…セラミック部材、３１…配線材。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electronic control device.
[0002]
[Prior art]
In a structure in which a semiconductor element having a plurality of connection terminals is mounted on a circuit board, there is a configuration disclosed in Patent Document 1 as a configuration for improving connection reliability and heat dissipation of the semiconductor element. In this method, at least the outer peripheral surface of a connection terminal located at a corner portion among a plurality of connection terminals is covered with a non-conductive resin layer.
[0003]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2001-77527
[Problems to be solved by the invention]
However, when the surrounding environment is high temperature and high humidity, the coating resin deteriorates under the influence of temperature and humidity. The deteriorated resin loses the protection effect, and may cause crack elongation in the solder and peeling of the substrate land. In an environment where the temperature change is large, these reductions become remarkable. That is, the long-term connection reliability of the semiconductor element is not satisfied. Further, heat generated in the semiconductor element is dissipated to the substrate only from the solder bumps, so that the heat resistance is high, the temperature of the semiconductor element tends to rise, and a malfunction may occur.
[0005]
The present invention has been made under such a background, and an object of the present invention is to improve connection reliability and heat dissipation of a semiconductor device.
[0006]
[Means for Solving the Problems]
According to the first aspect of the present invention, since the ceramic substrate (the second ceramic substrate) is bonded to the back surface of the semiconductor element, the apparent coefficient of thermal expansion of the semiconductor element can be approximated to the coefficient of thermal expansion of the ceramic substrate. Accordingly, the thermal stress applied to the solder joint is reduced, and the connection reliability can be improved. In addition, the ceramic substrate adhered to the back surface plays the role of a heat sink, so that heat dissipation from sudden heat generation of the semiconductor element can be increased. In this way, the connection reliability and heat dissipation of the semiconductor element can be improved.
[0007]
According to the second aspect of the invention, the electronic control device can be downsized by mounting the electronic component on at least one of the two surfaces of the second ceramic substrate.
[0008]
According to the third aspect of the present invention, a large-scale circuit can be configured by electrically connecting the first and second ceramic substrates.
According to the invention as set forth in claim 4, by using the same ceramic as the substrate material for the member for electrically connecting the first and second ceramic substrates, the thermal stress applied to the solder joint is reduced. Connection reliability can be improved.
[0009]
According to the fifth aspect of the present invention, by using a flexible substrate as a member for electrically connecting the first and second ceramic substrates, thermal stress applied to the solder joint is reduced, and connection reliability is reduced. And the manufacturing process can be simplified.
[0010]
According to the sixth aspect of the present invention, the flip chip type electronic component for the pedestal makes the back surface of the semiconductor element higher than other electronic components mounted on the first ceramic substrate, so that the second ceramic substrate can be easily arranged. Become.
[0011]
According to the seventh aspect of the present invention, the ceramic material is used as the material of the flip-chip electronic component for the pedestal, so that the thermal expansion coefficient of the flip-chip electronic component for the pedestal is close to the thermal expansion coefficient of the ceramic substrate. Thermal stress applied between the flip-chip type electronic component for use and the substrate is reduced, and connection reliability can be improved.
[0012]
According to the eighth aspect of the present invention, first, the semiconductor element is first mounted on the first ceramic substrate as compared with the case where the semiconductor element is mounted on the first ceramic substrate after the second ceramic substrate is bonded to the back surface of the semiconductor element. Since the semiconductor device is mounted on the substrate, a self-alignment effect accompanying the melting of the solder is realized, and it is not necessary to perform strict alignment. Therefore, the manufacturing process can be simplified.
[0013]
According to the ninth aspect of the present invention, since the batch reflow is performed, the number of steps is reduced, so that the manufacturing cost can be reduced.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 shows a longitudinal sectional view of an on-vehicle electronic control unit (ECU) according to the present embodiment. FIG. 2 is a perspective view of an in-vehicle electronic control unit (ECU). However, FIG. 2 is a perspective view of the ECU inside the case. FIG. 3 is an exploded perspective view of the ECU in the case. This ECU is an engine control ECU.
[0015]
In FIG. 1, a case 1 includes a case body 2 and a cover 3. The case body 2 is made of aluminum, and has a box shape with an open upper surface as a whole configuration. The upper opening of the case body 2 is closed by a cover (lid) 3.
[0016]
A ceramic substrate (first ceramic substrate) 10 is disposed (stored) on the bottom surface of the case main body 2 in the case 1 and fixed with an adhesive. The ceramic substrate 10 is used as a circuit board, and more specifically, the ceramic substrate 10 is a ceramic multilayer substrate. As shown in FIG. 3, electronic components 11, 12, and 13 are mounted (surface mounted) on the upper surface of the ceramic substrate 10. The electronic component 11 is a chip capacitor, and the electronic component 12 is a flip-chip type electronic component. The electronic component 13 is a semiconductor element, specifically, a chip size package (CSP), and is mounted via an interposer 14 as a flip-chip type electronic component for a base. Specifically, an interposer (a flip-chip type electronic component for pedestal) 14 is soldered on the upper surface of the ceramic substrate 10, and a semiconductor element (CSP) 13 is joined on the interposer 14 by soldering. The interposer 14 also functions as a wiring member, and electrically connects the bumps (solder balls) of the electronic component (CSP) 13 and the pads of the ceramic substrate 10. A large number (four in FIG. 3) of the semiconductor elements (CSP) 13 are arranged on the ceramic substrate 10.
[0017]
As described above, by mounting the semiconductor element (CSP) 13 on the first ceramic substrate 10 via the interposer 14 as the flip-chip type electronic component for the pedestal, other surface mounting on the first ceramic substrate 10 is performed. The back surface (upper surface) of the semiconductor element 13 is higher than the electronic components 11 and 12. As the material of the interposer 14, the same ceramic material (eg, alumina) as the material of the ceramic substrate 10 (eg, alumina) is used. Thereby, since the thermal expansion coefficient of the interposer 14 is close to the thermal expansion coefficient of the ceramic substrate 10, the thermal stress applied between the interposer 14 and the ceramic substrate 10 is reduced, and the connection reliability can be improved.
[0018]
Further, as shown in FIG. 1, a ceramic substrate (second ceramic substrate) 20 is disposed on the back surface (upper surface) of the semiconductor element (CSP) 13 mounted on the first ceramic substrate 10, and the adhesive layer 21 Fixed (bonded). The ceramic substrate 20 is used as a circuit board. More specifically, the ceramic substrate 20 is a ceramic multilayer substrate. Here, as described above, since the back surface of the semiconductor element 13 is higher than the other electronic components 11 and 12 mounted on the ceramic substrate 10 by the interposer 14, the second ceramic substrate 20 can be easily arranged. As shown in FIG. 3, electronic components 22 and 23 are mounted (mounted) on the lower surface of the ceramic substrate 20. The electronic component 22 is a chip capacitor. The electronic component 23 is a bare chip, which is fixed to the ceramic substrate 20 by the adhesive layer 24 of FIG. 1 and is bonded (electrically connected) by an Au wire 25. Note that a bare chip may be mounted on the first ceramic substrate 10.
[0019]
Further, as shown in FIG. 1, a ceramic member 30 as an electrical connection member is disposed between the first ceramic substrate 10 and the second ceramic substrate 20. The ceramic member 30 has a rectangular frame shape, and the electronic components 11, 12, 13, 22, and 23 are located inside the ceramic member 30. The base of the ceramic member 30 is made of a ceramic material (insulator), and a large number of wiring members (conductors) 31 extend in the vertical direction inside the base. Thus, the ceramic member 30 includes the wiring member 31. The wiring member 31 of the ceramic member 30 is soldered to the upper and lower ceramic substrates 10 and 20, and both substrates 10 and 20 are electrically connected via the ceramic member 30. In this manner, a large-scale circuit can be formed by electrically connecting the first and second ceramic substrates 10 and 20. Further, since the same ceramic as the substrate material is used for the member 30 for electrically connecting the first and second ceramic substrates 10 and 20, the thermal stress applied to the solder joint 32 (see FIG. 1) is reduced. Connection reliability can be improved.
[0020]
Further, as shown in FIG. 2, a large number of pads 15 are formed at the left end and the right end on the upper surface of the ceramic substrate 10. Further, on the left and right sides of the arrangement area of the ceramic substrate 10 in the case body 2, as shown in FIG. A connector 40 is inserted into each of the through holes 4 and is fixed in this state. The connector 40 includes a connector housing (socket) 41 and a connector pin (external connection pin) 42. The connector housing 41 has a closed cylindrical shape, and a connector portion 42 is supported by a cover portion of the connector housing 41 in a state of penetrating therethrough. Further, as shown in FIG. 2, the pads 15 of the ceramic substrate 10 and the connector pins 42 are electrically connected by bonding with wires 43.
[0021]
The connector 40 is connected to an end of a wire (not shown) via a mating connector. A battery, various sensors, and an actuator for engine control are connected to this wire. The ECU detects the operating state of the engine based on the sensor signal, executes various calculations, and drives an actuator such as an injector or an igniter to operate the engine in an optimal state.
[0022]
Next, a manufacturing method (assembly method) of the electronic control device will be described.
First, as a first step, the electronic components 11, 12, and 13 including the semiconductor element 13 are mounted on the upper surface of the first ceramic substrate 10. Similarly, the electronic components 22 and 23 are mounted on the second ceramic substrate 20. Further, the ceramic member 30 is arranged on the upper surface of the first ceramic substrate 10. Then, as a second step, the second ceramic substrate 20 is bonded to the back surface of the semiconductor element 13. Here, first, the semiconductor element 13 is attached to the first ceramic substrate 10 in comparison with the case where the semiconductor element 13 is mounted on the first ceramic substrate 10 after the second ceramic substrate 20 is bonded to the back surface of the semiconductor element 13. The self-alignment effect accompanying solder melting is realized for mounting, and it is not necessary to perform strict alignment, so that the manufacturing process can be simplified.
[0023]
Further, when the ceramic member 30 is installed between the upper and lower ceramic substrates 10 and 20, the electronic components 11, 12, 13, 22 and 23 are soldered and the first wiring member 31 of the ceramic member 30 for electrical connection is used. And soldering to the second ceramic substrates 10 and 20 are performed by batch reflow. By performing the batch reflow in this manner, the number of steps is reduced, and thus the manufacturing cost can be reduced.
[0024]
Subsequently, the first ceramic substrate 10 is fixed to the case body 2 of the case 1 and the connector 40 is attached. Further, the pads 15 of the ceramic substrate 10 and the connector pins 42 are bonded by wires 43. Further, the cover 3 is attached to the case body 2 to complete the manufacture (assembly) of the electronic control device.
[0025]
According to such a procedure, the second ceramic substrate 20 is bonded to the highly integrated semiconductor element (CSP) 13 mounted on the first ceramic substrate 10. At this time, it is preferable to use lead-free solder for the adhesive layer 21 in FIG. 1 in order to reduce environmental load. Further, when mounting the chip capacitors 11 and 22 on the ceramic substrates 10 and 20, it is preferable to use lead-free solder for solder joining in order to reduce environmental load. Similarly, for the adhesive layer 24 for fixing the bare chip 23, it is preferable to use lead-free solder for reducing the environmental load.
[0026]
Further, since the semiconductor element (CSP) 13 is mounted on the first ceramic substrate 10 via the interposer 14 made of the same material as the ceramic substrate, when the first ceramic substrate 10 and the interposer 14 use alumina, Since the thermal expansion coefficient is the same at about 7 × 10 −6 / ° C., the thermal stress acting on the solder joint 14a (see FIG. 1) is small.
[0027]
On the other hand, the thermal stress acting on the solder joint 13a (see FIG. 1) between the interposer 14 and the semiconductor element (CSP) 13 is large. This is because the coefficient of thermal expansion of the semiconductor element (silicon) is about 2 × 10 −6 / ° C., which includes a difference of about 5 × 10 −6 / ° C. This thermal stress is particularly large at a corner portion or a peripheral bump of the semiconductor element 13, and is large in a large semiconductor element 13.
[0028]
In recent years, as semiconductor devices have been required to have higher functions, the device size has tended to increase in size. Therefore, the connection life due to the thermal stress described above has become a problem in connection reliability.
[0029]
Therefore, by adhering the second ceramic substrate 20 to the back surface of the semiconductor element (CSP) 13 as in the present embodiment, the apparent thermal expansion coefficient of the semiconductor element (CSP) 13 increases, and the thermal expansion of the ceramic substrate 10 increases. Rate can be approximated. Therefore, the thermal stress applied to the solder joint 13a in FIG. 1 can be reduced. Thereby, the extension of the crack in the solder and the peeling of the land on the substrate side can be prevented, and the long-term connection reliability of the semiconductor element 13 can be improved.
[0030]
In addition, since the second ceramic substrate 20 functions as a heat sink, the heat dissipation of the semiconductor element 13 against sudden heat generation is enhanced, and malfunction can be prevented. In other words, heat generated in the semiconductor element (CSP) 13 is dissipated from the back surface to the second ceramic substrate 20, so that the thermal resistance between the semiconductor element 13 and the peripheral portion is reduced. As a result, even when the ambient temperature is high, the heat dissipation is high and the connection reliability is excellent, and it is possible to prevent a malfunction even under a higher temperature use environment.
[0031]
Although the chip capacitor 22 is mounted on the lower surface of the second ceramic substrate 20 as shown in FIG. 1, it is also possible to mount the chip capacitor 22 on the upper surface of the second ceramic substrate 20. Although the bare chip 23 is mounted on the lower surface of the second ceramic substrate 20 as shown in FIG. 1, it can be mounted on the upper surface of the second ceramic substrate 20 as well. In this manner, the electronic components 22 and 23 can be mounted on at least one of the two surfaces of the second ceramic substrate 20, which is preferable in reducing the size of the electronic control device.
[0032]
Further, the semiconductor element (CSP) 13 can be directly mounted on the first ceramic substrate 10 without using the interposer 14. However, it is desirable to limit the size to a small semiconductor element. This is because, for the same reason as described above, thermal stress is easily generated in the solder joint 13a, and connection reliability is concerned.
[0033]
As described above, the electrical connection between the upper and lower ceramic substrates 10 and 20 is performed by soldering via a number of wiring members (conductors) 31 in the ceramic member 30. At this time, after the solder connection, It is preferable to hermetically seal the gap between the solder joints 32 (see FIG. 1) with a glass material having a low melting point. The sealing can prevent the inflow of moisture from the outside, so that the connection life and the life of parts can be extended. Also, by employing a seal structure, even if lead eutectic (Sn-37Pb) solder is used for the solder joints 32, 14a, 13a, 12a, 11a, etc. in FIG. The effect of reducing environmental load can also be expected.
[0034]
The connection method and structure of the upper and lower ceramic substrates 10 and 20 are not limited to the illustrated form. That is, a flexible substrate (for the contact member 30) can be used for electrical connection between the first and second ceramic substrates 10 and 20. When a flexible substrate is used as a member for electrically connecting the first and second ceramic substrates 10 and 20 in this manner, thermal stress applied to a solder joint is reduced, and connection reliability can be improved. The manufacturing process can be simplified.
[0035]
Although a CSP (chip size package) is used as the semiconductor element 13, the present invention is not limited to this, and other semiconductor elements, in particular, a BGA (ball grid array) or a flip chip, which is a face-down bonding type semiconductor element. A type electronic component may be used.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of an in-vehicle electronic control unit (ECU) according to an embodiment.
FIG. 2 is a perspective view of an in-vehicle electronic control unit (ECU).
FIG. 3 is an exploded perspective view of an in-vehicle electronic control unit (ECU).
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Case, 2 ... Case main body, 3 ... Cover, 10 ... First ceramic substrate, 11, 12 ... Electronic component, 13 ... Semiconductor element, 14 ... Flip chip type electronic component for pedestal, 20 ... Second ceramic substrate , 22, 23 ... electronic parts, 30 ... ceramic members, 31 ... wiring materials.

Claims (9)

ケース（１）内において、電子部品（１１，１２，１３）を実装したセラミック基板（１０）を収納した電子制御装置であって、
第１のセラミック基板（１０）に実装した半導体素子（１３）の背面に第２のセラミック基板（２０）を接着したことを特徴とする電子制御装置。An electronic control device containing a ceramic substrate (10) on which electronic components (11, 12, 13) are mounted in a case (1),
An electronic control device characterized in that a second ceramic substrate (20) is bonded to the back surface of a semiconductor element (13) mounted on a first ceramic substrate (10). 前記第２のセラミック基板（２０）の両面のうちの少なくともいずれかの面に電子部品（２２，２３）を実装したことを特徴とする請求項１に記載の電子制御装置。The electronic control device according to claim 1, wherein electronic components (22, 23) are mounted on at least one of both surfaces of the second ceramic substrate (20). 前記第１のセラミック基板（１０）と第２のセラミック基板（２０）とを電気的に接続したことを特徴とする請求項２に記載の電子制御装置。The electronic control device according to claim 2, wherein the first ceramic substrate (10) and the second ceramic substrate (20) are electrically connected. 配線材（３１）を具備するセラミック部材（３０）を、前記第１のセラミック基板（１０）と第２のセラミック基板（２０）との間に配置し、セラミック部材（３０）の配線材（３１）を介して第１のセラミック基板（１０）と第２のセラミック基板（２０）とを電気的に接続したことを特徴とする請求項３に記載の電子制御装置。A ceramic member (30) including a wiring member (31) is disposed between the first ceramic substrate (10) and the second ceramic substrate (20), and a wiring member (31) of the ceramic member (30) is provided. The electronic control device according to claim 3, wherein the first ceramic substrate (10) and the second ceramic substrate (20) are electrically connected to each other via (1). 前記第１と第２のセラミック基板（１０，２０）間の電気的接続にフレキシブル基板を用いたことを特徴とする請求項３に記載の電子制御装置。The electronic control device according to claim 3, wherein a flexible substrate is used for electrical connection between the first and second ceramic substrates (10, 20). 前記第１のセラミック基板（１０）に対し台座用フリップチップ型電子部品（１４）を介して前記半導体素子（１３）を実装することにより、第１のセラミック基板（１０）に実装する他の電子部品（１１，１２）よりも前記半導体素子（１３）の背面を高くするようにしたことを特徴とする請求項１〜５のいずれか１項に記載の電子制御装置。By mounting the semiconductor element (13) on the first ceramic substrate (10) via a flip-chip type electronic component (14) for a pedestal, other electronic components mounted on the first ceramic substrate (10). The electronic control device according to any one of claims 1 to 5, wherein the back surface of the semiconductor element (13) is higher than the components (11, 12). 前記台座用フリップチップ型電子部品（１４）の材料としてセラミック材料を用いたことを特徴とする請求項６に記載の電子制御装置。The electronic control device according to claim 6, wherein a ceramic material is used as a material of the flip-chip electronic component (14) for the pedestal. ケース（１）内において、電子部品（１１，１２，１３）を実装したセラミック基板（１０）を収納した電子制御装置の製造方法であって、
第１のセラミック基板（１０）に半導体素子（１３）を実装する第１工程と、
前記半導体素子（１３）の背面に第２のセラミック基板（２０）を接着する第２工程と、
を含むことを特徴とする電子制御装置の製造方法。A method for manufacturing an electronic control device in which a ceramic substrate (10) on which electronic components (11, 12, 13) are mounted is housed in a case (1),
A first step of mounting a semiconductor element (13) on a first ceramic substrate (10);
A second step of bonding a second ceramic substrate (20) to the back surface of the semiconductor element (13);
A method of manufacturing an electronic control device, comprising: 電子部品（１１，１２，１３）のハンダ付けと、電気的接続用のセラミック部材（３０）の配線材（３１）の第１と第２のセラミック基板（１０，２０）へのハンダ付けとを一括リフローにて行うようにしたことを特徴とする請求項８に記載の電子制御装置の製造方法。Soldering the electronic components (11, 12, 13) and soldering the wiring member (31) of the ceramic member (30) for electrical connection to the first and second ceramic substrates (10, 20). The method for manufacturing an electronic control device according to claim 8, wherein the process is performed by batch reflow.
JP2002324042A 2002-11-07 2002-11-07 Electronic controller and method for manufacturing the same Pending JP2004158700A (en)

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JP2008547240A (en) * 2005-06-30 2008-12-25 シーメンス アクチエンゲゼルシヤフト Sensitive electronic device data module hardware protection device against unauthorized manipulation from outside
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