JPH10256420A - Semiconductor device and package thereof - Google Patents
Semiconductor device and package thereofInfo
- Publication number
- JPH10256420A JPH10256420A JP9052879A JP5287997A JPH10256420A JP H10256420 A JPH10256420 A JP H10256420A JP 9052879 A JP9052879 A JP 9052879A JP 5287997 A JP5287997 A JP 5287997A JP H10256420 A JPH10256420 A JP H10256420A
- Authority
- JP
- Japan
- Prior art keywords
- wiring pattern
- tape
- circuit board
- chip
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置用パッケ
ージ及び半導体装置に関する。The present invention relates to a semiconductor device package and a semiconductor device.
【０００２】[0002]
【従来の技術】従来のテープ１０を利用して形成され、
多数のはんだボール１８を有するボールグリットアレイ
（ＢＧＡ）型の半導体装置は、図７のような構造をして
いる。すなわち、テープ１０の表面には配線パターン１
４が形成され、テープ１０の裏面には、テープ基材１０
ａに穿設されたスルーホール（ビア）を介して、配線パ
ターン１４に電気的に接続された多数の外部接続端子
（はんだボール１８）が設けられている。そして、テー
プ１０が柔軟性を有することから、スティフナーと呼ば
れるリング状の部材（以下、「枠体２１」という）をテ
ープ１０に取り付けて、半導体パッケージの剛性を高め
ている。その枠体２１の内側に半導体チップ５０が搭載
されて半導体装置が形成されている。なお、枠体２１
は、一般的に、ステンレススチール材或いは銅材によっ
て形成されている。2. Description of the Related Art Formed using a conventional tape 10,
A ball grid array (BGA) type semiconductor device having a large number of solder balls 18 has a structure as shown in FIG. That is, the wiring pattern 1 is formed on the surface of the tape 10.
4 are formed, and a tape substrate 10
A large number of external connection terminals (solder balls 18) are provided which are electrically connected to the wiring pattern 14 via through holes (vias) drilled in a. Since the tape 10 has flexibility, a ring-shaped member called a stiffener (hereinafter, referred to as a “frame 21”) is attached to the tape 10 to increase the rigidity of the semiconductor package. A semiconductor device is formed by mounting a semiconductor chip 50 inside the frame 21. The frame 21
Is generally formed of a stainless steel material or a copper material.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来の構造では、通常、テープ１０は、その表面に金属箔
から形成された一層の配線パターン１４を備えるのみで
ある。そして、その配線パターン１４は、集積回路にお
ける集積度の向上に伴って、微細化している。このた
め、上記従来の構造では、グランド、パワー等のプレー
ンを形成することが難しいという課題があった。また、
デカップリングコンデンサ等の受動部品を取り付ける際
には、枠体２１に窓をあけて取り付けなければならない
という課題もあった。また、一層の平面内で配線パター
ン１４の形状を設計することになり、配線の自由度が制
限されると共に、配線の密集による電気的特性の低下と
いう課題があった。なお、テープ１０を多層に形成して
上記課題を解決することも考えれるが、テープ１０を多
層にすると半導体装置が厚くなってしまう。また、テー
プ１０の剛性が大きくなって好適に巻き取ることができ
なくなるなど、テープ状の利点が失われてしまう。However, in the above-described conventional structure, the tape 10 usually has only one layer of the wiring pattern 14 formed of a metal foil on the surface thereof. Then, the wiring pattern 14 is miniaturized as the degree of integration in the integrated circuit is improved. For this reason, in the above-mentioned conventional structure, there was a problem that it was difficult to form a plane for ground, power, and the like. Also,
When mounting a passive component such as a decoupling capacitor, there is also a problem that a window must be opened in the frame body 21 for mounting. Further, the shape of the wiring pattern 14 is designed in a single plane, so that the degree of freedom of the wiring is limited, and there is a problem that the electrical characteristics are lowered due to the denseness of the wiring. It is conceivable to solve the above-mentioned problem by forming the tape 10 in a multilayer structure, but when the tape 10 is formed in a multilayer structure, the semiconductor device becomes thicker. In addition, the tape-shaped advantages are lost, for example, the rigidity of the tape 10 is increased and the tape 10 cannot be suitably wound.
【０００４】そこで、本発明の目的は、テープを利用し
て形成された半導体パッケージ及び半導体装置におい
て、グランド、パワー等のプレーン、或いはその他の回
路部品を好適に組み込むことができる半導体パッケージ
及び半導体装置を提供することにある。An object of the present invention is to provide a semiconductor package and a semiconductor device formed by using a tape, in which a plane such as ground, power, or other circuit components can be suitably incorporated. Is to provide.
【０００５】[0005]
【課題を解決するための手段】本発明は、上記目的を達
成するために次の構成を備える。すなわち、本発明は、
半導体チップが搭載されるチップ搭載部を備え、表面に
前記半導体チップと電気的に接続される配線パターンが
設けられた可撓性を有するテープと、該テープの前記チ
ップ搭載部を取り囲むように枠状に形成され、前記配線
パターンと電気的に接続される回路配線パターンが設け
られ、前記テープに固定されてその剛性を高める枠状回
路基板とを具備する。The present invention has the following arrangement to achieve the above object. That is, the present invention
A flexible tape having a chip mounting portion on which a semiconductor chip is mounted, and a wiring pattern provided on a surface thereof with a wiring pattern electrically connected to the semiconductor chip; and a frame surrounding the chip mounting portion of the tape. A circuit wiring pattern which is formed in a shape and is electrically connected to the wiring pattern, and which is fixed to the tape to increase the rigidity thereof.
【０００６】また、前記枠状回路基板が、多層回路基板
によって形成されていることで配線の自由度を向上でき
る。Further, since the frame-shaped circuit board is formed of a multilayer circuit board, the degree of freedom of wiring can be improved.
【０００７】また、前記回路配線パターンが、プレーン
状に形成されたグランド用配線及びパワー用配線を含む
ことで半導体装置の電気的特性を向上できる。In addition, since the circuit wiring pattern includes a ground wiring and a power wiring formed in a plane, the electrical characteristics of the semiconductor device can be improved.
【０００８】また、前記テープの基材が、ポリイミドで
あること、及び／または前記枠状回路基板が、樹脂製回
路基板であることで、汎用技術を好適に利用でき、製造
コストの低減を図ることができる。In addition, since the base material of the tape is a polyimide and / or the frame-shaped circuit board is a resin circuit board, general-purpose technology can be suitably used, and the manufacturing cost can be reduced. be able to.
【０００９】また、本発明は、半導体チップが搭載され
るチップ搭載部を備え、表面に前記半導体チップと電気
的に接続される配線パターンが設けられた可撓性を有す
るテープと、該テープの前記チップ搭載部を取り囲むよ
うに枠状に形成され、前記配線パターンと電気的に接続
される回路配線パターンが設けられ、前記テープに固定
されてその剛性を高める枠状回路基板と、前記チップ搭
載部に搭載された半導体チップとを具備することを特徴
とする半導体装置にもある。Further, the present invention provides a flexible tape having a chip mounting portion on which a semiconductor chip is mounted and having a wiring pattern provided on a surface thereof to be electrically connected to the semiconductor chip; A frame-shaped circuit board formed in a frame shape so as to surround the chip mounting portion, provided with a circuit wiring pattern electrically connected to the wiring pattern, and fixed to the tape to increase its rigidity; There is also a semiconductor device characterized by comprising a semiconductor chip mounted on a unit.
【００１０】また、前記半導体チップがフリップチップ
接続によって前記チップ搭載部に搭載され、該半導体チ
ップの背面が前記枠状回路基板に固定された放熱板によ
り覆われていることで、半導体装置の放熱性を向上でき
る。Further, the semiconductor chip is mounted on the chip mounting portion by flip-chip connection, and the back surface of the semiconductor chip is covered with a heat radiating plate fixed to the frame-shaped circuit board, so that the heat dissipation of the semiconductor device is improved. Performance can be improved.
【００１１】また、前記放熱板が固定されない枠状回路
基板の部分に、チップコンデンサ等の回路部品が搭載さ
れていることで、半導体装置の機能を向上できる。In addition, the function of the semiconductor device can be improved by mounting a circuit component such as a chip capacitor on a portion of the frame-shaped circuit board on which the heat sink is not fixed.
【００１２】[0012]
【発明の実施の形態】以下、本発明にかかる好適な実施
の形態を添付図面と共に説明する。図１は本発明による
半導体装置の一実施例を示す断面図であり、４層回路基
板を、回路基板とスティフナーの効果を兼ねる備える枠
状回路基板として使用した構成を示している。１０はテ
ープであり、半導体チップ５０が搭載されるチップ搭載
部１２を備える。このテープ１０は、可撓性があって、
表面に半導体チップ５０と電気的に接続する配線パター
ン１４が設けられている。２０は枠状回路基板であり、
テープ１０のチップ搭載部１２を除く部分に搭載される
よう矩形の枠状に形成されている。この枠状回路基板２
０には、配線パターン１４と電気的に接続される回路配
線パターン２２が設けられている。従って、この枠状回
路基板２０は、テープ１０に固定されて剛性を高めるよ
うに作用し、結果的に半導体パッケージ及び半導体装置
としての剛性を高めることができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor device according to the present invention, and shows a configuration in which a four-layer circuit board is used as a frame-shaped circuit board having both a circuit board and a stiffener effect. Reference numeral 10 denotes a tape having a chip mounting portion 12 on which the semiconductor chip 50 is mounted. This tape 10 is flexible,
The wiring pattern 14 electrically connected to the semiconductor chip 50 is provided on the surface. 20 is a frame-shaped circuit board,
The tape 10 is formed in a rectangular frame shape so as to be mounted on a portion other than the chip mounting portion 12. This frame-shaped circuit board 2
0 is provided with a circuit wiring pattern 22 that is electrically connected to the wiring pattern 14. Therefore, the frame-shaped circuit board 20 is fixed to the tape 10 and acts to increase the rigidity. As a result, the rigidity of the semiconductor package and the semiconductor device can be increased.
【００１３】枠状回路基板２０に回路配線パターン２２
を有するため、配線の自由度を高めることができる。ま
た、回路配線パターン２２が、プレーン状に形成された
グランド用配線２４及びパワー用配線２６にすることで
半導体装置の電気的特性を向上できる。また、枠状回路
基板２０上を利用し、デカップリングコンデンサ等の受
動部品を好適に搭載することができる。図１〜３に示す
ようにチップコンデンサ４０を好適に配設できる。詳細
は後述する。A circuit wiring pattern 22 is provided on a frame-shaped circuit board 20.
, The degree of freedom of wiring can be increased. In addition, the electrical characteristics of the semiconductor device can be improved by forming the circuit wiring pattern 22 as the ground wiring 24 and the power wiring 26 formed in a plane shape. Further, the passive components such as the decoupling capacitors can be suitably mounted on the frame-shaped circuit board 20. As shown in FIGS. 1 to 3, the chip capacitor 40 can be suitably arranged. Details will be described later.
【００１４】[0014]
【実施例】次に図１〜６に基づいて、本発明による半導
体装置の実施例について詳細に説明する。テープ１０上
のチップ搭載部１２は、テープ１０の中央部に設けられ
ている。このテープの基材１０ａの材質は、ポリイミド
やエポキシ等の樹脂等であればよく、可撓性があるシー
ト状の材料を用いる。すなわち、テープ１０が、可撓性
を生じる程度に柔軟性が有り、薄い材料で形成されてい
ることで、テープ１０のたわみによって半導体チップ５
０等との熱膨張係数の差による応力を好適に吸収でき
る。これにより、半導体装置が破損することを防止で
き、信頼性を向上できる。また、テープ１０の表面には
配線パターン１４が形成され、テープ１０の裏面には、
テープ基材１０ａに穿設されたスルーホール１６（ビ
ア）を介して、配線パターン１４に電気的に接続された
多数の外部接続端子（はんだボール１８）が設けられて
いる。Next, an embodiment of a semiconductor device according to the present invention will be described in detail with reference to FIGS. The chip mounting section 12 on the tape 10 is provided at the center of the tape 10. The material of the base material 10a of the tape may be a resin such as polyimide or epoxy, and a flexible sheet material is used. That is, since the tape 10 is flexible enough to generate flexibility and is formed of a thin material, the semiconductor chip 5
Stress due to a difference in thermal expansion coefficient from 0 or the like can be suitably absorbed. Thereby, the semiconductor device can be prevented from being damaged, and the reliability can be improved. Further, a wiring pattern 14 is formed on the front surface of the tape 10, and on the back surface of the tape 10,
A large number of external connection terminals (solder balls 18) electrically connected to the wiring pattern 14 are provided through through holes 16 (vias) formed in the tape base 10a.
【００１５】半導体チップ５０は、テープ１０のチップ
搭載部１２で枠状回路基板の枠内２０ａに、フリップチ
ップ接続によってテープ１０の配線パターン１４へ接続
されている。なお、半導体チップ５０のテープ１０（配
線パターン１４）への接続技術としては、フリップチッ
プ接続以外でも、ワイヤーボンディング接続、ＴＡＢ接
続等も利用できる。The semiconductor chip 50 is connected to the wiring pattern 14 of the tape 10 by flip-chip connection to the inside 20a of the frame-shaped circuit board at the chip mounting portion 12 of the tape 10. As a technique for connecting the semiconductor chip 50 to the tape 10 (wiring pattern 14), wire bonding connection, TAB connection, or the like can be used other than flip chip connection.
【００１６】図４はワイヤーボンディング接続の実施例
を示す断面図である。半導体チップ５０の背面がテープ
１０に接着され、半導体チップ５０と配線パターン１４
とがワイヤ５２で接続されている。５４はリッドであ
り、半導体チップ５０を保護するよう、枠状回路基板２
０に接着・支持されて、半導体チップ５０の上方を覆っ
ている。FIG. 4 is a sectional view showing an embodiment of wire bonding connection. The back surface of the semiconductor chip 50 is adhered to the tape 10, and the semiconductor chip 50 and the wiring pattern 14 are bonded.
Are connected by a wire 52. Reference numeral 54 denotes a lid, which protects the semiconductor chip 50 so as to protect the semiconductor chip 50.
0, and covers the upper part of the semiconductor chip 50.
【００１７】また、図５はＴＡＢ接続の実施例を示す断
面図である。５６はＴＡＢのリードであり、半導体チッ
プ５０に接続されている。ＴＡＢ接続によれば、一括に
接続でき、半導体チップ５０と配線パターン１４との接
続を効率良く行うことができる。また、図１の実施例と
同様に、半導体チップ５０の背面が枠状回路基板２０に
固定された放熱板により覆われている。FIG. 5 is a sectional view showing an embodiment of TAB connection. Reference numeral 56 denotes a TAB lead, which is connected to the semiconductor chip 50. According to the TAB connection, the connections can be made collectively, and the connection between the semiconductor chip 50 and the wiring pattern 14 can be performed efficiently. 1, the back surface of the semiconductor chip 50 is covered with a heat sink fixed to the frame-shaped circuit board 20.
【００１８】さらに、図６はフリップチップ接続の一種
として、半導体チップ５０と配線パターン１４とが異方
性導電性接着剤（以下、「ＡＣＦ」と記す）５８で接続
されている。半導体チップ５０及び／又は配線パターン
１４（本実施例では半導体チップ５０）にバンプ６０を
形成しておき、半導体チップ５０と配線パターン１４と
間に挟さまれたＡＣＦ５８を、挟圧することで容易に接
続できる。FIG. 6 shows a flip chip connection in which the semiconductor chip 50 and the wiring pattern 14 are connected by an anisotropic conductive adhesive (hereinafter, referred to as “ACF”) 58. The bumps 60 are formed on the semiconductor chip 50 and / or the wiring pattern 14 (the semiconductor chip 50 in this embodiment), and the ACF 58 sandwiched between the semiconductor chip 50 and the wiring pattern 14 can be easily pressed. Can connect.
【００１９】枠状回路基板２０は、図１の実施例では４
層の回路基板によって形成されており、これにより、配
線の自由度を向上できる。なお、４層に限定されること
なく、少なくと１層あれば、配線の自由度を向上でき
る。また、回路配線パターン２２の少なくとも一部を、
プレーン状に広い面積を備えるように形成されたグラン
ド用配線２４及びパワー用配線２６として利用できる。
これにより、パワーの供給を容易に並列にとることが可
能であり、また、半導体装置の電気的特性を向上でき
る。なお、枠状回路基板２０の中には、以上のような配
線パターンの他に必要な電気回路を形成してもよい。枠
状回路基板２０は、通常の樹脂製回路基板と同様の積層
構造の基板を所定の枠状に形成して用いればよい。すな
わち、枠状回路基板２０の製法は、通常の樹脂製回路基
板（プリント基板）の製法がそのまま使用できる。従っ
て、従来の基板( conventional board )、ビルトアップ
( built up )基板、いわゆるＢ2 it(Buried Bump Inter
connection Technology )基板、及びＲＣＣ( Resin Coa
tedCopper )基板等が使用可能である。汎用技術を好適
に利用でき、製造コストの低減を図ることができる。In the embodiment shown in FIG.
It is formed of a layered circuit board, thereby improving the degree of freedom of wiring. The number of layers is not limited to four, and if there is at least one layer, the degree of freedom of wiring can be improved. Further, at least a part of the circuit wiring pattern 22 is
It can be used as the ground wiring 24 and the power wiring 26 formed to have a large area in a plane shape.
Accordingly, power can be easily supplied in parallel, and the electrical characteristics of the semiconductor device can be improved. In the frame-like circuit board 20, necessary electric circuits may be formed in addition to the above-described wiring patterns. The frame-shaped circuit board 20 may be formed by forming a board having the same laminated structure as a normal resin circuit board into a predetermined frame shape. That is, as the method of manufacturing the frame-shaped circuit board 20, a normal method of manufacturing a resin circuit board (printed board) can be used as it is. Therefore, conventional board (built-up)
(built up) substrate, so-called B 2 it (Buried Bump Inter
connection Technology) substrate and RCC (Resin Coa
tedCopper) substrates and the like can be used. General-purpose technology can be suitably used, and manufacturing costs can be reduced.
【００２０】テープ１０と枠状回路基板２０との接続
（固定）方法は、例えば、はんだ付け２６によって配線
パターン１４と回路配線パターン２２との電気的な接続
を行い、必要の応じて隙間を接着剤によって埋めればよ
い。他の接続方法としては、導電性ペースト、例えば、
銀エポキシペーストを利用してもよい。電気的な接続の
必要のない隙間は、上記のはんだ付けと同様に接着剤を
使用する。A method of connecting (fixing) the tape 10 and the frame-shaped circuit board 20 is, for example, to make an electrical connection between the wiring pattern 14 and the circuit wiring pattern 22 by soldering 26 and bond a gap as necessary. What is necessary is just to fill with an agent. Other connection methods include conductive paste, for example,
A silver epoxy paste may be used. For the gaps that do not require electrical connection, an adhesive is used as in the case of the soldering described above.
【００２１】さらに他の接続方法としては、図５に示す
ように、ＡＣＦ５８を使用することも可能である。この
ＡＣＦを利用する場合は、通常は枠状回路基板２０の回
路配線パターン２２に凸状接続端子を設け、テープ１０
の配線パターン１４にも凸状接続端子設けて、双方の位
置を対応する凸状接続端子同士が対向するように合せ
て、双方の凸状接続端子によってＡＣＦを挟んで圧する
ことにより、容易に接続できる。なお、このとき、ＡＣ
Ｆ自身が接着剤としても働くので、特に他の接着剤は不
要である。なお、枠状回路基板２０の裏面の端子２２ａ
には必要により、はんだめっき、Ａｕめっき等を施して
おく。特に、はんだ接続の場合には、はんだのプリコー
トを施しておくことも可能である。As another connection method, as shown in FIG. 5, an ACF 58 can be used. When this ACF is used, usually, a convex connection terminal is provided on the circuit wiring pattern 22 of the frame-shaped circuit board 20, and the tape 10
The wiring pattern 14 is also provided with a convex connection terminal, the two positions are adjusted so that the corresponding convex connection terminals face each other, and the ACF is sandwiched between the two convex connection terminals so that the connection is easily performed. it can. At this time, AC
Since F itself functions as an adhesive, other adhesives are not particularly necessary. The terminal 22a on the back surface of the frame-shaped circuit board 20
Is subjected to solder plating, Au plating or the like as necessary. In particular, in the case of solder connection, it is also possible to apply a pre-coat of solder.
【００２２】３０は放熱板であり、半導体チップ１０の
背面を覆うように、枠状回路基板２０によって支持され
て搭載されている。すなわち、テープ１０にフリップチ
ップ接続された半導体チップ１０の放熱面と、枠状回路
基板２０の上面の少なくとも一部に接着剤３２（図１参
照）を介して積層・接着されている。この放熱板３０と
しては、図示した形状に限られず、フィンを設けた放熱
性の高いものを用いることができるのは勿論である。Reference numeral 30 denotes a heat sink, which is supported and mounted by the frame-shaped circuit board 20 so as to cover the back surface of the semiconductor chip 10. That is, the heat dissipation surface of the semiconductor chip 10 flip-chip connected to the tape 10 and at least a part of the upper surface of the frame-shaped circuit board 20 are laminated and adhered via the adhesive 32 (see FIG. 1). The shape of the heat radiating plate 30 is not limited to the illustrated shape, and a fin provided with a high heat radiating property can be used.
【００２３】また、４０はチップコンデンサであり、枠
状回路基板２０上で、放熱板３０が被覆されない部分
に、接続・搭載されている。枠状回路基板２０は、回路
配線パターンを露出させることができ、チップコンデン
サ４０に限らず、他の回路部品、例えば抵抗を搭載でき
るのは勿論である。図２はチップコンデンサ４０の配置
例を示す斜視図であり、半導体パッケージの全面に放熱
板３０（ヒートスプレッダー）を貼らず、中央部付近の
みとし、外周部にチップコンデンサの搭載位置を確保し
ている。また、それらの回路部品を搭載するためには、
放熱板３０に図３のように窓３４をくり抜いて、その中
にチップコンデンサ４０等の回路部品を搭載してもよ
い。Reference numeral 40 denotes a chip capacitor, which is connected and mounted on a portion of the frame-shaped circuit board 20 which is not covered with the heat sink 30. The frame-shaped circuit board 20 can expose a circuit wiring pattern and can mount not only the chip capacitor 40 but also other circuit components such as a resistor. FIG. 2 is a perspective view showing an example of the arrangement of the chip capacitors 40. The heat sink 30 (heat spreader) is not attached to the entire surface of the semiconductor package, but only in the vicinity of the center, and the mounting position of the chip capacitors is secured in the outer periphery. I have. Also, in order to mount those circuit components,
As shown in FIG. 3, a window 34 may be hollowed out in the heat sink 30, and a circuit component such as a chip capacitor 40 may be mounted therein.
【００２４】従って、本発明によれば、スティフナーと
してに作用する枠状回路基板２０に多層回路基板を用い
ることにより、パワー、グランド等のプレーンの形成、
チップコンデンサ等の個別部品搭載のパッドの形成が容
易にできる。本発明にかかる半導体装置が実装されるマ
ザーボード（基板）の材料に対して、枠状回路基板２０
の材料を、一致させることあるいは熱膨張係数の近い材
料を用いることは、相互に基板であるため、容易に可能
である。従って、はんだボール１８へ作用する応力を低
く抑えることが容易となり、はんだの疲労破壊を防ぐこ
とができる。実装にかかる信頼性を向上できる。Therefore, according to the present invention, by using a multilayer circuit board for the frame-shaped circuit board 20 acting as a stiffener, it is possible to form a plane such as power and ground.
Pads for mounting individual components such as chip capacitors can be easily formed. The material of the motherboard (substrate) on which the semiconductor device according to the present invention is mounted is reduced by the frame-shaped circuit board 20.
It is easy to match the materials described above or to use materials having similar thermal expansion coefficients because they are mutually substrates. Therefore, it is easy to keep the stress acting on the solder ball 18 low, and it is possible to prevent the fatigue damage of the solder. Reliability of mounting can be improved.
【００２５】また、本発明にかかる半導体装置用パッケ
ージの製造プロセスによれば、テープ１０と枠状回路基
板２０とを、それぞれの部品として別々に形成し、良品
のみを使って組み上げることが可能である。従って、テ
ープ１０と枠状回路基板２０とを一体で製造する場合に
比べ、製造工程でのリスクを低減できる。また、本発明
によれば、テープ１０と枠状回路基板２０との一回の積
層によってキャビティ構造を形成でき、キャビティ構造
を作る難しさをなくすことができる。Further, according to the semiconductor device package manufacturing process of the present invention, the tape 10 and the frame-shaped circuit board 20 can be separately formed as respective components, and assembled using only non-defective products. is there. Therefore, the risk in the manufacturing process can be reduced as compared with the case where the tape 10 and the frame-shaped circuit board 20 are manufactured integrally. Further, according to the present invention, the cavity structure can be formed by one-time lamination of the tape 10 and the frame-shaped circuit board 20, and the difficulty in forming the cavity structure can be eliminated.
【００２６】以上の実施例では枠状回路基板として、樹
脂製回路基板を利用する場合を説明したが、本発明はこ
れに限らず、金属の板状芯材を備えるいわゆるメタルコ
ア基板を用いてもよい。これによれば、薄くても剛性を
確保できると共に、金属の板状芯材（メタルコア）の部
分をグランド、或いはパワー供給の配線としても利用で
きる。また、以上の実施例では、半導体チップを保護す
るために、放熱板又はリッドを用いたが、本発明ではこ
れに限らず、樹脂のポッティングによって半導体チップ
の封止を行ってもよい。以上、本発明につき好適な実施
例を挙げて種々説明してきたが、本発明はこの実施例に
限定されるものではなく、発明の精神を逸脱しない範囲
内で多くの改変を施し得るのは勿論のことである。In the above embodiment, the case where a resin circuit board is used as the frame-shaped circuit board has been described. However, the present invention is not limited to this, and a so-called metal core board having a metal plate-shaped core material may be used. Good. According to this, rigidity can be ensured even if it is thin, and the portion of the metal plate-shaped core (metal core) can be used as ground or power supply wiring. Further, in the above embodiments, the heat sink or the lid is used to protect the semiconductor chip. However, the present invention is not limited to this, and the semiconductor chip may be sealed by potting with a resin. As described above, the present invention has been described variously with reference to preferred embodiments. However, the present invention is not limited to the embodiments, and it is needless to say that many modifications can be made without departing from the spirit of the invention. That is.
【００２７】[0027]
【発明の効果】本発明によれば、テープの配線パターン
と、枠状回路基板の回路配線パターンとが電気的に接続
されて、テープ上に枠状回路基板が固定されることで、
可撓性のあるテープを利用した半導体パッケージ及び半
導体装置が形成される。枠状回路基板には回路配線パタ
ーンが設けられているため、剛性を向上できると共に、
グランド、パワー等のプレーン、或いはその他の回路部
品を好適に組み込むことができるという著効を奏する。According to the present invention, the wiring pattern of the tape and the circuit wiring pattern of the frame-shaped circuit board are electrically connected, and the frame-shaped circuit board is fixed on the tape.
A semiconductor package and a semiconductor device using a flexible tape are formed. Since the circuit wiring pattern is provided on the frame-shaped circuit board, the rigidity can be improved and
This has a significant effect that a plane such as ground, power, or other circuit components can be suitably incorporated.
【図１】本発明の一実施例を示す半導体装置の断面図で
ある。FIG. 1 is a sectional view of a semiconductor device showing one embodiment of the present invention.
【図２】本発明にかかるチップコンデンサの搭載例を示
す斜視図である。FIG. 2 is a perspective view showing an example of mounting a chip capacitor according to the present invention.
【図３】本発明にかかるチップコンデンサの他の搭載例
を示す平面図である。FIG. 3 is a plan view showing another mounting example of the chip capacitor according to the present invention.
【図４】半導体チップをワイヤで接続した場合を説明す
る断面図である。FIG. 4 is a cross-sectional view illustrating a case where semiconductor chips are connected by wires.
【図５】半導体チップをＴＡＢ接続した場合を説明する
断面図である。FIG. 5 is a cross-sectional view illustrating a case where semiconductor chips are connected by TAB.
【図６】半導体チップを異方性導電性接着剤で接続した
場合を説明する断面図である。FIG. 6 is a cross-sectional view illustrating a case where semiconductor chips are connected with an anisotropic conductive adhesive.
【図７】従来の技術を説明する断面図である。FIG. 7 is a cross-sectional view illustrating a conventional technique.
１０ テープ １２ チップ搭載部 １４ 配線パターン ２０ 枠状回路基板 ２２ 回路配線パターン ２４ グランド用配線 ２６ パワー用配線 ３０ 放熱板 ４０ チップコンデンサ ５０ 半導体チップ DESCRIPTION OF SYMBOLS 10 Tape 12 Chip mounting part 14 Wiring pattern 20 Frame-shaped circuit board 22 Circuit wiring pattern 24 Ground wiring 26 Power wiring 30 Heat sink 40 Chip capacitor 50 Semiconductor chip
フロントページの続き (72)発明者 モハン キルロスカー アメリカ合衆国、カリフォルニア州95054、 サンタクララ、スイート101、スコット ブールバード3211 シンコー エレクトリ ック アメリカ内 (72)発明者 クリスタル シラー アメリカ合衆国、カリフォルニア州95054、 サンタクララ、スイート101、スコット ブールバード3211 シンコー エレクトリ ック アメリカ内 (72)発明者 リック マクドナルド アメリカ合衆国、カリフォルニア州95054、 サンタクララ、スイート101、スコット ブールバード3211 シンコー エレクトリ ック アメリカ内Continued on the front page (72) Inventor Mohan Kirlosker, 95054, California, United States, Santa Clara, Suite 101, Scott Boulevard 3211 Shinko Electric America (72) Inventor, Crystal Schiller United States, 95054, California, Santa Clara, Suite 101, Scott Boulevard 3211 Shinko Electric America (72) Inventor Rick MacDonald USA, 95054, California, Santa Clara, Suite 101, Scott Boulevard 3211 Shinko Electric America
Claims (10)
を備え、表面に前記半導体チップと電気的に接続される
配線パターンが設けられた可撓性を有するテープと、 該テープの前記チップ搭載部を取り囲むように枠状に形
成され、前記配線パターンと電気的に接続される回路配
線パターンが設けられ、前記テープに固定されてその剛
性を高める枠状回路基板とを具備することを特徴とする
半導体装置用パッケージ。1. A flexible tape having a chip mounting portion on which a semiconductor chip is mounted, and a wiring pattern provided on a surface thereof with a wiring pattern electrically connected to the semiconductor chip; and the chip mounting portion of the tape. A circuit wiring pattern formed in a frame shape surrounding the wiring pattern and electrically connected to the wiring pattern, and fixed to the tape to increase the rigidity thereof. Package for semiconductor device.
って形成されていることを特徴とする請求項１記載の半
導体装置用パッケージ。2. The semiconductor device package according to claim 1, wherein said frame-shaped circuit board is formed of a multilayer circuit board.
形成されたグランド用配線及びパワー用配線を含むこと
を特徴とする請求項１または２記載の半導体装置用パッ
ケージ。3. The semiconductor device package according to claim 1, wherein the circuit wiring pattern includes a ground wiring and a power wiring formed in a plane shape.
ことを特徴とする請求項１、２または３記載の半導体装
置用パッケージ。4. The semiconductor device package according to claim 1, wherein the base material of the tape is polyimide.
あることを特徴とする請求項１、２、３または４記載の
半導体装置用パッケージ。5. The semiconductor device package according to claim 1, wherein the frame-shaped circuit board is a resin circuit board.
を備え、表面に前記半導体チップと電気的に接続される
配線パターンが設けられた可撓性を有するテープと、 該テープの前記チップ搭載部を取り囲むように枠状に形
成され、前記配線パターンと電気的に接続される回路配
線パターンが設けられ、前記テープに固定されてその剛
性を高める枠状回路基板と、 前記チップ搭載部に搭載された半導体チップとを具備す
ることを特徴とする半導体装置。6. A flexible tape having a chip mounting portion on which a semiconductor chip is mounted, and a wiring pattern provided on a surface thereof with a wiring pattern electrically connected to the semiconductor chip; and the chip mounting portion of the tape. A circuit wiring pattern that is formed in a frame shape so as to surround the wiring pattern and is electrically connected to the wiring pattern, is fixed to the tape and increases the rigidity thereof, and is mounted on the chip mounting portion. A semiconductor device comprising: a semiconductor chip.
って形成されていることを特徴とする請求項６記載の半
導体装置。7. The semiconductor device according to claim 6, wherein said frame-shaped circuit board is formed by a multilayer circuit board.
形成されたグランド用配線及びパワー用配線を含むこと
を特徴とする請求項６または７記載の半導体装置。8. The semiconductor device according to claim 6, wherein the circuit wiring pattern includes a ground wiring and a power wiring formed in a plane shape.
によって前記チップ搭載部に搭載され、該半導体チップ
の背面が前記枠状回路基板に固定された放熱板により覆
われていることを特徴とする請求項６、７または８記載
の半導体装置。9. The semiconductor chip is mounted on the chip mounting portion by flip-chip connection, and a back surface of the semiconductor chip is covered with a heat sink fixed to the frame-shaped circuit board. 9. The semiconductor device according to 6, 7, or 8.
板の部分に、チップコンデンサ等の回路部品が搭載され
ていることを特徴とする請求項９記載の半導体装置。10. The semiconductor device according to claim 9, wherein a circuit component such as a chip capacitor is mounted on a portion of the frame-shaped circuit board to which the heat sink is not fixed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9052879A JPH10256420A (en) | 1997-03-07 | 1997-03-07 | Semiconductor device and package thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9052879A JPH10256420A (en) | 1997-03-07 | 1997-03-07 | Semiconductor device and package thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10256420A true JPH10256420A (en) | 1998-09-25 |
Family
ID=12927178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9052879A Pending JPH10256420A (en) | 1997-03-07 | 1997-03-07 | Semiconductor device and package thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10256420A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201298B1 (en) | 1998-04-28 | 2001-03-13 | Nec Corporation | Semiconductor device using wiring tape |
| US6355978B1 (en) | 1999-07-19 | 2002-03-12 | Mitsubishi Denki Kabushiki Kaisha | Package for accommodating electronic parts, semiconductor device and method for manufacturing package |
-
1997
- 1997-03-07 JP JP9052879A patent/JPH10256420A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6201298B1 (en) | 1998-04-28 | 2001-03-13 | Nec Corporation | Semiconductor device using wiring tape |
| US6355978B1 (en) | 1999-07-19 | 2002-03-12 | Mitsubishi Denki Kabushiki Kaisha | Package for accommodating electronic parts, semiconductor device and method for manufacturing package |
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