JPS6046037A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6046037A JPS6046037A JP15281684A JP15281684A JPS6046037A JP S6046037 A JPS6046037 A JP S6046037A JP 15281684 A JP15281684 A JP 15281684A JP 15281684 A JP15281684 A JP 15281684A JP S6046037 A JPS6046037 A JP S6046037A
- Authority
- JP
- Japan
- Prior art keywords
- plate
- substrate
- metal substrate
- insulating plate
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体装置に関するもので、特にそりの少ない
絶縁型電力用に最適な半導体装置に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device with little warpage and optimal for insulated power use.
絶縁型電力用半導体装置は、第１図に示すように、半導
体ペレット１と金属基板２を絶縁板３を介して、ろう材
４を用いて、接合した構造となっている。この半導体装
置は、さらに、放熱板５にねじ６で取りつけられて、使
用される。As shown in FIG. 1, the insulated power semiconductor device has a structure in which a semiconductor pellet 1 and a metal substrate 2 are joined with an insulating plate 3 interposed therebetween using a brazing material 4. This semiconductor device is further attached to a heat sink 5 with screws 6 and used.
このような構成により、半導体ペレット１を、金属基板
２および放熱板５から電気的に絶縁することができる。With such a configuration, the semiconductor pellet 1 can be electrically insulated from the metal substrate 2 and the heat sink 5.
また、半導体ペレット１が電力を消費することによって
発生した熱を、ろう材４゜絶縁板３．金属基板２を通し
て、放熱板５に逃すことができる。In addition, the heat generated by the semiconductor pellet 1 consuming power is transferred to the brazing material 4° insulating plate 3. The heat can be released to the heat sink 5 through the metal substrate 2.
一般に、半導体ペレット１には、シリコンが、金属基板
２には、銅が、絶縁板３には、アルミナセラミックが、
ろう材４には、鉛錫系半田が用いられることが多い。Generally, the semiconductor pellet 1 is made of silicon, the metal substrate 2 is made of copper, and the insulating plate 3 is made of alumina ceramic.
As the brazing filler metal 4, lead-tin solder is often used.
半田付の工程で、温度を上昇させ、ろう材４をとかし、
次に、温度を下げ、ろう材４の凝固点に達するまでは、
半導体ペレット１と絶縁板３と金属基板２の３つの部品
は、互いに自由に膨張収縮できるが、凝固点でろう材４
が固まると、３つの部品は互いに接合される。このろう
材４の凝固点から常温に下げる過程で、それぞれの部品
の収縮量の差によって、そりが生ずる。In the soldering process, the temperature is raised and the brazing material 4 is melted.
Next, lower the temperature until it reaches the freezing point of the brazing filler metal 4.
The three parts, the semiconductor pellet 1, the insulating plate 3, and the metal substrate 2, can freely expand and contract with each other, but the brazing material 4 at the freezing point
Once set, the three parts are joined together. In the process of lowering the brazing filler metal 4 from its freezing point to room temperature, warping occurs due to the difference in the amount of shrinkage of each component.
一般に、金属基板２のｔＩＡ膨張係数は、絶縁板３およ
び半導体ペレット１の線膨張係数より大きい。Generally, the tIA expansion coefficient of the metal substrate 2 is larger than the linear expansion coefficient of the insulating plate 3 and the semiconductor pellet 1.
したがって、金属基板２が最も熱収縮量が大きくなるが
、金属基板２の上面は、熱収縮量の小さい絶縁板３で拘
束されているため、下面より収縮量が小さくなる。この
ため、金属基板２は下に凹なそりを生ずることになる。Therefore, the metal substrate 2 has the largest amount of thermal contraction, but since the upper surface of the metal substrate 2 is restrained by the insulating plate 3 which has a smaller amount of thermal contraction, the amount of contraction is smaller than that of the lower surface. For this reason, the metal substrate 2 will have a downward concave warp.
大きなそりが生ずると、金属基板２と放熱板５との間に
隙間７が生ずる。このため、半導体ペレット１で発生し
た熱が逃げにくくなり、半導体ペレット１の温度が上昇
し、特性の劣化が生じ易くなる。When a large warp occurs, a gap 7 is created between the metal substrate 2 and the heat sink 5. Therefore, it becomes difficult for the heat generated in the semiconductor pellet 1 to escape, the temperature of the semiconductor pellet 1 increases, and the characteristics tend to deteriorate.
本発明は、金属基板のそりが放熱などに与える影響を除
去し、金属基板と放熱板との間に密着性の良い半導体装
置を提供することを目的とするものである。An object of the present invention is to eliminate the influence of warpage of a metal substrate on heat radiation, etc., and to provide a semiconductor device with good adhesion between the metal substrate and a heat sink.
（発明の概要〕
本発明の特徴とするところは、金属基板の上に絶縁板、
半導体ペレットをろう材で接合してなる半導体装置にお
いて、金属基板の厚さ−と絶縁板の厚さの関係を一方を
他方に比べ十分厚くしたものである。(Summary of the Invention) The feature of the present invention is that an insulating plate is placed on a metal substrate.
In a semiconductor device formed by bonding semiconductor pellets with a brazing material, the relationship between the thickness of the metal substrate and the thickness of the insulating plate is such that one is sufficiently thicker than the other.
以下、本発明の半導体装置の一実施例を第２図により説
明する。半導体ペレット１と金属基板２′を、絶縁板３
′を介して、ろう材４で接合した構造となっているが、
ここで、金属基板２′は、絶縁板３′の下の部分で薄く
形成されている。この半導体装置は、さらに、放熱板５
にねじ６で取りつけられて、使用される。An embodiment of the semiconductor device of the present invention will be described below with reference to FIG. The semiconductor pellet 1 and the metal substrate 2' are connected to an insulating plate 3.
The structure is such that they are joined with brazing filler metal 4 through
Here, the metal substrate 2' is formed thin in a portion below the insulating plate 3'. This semiconductor device further includes a heat sink 5.
It is attached with screws 6 and used.
第３図は本発明の半導体装置の他の実施例で、この場合
、金属基板２＃は絶縁板３″′の下の部分で他端に厚い
ものとなっている。FIG. 3 shows another embodiment of the semiconductor device of the present invention, in which the metal substrate 2# is thicker at the other end at the lower portion of the insulating plate 3''.
このような構成により、半導体ペレット１が金属基板２
′又は２′および放熱板５から電気的に絶縁できること
、半導体ペレット１で発生した熱をろう材４．絶縁板３
′又は３′、金属基板２′又は２′を通して、放熱板５
に逃すことができる。With such a configuration, the semiconductor pellet 1 is attached to the metal substrate 2.
' or 2' and the heat sink 5, and the heat generated in the semiconductor pellet 1 can be transferred to the brazing material 4. Insulating plate 3
' or 3', and the heat sink 5 through the metal substrate 2' or 2'.
can be missed.
第２図に示すように、金属基板２′の絶縁板３′の下の
部分を絶縁板３より非常に薄くすれば、ろう付時の金属
基板２′と絶縁板３′の収縮差は、金属基板２′の絶縁
板の下の部分が全体的に引きのばされることにより吸収
され、そり量は小さくなる。そり量が小さくなわば、半
導体装置を放熱板に取り付けた場合の金属基板２′と放
熱板３′の密着がよくなり、放熱特性が向上する。As shown in FIG. 2, if the part of the metal substrate 2' below the insulating plate 3' is made much thinner than the insulating plate 3, the difference in shrinkage between the metal substrate 2' and the insulating plate 3' during brazing will be This is absorbed by stretching the entire portion of the metal substrate 2' below the insulating plate, and the amount of warpage is reduced. The smaller the amount of warpage, the better the close contact between the metal substrate 2' and the heat sink 3' when the semiconductor device is attached to the heat sink, and the heat dissipation characteristics will be improved.
一方、第３図に示すように、金属基板での絶縁板の下の
部分を絶縁板３′より十分に厚くすれば、ろう付時の金
属基板２＃と絶縁板３″の収縮差は、絶縁板３′が全体
的に圧縮されることにより吸収され、そり量は小さくな
る。On the other hand, as shown in FIG. 3, if the lower part of the insulating plate on the metal substrate is made sufficiently thicker than the insulating plate 3', the shrinkage difference between the metal substrate 2# and the insulating plate 3'' during brazing will be This is absorbed by compressing the insulating plate 3' as a whole, and the amount of warpage becomes smaller.
ろう付後の冷却によって生ずるそり量に及ぼす金属基板
と絶縁板の厚さの比の影響を計算した例を、金属基板を
銅、＃！！緑板をアルミナセラミック。Here is an example of calculating the effect of the ratio of the thickness of the metal substrate to the insulating plate on the amount of warpage caused by cooling after brazing. ! Alumina ceramic green plate.
ろう材を鉛錫系半田とした場合について、第４図に示す
。FIG. 4 shows the case where lead-tin solder is used as the brazing material.
第４図より、金属基板の厚さを絶縁板の厚さより、十分
薄くするか、または、十分厚くすることにより、そり量
を小さくすることができることがわかる。From FIG. 4, it can be seen that the amount of warpage can be reduced by making the thickness of the metal substrate sufficiently thinner or thicker than the thickness of the insulating plate.
今、そり量の許容値を０．１ ｗｒｈ程度とすれば、金
属基板厚さを絶縁板厚さの一以下または、４倍以上とす
ればよいことがわかる。Now, if the allowable value for the amount of warpage is about 0.1 wrh, it is understood that the thickness of the metal substrate should be one or less or four times or more the thickness of the insulating plate.
（発明の効果〕
本発明によれば、金属基板のそり量が小さくなるので、
絶縁板との間の密着性が良くなり、放熱特性が向上する
。(Effect of the invention) According to the invention, since the amount of warpage of the metal substrate is reduced,
The adhesion with the insulating plate is improved, and the heat dissipation characteristics are improved.
第１図は、従来の絶縁型電力用半導体装置を放熱板に取
り付けた状態を示す側面図、第２図は、本発明の一実施
例を示す側面図、第３図は、本発明の他の実施例を示す
側面図、第４図は、ろう付後の冷却によって生ずるそり
量を及ぼす金属基板と絶縁板の厚さの比の影響を計算し
た例を示す図である。
１・・・半導体ペレット、２’ 、２’・・・金属基板
、五 ＩＩｉ］
肩 Ｚｌｌｕ
ＹＪ ３ 図
第４図
Ｓｐ、’：５ｌｌ−
Ｕ弓〆FIG. 1 is a side view showing a conventional insulated power semiconductor device attached to a heat sink, FIG. 2 is a side view showing an embodiment of the present invention, and FIG. 3 is a side view showing an embodiment of the present invention. FIG. 4 is a side view showing the embodiment of the present invention, and is a diagram showing an example of calculating the effect of the ratio of the thickness of the metal substrate to the insulating plate on the amount of warpage caused by cooling after brazing. 1... Semiconductor pellet, 2', 2'... Metal substrate, 5 IIi] Shoulder Zllu YJ 3 Figure 4 Sp, ': 5ll- U bow
Claims (1)
接合してなる半導体装置において、金属基板の厚さと絶
縁板の厚さとの関係を一方を他方に比べ十分厚くしたこ
とを特徴とする半導体装置。 ２、金属基板の厚さを絶縁板の厚さの一以下としたこと
を特徴とする特許請求の範囲第１項記載の半導体装置。 ３、金属基板の厚さを絶縁板の厚さの４倍以上としたこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
。[Claims] 1. In a semiconductor device formed by bonding an insulating plate and a semiconductor pellet onto a metal substrate using a brazing material, the relationship between the thickness of the metal substrate and the thickness of the insulating plate is such that one is sufficiently thicker than the other. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the thickness of the metal substrate is one or less of the thickness of the insulating plate. 3. The semiconductor device according to claim 1, wherein the thickness of the metal substrate is four times or more the thickness of the insulating plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15281684A JPS6046037A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15281684A JPS6046037A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6046037A true JPS6046037A (en) | 1985-03-12 |
Family
ID=15548781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15281684A Pending JPS6046037A (en) | 1984-07-25 | 1984-07-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6046037A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5378924A (en) * | 1992-09-10 | 1995-01-03 | Vlsi Technology, Inc. | Apparatus for thermally coupling a heat sink to a lead frame |
| US7102226B2 (en) * | 2001-12-21 | 2006-09-05 | Intel Corporation | Device and method for package warp compensation in an integrated heat spreader |
-
1984
- 1984-07-25 JP JP15281684A patent/JPS6046037A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5378924A (en) * | 1992-09-10 | 1995-01-03 | Vlsi Technology, Inc. | Apparatus for thermally coupling a heat sink to a lead frame |
| US5442234A (en) * | 1992-09-10 | 1995-08-15 | Vlsi Technology, Inc. | Apparatus for thermally coupling a heat sink to a leadframe |
| US7102226B2 (en) * | 2001-12-21 | 2006-09-05 | Intel Corporation | Device and method for package warp compensation in an integrated heat spreader |
| US7256058B2 (en) | 2001-12-21 | 2007-08-14 | Intel Corporation | Device and method for package warp compensation in an integrated heat spreader |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4670771A (en) | Rectifier module | |
| JPH04162756A (en) | Semiconductor module | |
| JPS61176142A (en) | Substrate structure | |
| JPS59130449A (en) | Insulation type semiconductor element | |
| JP2002299495A (en) | Semiconductor circuit board | |
| JPS6046037A (en) | Semiconductor device | |
| JPS60113931A (en) | Semiconductor device | |
| JPH0322706B2 (en) | ||
| JPH0677631A (en) | Mounting method of chip component onto aluminum board | |
| JP2558574B2 (en) | Semiconductor device | |
| KR0183010B1 (en) | Semiconductor device having particular solder interconnection arrangement | |
| JPS62216251A (en) | High thermal conductive substrate | |
| JP3522975B2 (en) | Semiconductor device | |
| JPH0558569B2 (en) | ||
| JP2619155B2 (en) | Hybrid integrated circuit device | |
| KR102564818B1 (en) | Power module and manufacturing method thereof | |
| JPS58102532A (en) | Semiconductor device | |
| Xu et al. | Thermal performance and reliability management for novel power electronic packaging using integrated base plate | |
| JPS5832423A (en) | Semiconductor device | |
| JPS6076179A (en) | Thermoelectric converter | |
| JP2006041231A (en) | Ceramic circuit board and electric apparatus | |
| JPS5952853A (en) | Semiconductor device | |
| JP4123717B2 (en) | Manufacturing method of chip type semiconductor device | |
| JPH05299445A (en) | Semiconductor device sealed with resin | |
| JPH0214557A (en) | Semiconductor device |