JPS5990938A - Printed circuit board for semiconductor device - Google Patents

Printed circuit board for semiconductor device

Info

Publication number
JPS5990938A
JPS5990938A JP57201542A JP20154282A JPS5990938A JP S5990938 A JPS5990938 A JP S5990938A JP 57201542 A JP57201542 A JP 57201542A JP 20154282 A JP20154282 A JP 20154282A JP S5990938 A JPS5990938 A JP S5990938A
Authority
JP
Japan
Prior art keywords
plating
printed circuit
gold
circuit board
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57201542A
Other languages
Japanese (ja)
Inventor
Hirofumi Nakajima
中島　宏文
Seiichi Nishino
西野　誠一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57201542A priority Critical patent/JPS5990938A/en
Publication of JPS5990938A publication Critical patent/JPS5990938A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To make possible the direct wire bonding and suppress the abrasion of contact land by executing soft gold plating to the element connecting part on the nickel plating and hard gold plating in the plating structure in an external connecting terminal circuit. CONSTITUTION:Wiring is formed by etching the laminated board made of the copper-clad glass epoxy, nickel plating is conducted thereto and hard gold plating is carried out to the entire part of the printed circuit board 31. Next, the contact land 32 is partly masked 33 for partial plating and soft gold plating is further conducted to the soft-gold plated wiring layer 34 for wire bonding. Thereafter, the mask 33 is melted and washing is carried out. A printed circuit board 35 can be obtained. Connection of gold wire is possible by the thermal pressure wire bonding in combination with ultrasonic wave and the contact land which may generate mechanical abrasion is subjected to hard gold-plating with less which assures less abrasion.

Description

【発明の詳細な説明】 本発明は半塙・体装撓を用プリント回路基板にかがシ、
とくに半導体素子を直接プリント回路基板に搭載し、半
導体素子上の電極パッドと基板上のプリントされた回路
をワイヤボンデインクして結線しかつ同一基板内にある
外部接絞端子用パターンでソケットなどに挿入して使用
される半導体装置用プリント回路基板に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for applying a half-wall/body flexure to a printed circuit board.
In particular, it is possible to directly mount a semiconductor element on a printed circuit board, connect the electrode pads on the semiconductor element and the circuit printed on the board by wire bonding, and use the external contact terminal pattern on the same board to connect it to a socket, etc. The present invention relates to a printed circuit board for a semiconductor device that is inserted and used.

従来、デジタル時計や液晶表示の電子オモチャには半導
体装置の厚さが薄いものが要求されている為に、プリン
ト回路基板に直接半導体素子を搭載し、ワイヤボンディ
ングによってプリント基板上の配線と直接結線するチッ
プオンボードと呼ばれるパッケージが用いられていた。Conventionally, digital watches and electronic toys with LCD displays require thin semiconductor devices, so semiconductor elements are mounted directly on printed circuit boards and connected directly to the wiring on the printed circuit board using wire bonding. A package called chip-on-board was used.

第１図は従来採用されてきたチップオンボードの断面図
であり、１１は一般にプリント回路基板と称されている
絶縁性基板で、その表面には多数の配線層１２が形成さ
れている。半導体素子１３は適当な接着羽層１４によ如
プリント回路基板の表面に固着され、多数のボンディン
グワイヤ１５を介して対応する配線層１２に電気的に接
続されている。そして半導体素子１３とボンディングワ
イヤ１５．配線層１２は有機レンジ１６によっておおわ
れている。ボンティングワイヤによって結線される配線
層１２は、ボンディング性を向上さぜる為に銅箔にニッ
ケルメッキを施し、その上から９９．９９１以上の金メ
ッキを施す。このような構造は金メッキがワイヤボンデ
ィング用の結線金属の役割を果すと七もに、スイッチ部
のコンタクト金趙として、また良好な半田付を有するメ
ッキとして非常に優れた特性を示している。しかしなが
ら、９９．９９％以上の金メッキは硬度が低いために機
械摩擦を生ずる方式のスイッチ部についてはメッキの摩
滅が激しく、下地のニッケルメッキが無用してくる。摩
滅してニッケルが露出した状態では、ニッケルの硬度が
非常に高い為に逆にスイッチの相手側の金属を摩滅させ
ることになる。デジタル時計や液晶表示電子オモチャ等
、従来よりチップオンボード構造を採用していたものは
全て押しボタンスイッチ型のコンタクト形式であシ、上
述した摩滅がないパッケージであった。FIG. 1 is a sectional view of a conventional chip-on-board. Reference numeral 11 is an insulating substrate generally called a printed circuit board, and a large number of wiring layers 12 are formed on the surface of the insulating substrate. The semiconductor element 13 is fixed to the surface of the printed circuit board by a suitable adhesive layer 14 and electrically connected to the corresponding wiring layer 12 via a number of bonding wires 15. Then, the semiconductor element 13 and the bonding wire 15. The wiring layer 12 is covered by an organic range 16. For the wiring layer 12 connected by bonding wires, copper foil is plated with nickel in order to improve bonding properties, and then gold plated with 99.991 or more is applied thereon. In this structure, the gold plating not only plays the role of a connection metal for wire bonding, but also has excellent properties as a contact metal for a switch section and as a plating with good solderability. However, since gold plating of 99.99% or more has a low hardness, the plating is subject to severe abrasion in switch parts that generate mechanical friction, making the underlying nickel plating useless. If the nickel is worn away and exposed, it will actually wear away the other metal of the switch because nickel is extremely hard. All products that have conventionally adopted a chip-on-board structure, such as digital watches and electronic toys with liquid crystal displays, have had push-button switch type contacts, and have the above-mentioned wear-free packages.

しかるに、最近チップオンボードの一端にコンタクトラ
ンドを設け、他の電子装置のコネクターに差し込んで使
用する型のパッケージが要求されるようになり、前述の
摩滅が問題となった。However, recently there has been a demand for a type of package that has a contact land at one end of the chip-on-board and is used by being inserted into a connector of another electronic device, and the above-mentioned wear and tear has become a problem.

一般的にコンタクトランドには硬質金メッキを施して摩
滅を防止するが、チップオンボードの金メッキに硬質金
を採用した場合、通常のメッキ方式ではプリント基板上
の配線層も硬質となる。しかるに硬質金メッキは不純物
濃度が高い為に熱圧着によるワイヤボンディングをした
場合、ワイヤが配線層から剥れ、電気的接続が不可能と
なる問題があることは良く知られている。Generally, contact lands are plated with hard gold to prevent abrasion, but when hard gold is used for chip-on-board gold plating, the wiring layer on the printed circuit board also becomes hard using the normal plating method. However, it is well known that hard gold plating has a high impurity concentration, so when wire bonding is performed by thermocompression, the wire peels off from the wiring layer, making electrical connection impossible.

かかる間融の対策としては、通常部分メッキによって二
種類の異なるメッキを各部分に行なうのであるが、プリ
ント回路基板の場合、表面と矢面を結ぷスルホールにも
金メッキを浩ｊねばならない。この為には基板をメッキ
液に浸すことが必要で、部分メッキを行なう方法として
プリント基板に部分メッキ用のマスクを二回かりること
になる。As a countermeasure against such melting, two different types of plating are usually applied to each part by partial plating, but in the case of printed circuit boards, gold plating must also be applied to the through-holes that connect the surface and the main surface. For this purpose, it is necessary to immerse the board in a plating solution, and as a method of performing partial plating, a mask for partial plating is applied twice to the printed circuit board.

第２図に二種類のメッキを行なう場合の部分メッキ工程
を示す。エツチングによって配線を形成し、ニッケルメ
ッキを行なった後（Ｍ２図（Ａ））のプリント回路基板
２１の配線層部２２に部分メッキ用のマスク２３をかけ
て（第２図（Ｂ））硬質金メッキ浴でメッキを行なうと
コンタクトランド２４だけに６ｔｌ金メツキかなされる
。次にマスク２３を浴して（第２図（Ｃ））洗浄した基
板２５に、更に部分メッキ用マスク２６をコンタクトラ
ンドにかりる。この基枦を軟質金メッキ浴に入れてメッ
キを行なうと配紛部２２が軟質金メッキされる（第２図
（Ｄ））。最後に杓びマスク２６を溶して洗浄し、最終
状態である二ａ類のメッキされた回路基板を得る（第２
図のン）。このような工程は複数なうえ、高価なソルダ
ーマスクを２回かりるので、コストが高くなシ、また製
造能力も低い。FIG. 2 shows a partial plating process in which two types of plating are performed. After wiring is formed by etching and nickel plating is performed (Fig. M2 (A)), a mask 23 for partial plating is applied to the wiring layer portion 22 of the printed circuit board 21 (Fig. 2 (B)), and hard gold plating is applied. When plating is performed in a bath, only the contact land 24 is plated with 6TL gold. Next, a partial plating mask 26 is applied to the contact land on the substrate 25 which has been cleaned by applying a mask 23 (FIG. 2(C)). When this base plate is placed in a soft gold plating bath and plated, the powder distribution portion 22 is plated with soft gold (FIG. 2(D)). Finally, the ladle mask 26 is melted and cleaned to obtain a plated circuit board of type 2a in the final state (second
). Such steps are multiple, and expensive solder masks are required twice, resulting in high costs and low manufacturing capacity.

本発明は上述の状況を鑑みてなされたものであり、その
目的とするところはフリント回路基板の配線に直接ワイ
ヤボンデインクが可能であシ、かつコンタクトランドが
摩滅しにくい硬質金メッキである安価な卑−枡を得るこ
とにある。The present invention was made in view of the above-mentioned circumstances, and its purpose is to provide an inexpensive method that allows direct wire bonding ink to the wiring of a flint circuit board, and that has contact lands made of hard gold plating that is resistant to wear. The purpose is to gain a sense of humility.

本発明は銅張積層基板をエツチングして回路を形成する
プリント回路基板で同一基板内に外部接続端子回路と素
子搭載回路を有する基板の素子搭載回路のメッキ構成が
外部接続端子回路におけるメッキ構成のニッケルメッキ
、硬質金メッキを施した上にすくなくとも素子接続部に
軟質金メッキを施したことを特徴とする半導体装置用プ
リント回路基板である。The present invention relates to a printed circuit board in which a circuit is formed by etching a copper-clad laminated board, and has an external connection terminal circuit and an element mounting circuit on the same board. This is a printed circuit board for a semiconductor device characterized by being nickel plated, hard gold plating, and soft gold plating applied to at least the element connection portions.

本発明を実施例について説明する。第３図は本発明の実
施例を示す。ガラスエポキシに銅張したラミネート基板
をエツチングによって配線形式しく第３図（Ａ））、ニ
ッケルメッキを行なった後のプリント回路基板３１に全
面硬質金メッキを行なう（第３図（Ｂ））。次にコンタ
クトランド３２に部分メッキ用マスク３３をかけ、硬質
金メッキされているワイヤボンディング用配線層３４に
更に軟賀金メッキを施す（第３図Ｃ１）。その後マスク
３３を浴して洗浄し、本発明によるプリント回路基板３
５を旬る（第３図（Ｄ））。The present invention will be described with reference to examples. FIG. 3 shows an embodiment of the invention. A laminate board made of glass epoxy coated with copper is etched to form wiring (FIG. 3(A)), and after nickel plating, the entire surface of the printed circuit board 31 is plated with hard gold (FIG. 3(B)). Next, a partial plating mask 33 is applied to the contact land 32, and soft gold plating is further applied to the hard gold-plated wire bonding wiring layer 34 (FIG. 3 C1). The mask 33 is then bathed and cleaned, and the printed circuit board 3 according to the invention is
5 (Figure 3 (D)).

このようにして製作した基徊は超音波並用の熱圧着ワイ
ヤボンディングによって金線結線が可能であシ、かつ機
械的摩擦の生ずるコンタクトランドは摩滅の少ない硬質
金メッキとなった。The base fabricated in this way can be connected with gold wire by thermocompression wire bonding, which is comparable to ultrasonic waves, and the contact lands, where mechanical friction occurs, are plated with hard gold, which causes less wear.

本発明によれは高価な部分メッキ用マスクも１回ですま
すことができ、原価を低減することができる。また、コ
ンタクトランドは機械的摩滅から金メッキ厚として軟質
金メッキならば０．５〜１μ必要であるが、硬質金メッ
キならは０．２μ〜０．５μで十分な規格であシ、金量
な削減することもできるのでその効果は著しい。According to the present invention, an expensive partial plating mask can be used only once, and the cost can be reduced. In addition, the contact land needs to have a gold plating thickness of 0.5 to 1μ for soft gold plating to prevent mechanical abrasion, but for hard gold plating, 0.2μ to 0.5μ is a sufficient standard, and the amount of gold can be reduced. The effect is remarkable because it can also be done.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のチップオンボードの断面図。 第２図は２柚類のメッキを基板に施う“基１合の従来の
方法を示す図、第３図は本発明の実施例によるプリント
回路基板のメッキを施す方法を示す図である。 尚、図において、１１・・・・・・ガラスエポキシ、１
２・・・・・・ワイヤボンディング用配線層、１３・・
・・・・半導体素子、１４・・・・・・接着材層、１５
・・・・・・ボンディングワイヤ、１６・・・・・・有
機レジン、２１．３１・・・・・・ニッケルメッキＪ１
のプリント基板、２２．３４・・・・・・ワイヤボンテ
ィング用配線部、２３，２６．３３・・・・・・部分メ
ッキ用マスク、２４．３２・・・°°°コンタクトラン
ド、２５・旧・・プリント基板、２７．３５・・・・・
・Ｚｆｌｋ類のメッキが施されたプリント回路基板であ
る。 第　Ｚ　図Figure 1 is a cross-sectional view of a conventional chip-on-board. FIG. 2 is a diagram illustrating a conventional method of plating a printed circuit board according to an embodiment of the present invention. In addition, in the figure, 11...Glass epoxy, 1
2...Wiring layer for wire bonding, 13...
... Semiconductor element, 14 ... Adhesive layer, 15
...Bonding wire, 16...Organic resin, 21.31...Nickel plating J1
Printed circuit board, 22.34... Wiring part for wire bonding, 23, 26.33... Mask for partial plating, 24.32...°°° Contact land, 25. Old...Printed circuit board, 27.35...
- It is a printed circuit board plated with Zflk type. Figure Z

Claims (1)

【特許請求の範囲】[Claims] 銅張シ積層基板をエツチングして回路を形成し、同一基
板内に外部接続端子回路と素子搭載回路とを崩する半導
体装置用プリント回路基板において、素子搭載回路のメ
ッキ構成が、外部接続端子回路におけるメッキ構成のニ
ッケルメッキ、硬質金メッキを施むした上にすくなくと
も素子接続部に軟質金メッキを施こしたことを％徴とす
る半導体装置用プリント回路基板。In printed circuit boards for semiconductor devices, in which a circuit is formed by etching a copper-clad laminated board, and an external connection terminal circuit and an element mounting circuit are separated on the same board, the plating structure of the element mounting circuit is different from the external connection terminal circuit. A printed circuit board for a semiconductor device having a plating composition of nickel plating, hard gold plating, and soft gold plating at least on the element connection parts.
JP57201542A 1982-11-17 1982-11-17 Printed circuit board for semiconductor device Pending JPS5990938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57201542A JPS5990938A (en) 1982-11-17 1982-11-17 Printed circuit board for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57201542A JPS5990938A (en) 1982-11-17 1982-11-17 Printed circuit board for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5990938A true JPS5990938A (en) 1984-05-25

Family

ID=16442768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57201542A Pending JPS5990938A (en) 1982-11-17 1982-11-17 Printed circuit board for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5990938A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0594427A3 (en) * 1992-10-21 1995-06-21 Nippon Electric Co A printed circuit board mounted with electric elements thereon.
EP0884935A3 (en) * 1997-06-11 2000-03-08 International Business Machines Corporation Universal surface finish for DCA SMT, and pad on pad interconnections
US6091137A (en) * 1996-05-31 2000-07-18 Kabushiki Kaisha Toshiba Semiconductor device substrate and method of manufacturing the same
JP2002124744A (en) * 2000-10-12 2002-04-26 Eastern Co Ltd Circuit board
US6528769B2 (en) 2000-04-03 2003-03-04 Schott Glas Connection of a junction to an electrical conductor track on a plate

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0594427A3 (en) * 1992-10-21 1995-06-21 Nippon Electric Co A printed circuit board mounted with electric elements thereon.
US6091137A (en) * 1996-05-31 2000-07-18 Kabushiki Kaisha Toshiba Semiconductor device substrate and method of manufacturing the same
EP0884935A3 (en) * 1997-06-11 2000-03-08 International Business Machines Corporation Universal surface finish for DCA SMT, and pad on pad interconnections
US6528769B2 (en) 2000-04-03 2003-03-04 Schott Glas Connection of a junction to an electrical conductor track on a plate
JP2002124744A (en) * 2000-10-12 2002-04-26 Eastern Co Ltd Circuit board

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