JP2762500B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial application fields B. Summary of the invention C. Prior art [FIGS. 5 and 6] D. Problems to be solved by the invention [FIG. 6] E. Means for solving problems F. Function G. Embodiment [FIGS. 1 to 4] H. Effects of the Invention (A. Industrial Application Field) The present invention relates to a semiconductor device, particularly to a semiconductor device having alignment marks formed thereon.

(B. Summary of the Invention) The present invention forms a breakwater in a semiconductor device in which an alignment mark is formed, in order to prevent the visibility of the alignment mark through the resist film from lowering, thereby preventing the alignment accuracy from lowering. An alignment mark is formed on a line pattern inside a plurality of parallel line patterns.

(C. Prior Art) [FIGS. 5 and 6] In recent years, the integration of ICs, LSIs, and VLSIs has become remarkable, and accordingly, the necessity of improving the alignment accuracy of masks has increased. And the alignment is JP-B 63-47330
As described in Japanese Patent Application Laid-Open Publication No. H10-209, alignment marks are formed on the surface of a substrate, and the positional relationship between the mask and the substrate is made to be a predetermined position using the marks as an index. Particularly recently, in order to further increase the alignment accuracy, a rectangular shape in which a plurality of, for example, convex portions are arranged in a predetermined direction is formed as an alignment mark at an appropriate position on a semiconductor wafer, and then a resist film is formed. The alignment is performed by visually recognizing the alignment mark through the resist film and setting the positional relationship between the alignment mark and the mask as predetermined.

By the way, when a fine pattern is formed by photolithography, a photoresist film is formed by a spin coating method (spin coating method) in which a semiconductor wafer is coated while being rotated. As a result, the following inconvenience occurs. FIGS. 5 (A) and 5 (B) are for explaining such inconvenience. FIG. 5 (A) is a cross-sectional view showing step coverage near a rotation center, and FIG. FIG. 5 is a cross-sectional view showing step coverage in a portion far from the center (close to the periphery of the semiconductor wafer a). As is clear from FIG. 3A, in the portion near the center of rotation, the step of the photoresist film c is not only on the step on the rotation center side of the mark b (for example, made of aluminum) but also on the opposite side. There is no change in the coverage, and the step coverage has symmetry. However, as shown in FIG. 4B, as the semiconductor wafer a becomes closer to the periphery, the step coverage of the photoresist film c is good at the step on the rotation center side, but deteriorates at the step on the opposite side.

Such asymmetry of the step coverage becomes remarkable as the diameter of the semiconductor wafer a increases.
If such asymmetry occurs in the step coverage, mask alignment is performed by a general mask alignment method in which the alignment mark on the chip is scanned with laser light to detect temporary light of diffracted light irregularly reflected on the mark. In this case, the reflected light of the alignment light at the mark where the step coverage is asymmetric is bent due to light refraction, which causes a problem that accurate mask alignment cannot be performed.

Therefore, as shown in FIGS. 6 (A) and 6 (B), it is conceived to form patterns d, d to be breakwaters on both sides of the alignment mark b to reduce the asymmetry of the step coverage of the resist film c. Was done. In this way, the asymmetry of the step coverage of the resist film between the step closer to the center of the semiconductor wafer and the step farther from the center can be actually reduced. Therefore, an alignment error due to the asymmetry of the step coverage can be reduced. The breakwater patterns d and d are formed of aluminum in the same manner as the alignment mark b.

(D. Problems to be Solved by the Invention) [FIG. 6] By the way, as shown in FIGS. 6 (A) and (B), line patterns d, d serving as breakwaters are provided on both sides of the alignment mark b. In such a case, the film thickness t of the resist film c on the alignment mark b is increased, so that visibility (visibility) is deteriorated, and as a result, alignment accuracy is deteriorated. That is,
By providing the line patterns d and d serving as breakwaters, the decrease in alignment accuracy due to the asymmetry of the step coverage with respect to the alignment mark b of the resist film c is reduced, but the visibility is reduced due to the increase in the thickness of the resist film. As a result, the alignment accuracy is reduced, and the alignment accuracy cannot be sufficiently improved.

The present invention has been made in order to solve such a problem. Not only is the visibility reduced due to the asymmetry of the step coverage of the resist film, but also the visibility is increased due to an increase in the film thickness of the resist film on the alignment mark. It is an object of the present invention to effectively prevent the lowering of the alignment and improve the alignment accuracy.

(E. Means for Solving the Problems) In order to solve the above problems, the semiconductor device of the present invention has an alignment mark formed on a line pattern inside a plurality of parallel line patterns serving as breakwaters. .

(F. Function) According to the semiconductor device of the present invention, since the alignment mark is formed on the line pattern, the thickness of the resist film on the alignment mark can be reduced by the thickness of the line pattern. Consequently, the visibility of the alignment mark seen through the resist film can be increased. In addition, since there is a line pattern serving as a breakwater, the asymmetry of the step coverage of the resist film can be reduced. Therefore, a decrease in alignment accuracy due to the asymmetry of the step coverage of the resist film can be prevented as before.

 Accordingly, alignment accuracy can be increased.

(G. Embodiment) [FIGS. 1 to 4] Hereinafter, a semiconductor device of the present invention will be described in detail with reference to illustrated embodiments.

1 and 2 show one embodiment of the semiconductor device of the present invention. FIG. 1 is a plan view, and FIG.
FIG.

In the drawing, 1 is a semiconductor wafer, 2, 3, and 2 are line patterns formed in parallel on the surface of the semiconductor wafer 1 and are made of, for example, aluminum, and the line patterns 2 and 2 on both sides are asymmetrical in the above-described step coverage. It becomes a breakwater to reduce the nature.

Reference numeral 3 denotes a center line pattern, 4, 4,..., Alignment marks formed on the line pattern 3, which are made of, for example, an insulating film such as SiO ₂ . Reference numeral 5 denotes a resist film formed on the semiconductor wafer 1.

According to such a semiconductor device, the asymmetry of the step coverage of the resist film 5 is reduced due to the presence of the line patterns 2 and 2 serving as breakwaters, and a decrease in alignment accuracy due to the asymmetry can be prevented. Since the use mark 4 is formed on the line pattern 3, the thickness t of the resist film 5 on the alignment mark 4 can be reduced by the thickness of the line pattern 3. The visibility over the resist film can be increased.
Therefore, the breakwater can be raised.

FIGS. 3A and 3B show a method of manufacturing the semiconductor device shown in FIGS. 1 and 2 in the order of steps. In this method, first, an aluminum film is formed on a semiconductor wafer 1 and selectively etched to form line patterns 2, 3, and 2 as shown in FIG. (Interlayer insulating film) is formed and selectively etched to form an alignment mark 4 as shown in FIG.

4 (A) to 4 (D) are cross-sectional views showing a modification of the method for manufacturing the semiconductor device shown in FIG. 3 in the order of steps, and the left part shows where a contact hole of an integrated circuit is formed. , The right part shows where the alignment mark is formed.

(A) An insulating film 6 is formed on a semiconductor wafer 1 and then a required contact hole or through hole 7 is formed by selectively etching the insulating film 6. FIG. 7A shows a state after the formation of the holes 7, and as is clear from this figure, the insulating film does not exist in the alignment mark forming portion (right portion).

(B) Next, as shown in FIG. 3B, a first-layer aluminum wiring film 8 is formed. 8a is a mark base film formed simultaneously with the aluminum wiring film 8. The base film 8a is formed to increase the height of the alignment mark where the alignment mark is to be formed later.

(C) Next, an interlayer insulating film 9 is formed as shown in FIG. Reference numeral 9a denotes an alignment mark formed simultaneously with the interlayer insulating film 9 and is formed on the mark base film 8a.

(D) Thereafter, a second-layer aluminum wiring film 10 is formed as shown in FIG. Numeral 11 denotes a projection formed on the alignment mark 9a of the aluminum wiring film 10,
These projections substantially function as alignment marks.

In this manufacturing method, an alignment mark 9a made of an insulating film is formed on a base film 8a made of aluminum of a first layer, so that a portion of the second layer 10 on the alignment mark 9a made of aluminum is formed of an aluminum wiring layer. The protrusions 11 remain even after the flattening process on the layer 10 and function as substantial alignment marks.

That is, conventionally, when an alignment mark made of an insulating film is formed on the surface of a semiconductor wafer and then an aluminum wiring film is formed on the surface, a portion of the aluminum wiring film on the alignment mark is raised by the alignment mark. There is a technique of using the raised portion as a substantial alignment mark. However, this technique cannot be applied to the latest method of manufacturing a semiconductor device having a step of flattening an aluminum wiring film.
This is because the portion of the aluminum wiring film on the alignment mark is also flattened in the flattening step.

Therefore, in the manufacturing method shown in FIG. 4, the base film 8a is formed in advance before the formation of the alignment mark 9a, and the alignment mark 9a is formed on the base film 8a to form the alignment mark 9a. Make it higher. By doing so, the aluminum wiring film 10 is raised above the alignment mark 9a, and the raised portion 11
Can function as an alignment mark.

(H. Effects of the Invention) As described above, the semiconductor device of the present invention is characterized in that an alignment mark is formed on at least an inner line pattern of a plurality of line patterns arranged in parallel. Is what you do.

Therefore, according to the semiconductor device of the present invention, since the alignment mark is formed on the line pattern, the thickness of the resist film on the alignment mark can be reduced by the thickness of the line pattern. The visibility of the alignment mark seen through the film can be increased. In addition, since there is a line pattern serving as a breakwater, the asymmetry of the step coverage of the resist film can be reduced.

 Accordingly, alignment accuracy can be increased.

[Brief description of the drawings]

1 to 3 are views for explaining one embodiment of the semiconductor device of the present invention. FIG. 1 is a plan view, and FIG.
3 (A) and 3 (B) are cross-sectional views showing the manufacturing method in the order of steps, and FIGS. 4 (A) to (D) are cross-sectional views of the manufacturing method shown in FIG. Sectional view showing a modified example in the order of steps,
5 (A) and 5 (B) are cross-sectional views showing the asymmetry of the conventional step coverage. FIG. 5 (A) shows a portion closer to the rotation center, and FIG. 5 (B) shows a portion farther from the rotation center. 6 (A) and 6 (B) are cross-sectional views showing a conventional example and its problems. FIG. 6 (A) shows a portion closer to the rotation center and FIG. 6 (B) shows a portion farther from the rotation center. . Description of symbols 2, 2,.

Claims (1)

(57) [Claims] 1. A semiconductor device, wherein an alignment mark is formed on at least an inner line pattern of a plurality of line patterns arranged in parallel.