CN105448713A - Manufacturing method of vacuum cavity gate structure pseudomorphic high electron mobility transistor - Google Patents
Manufacturing method of vacuum cavity gate structure pseudomorphic high electron mobility transistor Download PDFInfo
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- CN105448713A CN105448713A CN201510878221.3A CN201510878221A CN105448713A CN 105448713 A CN105448713 A CN 105448713A CN 201510878221 A CN201510878221 A CN 201510878221A CN 105448713 A CN105448713 A CN 105448713A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 39
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 238000001312 dry etching Methods 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000001039 wet etching Methods 0.000 claims description 14
- 238000005566 electron beam evaporation Methods 0.000 claims description 11
- 150000001875 compounds Chemical class 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 238000002161 passivation Methods 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000012545 processing Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims description 2
- 108090000723 Insulin-Like Growth Factor I Proteins 0.000 claims description 2
- 102000013275 Somatomedins Human genes 0.000 claims description 2
- 238000013461 design Methods 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 8
- 230000008020 evaporation Effects 0.000 abstract description 7
- 238000001704 evaporation Methods 0.000 abstract description 7
- 230000003628 erosive effect Effects 0.000 abstract description 5
- 230000007797 corrosion Effects 0.000 abstract description 4
- 238000005260 corrosion Methods 0.000 abstract description 4
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 3
- 229910018557 Si O Inorganic materials 0.000 abstract description 2
- 230000003071 parasitic effect Effects 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000001737 promoting effect Effects 0.000 description 3
- 238000004064 recycling Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000276 deep-ultraviolet lithography Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention discloses a manufacturing method of a vacuum cavity gate structure pseudomorphic high electron mobility transistor. The method comprises the following steps: growing a stack gate medium on the surface of a semiconductor, and using photoresist as a mask film; using the difference of dry method (or a wet method) etching for etching (or corrosion) speed of different gate media; forming holes with controllable shapes, specifications and sizes in two sides of gate pins through etching (or corrosion); and carrying out gate evaporation peeling so as to obtain a T-shaped gate with good profile shape and controllable stray capacitance. The manufacturing method has the advantages that thin Si-O layers are inserted among three layers of gate media (which are compact, loosened and compact) to form a five-layer medium structure; an appropriate lateral erosion depth is formed by adjusting dry method etching conditions; and meanwhile, the thickness proportion of each medium layer can also be adjusted for controlling the lateral erosion height, and then the sizes of formed medium cavities are controlled; and after the gate evaporation peeling, a medium cavity with controllable size can be formed below the gate cap of the T-shaped gate, so that the gate stray capacitance is reduced, and the frequency characteristic promotion becomes controllable.
Description
Technical field:
The present invention relates to the grid preparation method of a kind of two generations and three generations's semiconductor high-mobility field-effect transistor.Belong to technical field of semiconductors.In Engineering applications of microwave and millimeter waves, forming grid metal medium cavity to reduce grid parasitic capacitance by suitable process means is improve the effective means of device high frequency performance.The gate medium cavity formation method that the present invention proposes can, by the size in adjustment medium cavity, make grid parasitic capacitance reduce more controlled advantage, has much using value for raising microwave and millimeter wave device correlated performance.
Background technology:
Compound semiconductor materials compares traditional silicon materials, has the features such as mobility is high, energy gap is large, is therefore widely used in the field such as high frequency, microwave.Along with the development of compound semiconductor device, the fields such as wireless communications market, space flight, military issue weapons equipment also propose higher requirement for the performance of microwave transistor.In order to realize higher gain, lower noise, faster operating rate, a large amount of energy that various countries all drop in compound semiconductor research and development field.
For microwave and millimeter wave device, promoting one of Main Means of frequency characteristic is reduce device gate length to reach the object promoting frequency characteristic with the transit time reducing channel electrons.The grid of current domestic and international advanced GaAs, InP, GaN device are long has narrowed down to level within 100nm, and the increase of the gate resistance brought becomes one of key factor of restriction small size device performance boost thereupon, in order to solve the problem that gate resistance increases, usually taking the method increasing grid cover size, is also so-called T-shaped grid, Y type grid or Mushroom Gate.
And thisly still do not claim to be a kind of perfectly solution by increasing grid cover size to reach the technological means reducing grid resistance, because the parasitic capacitance that large scale grid cover is introduced can cause the decline of device frequency characteristic.Especially for the long device of little grid, its intrinsic capacity is little, parasitic capacitance is relatively large, and parasitic capacitance becomes the principal element affecting device frequency characteristic, so for microwave and millimeter wave device, the core promoting frequency characteristic is to reduce grid parasitic capacitance.
A kind of method of conventional reduction dielectric constant impact is naked grid technique, namely before grid evaporation of metal, gate medium is not grown, the direct glue-type being obtained wanting by electron-beam direct writing or deep UV lithography on material, after grid evaporation of metal, glue-type is converted into grid-type, stripping obtains metal gate, grows the isotropic medium parcel of one deck afterwards, completes grid passivation.Naked grid technique itself has certain deficiency, comprising: owing to not having dielectric support, easily cause down grid, and before grid passivation, grid barrier metal is directly exposed in air, can affect the Schottky contacts of grid potential barrier when grid are peeled off.
Under grid cover metal, form medium cavity is another conventional means reducing grid parasitic capacitance, because compared to SiN
xdielectric capacitance, vacuum (air) the dielectric capacitance value of same size is about the former 1/7.Usually after T-shaped grid metal forming, utilize the dry etching of isotropic hardening to be removed by the medium of assistant formation, the method growth protecting medium that recycling anisotropy is strong, form shutoff cavity because all directions growth rate is different.The problem of this technique is that the step of dry etching assistant formation medium can bring damage to the surface of device, and utilize anisotropic approaches to grow the vacuum hole general size formed very little, the reduction for grid parasitic capacitance is also more limited simultaneously; And its shape size is difficult to control, this will cause in sheet and discrete between sheet.
Therefore the process in the controlled medium cavity of a kind of large scale is sought, significant for the frequency characteristic improving the long device of the especially little grid of device.
Summary of the invention:
What the present invention proposed is a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor manufacture method, and object is to solve the above-mentioned defect existing for prior art.
For making the medium cavity of formation controlled, grow five layers of medium successively at semiconductor surface, be respectively fine and close-the finest and close-loose-the finest and close-fine and close dielectric layer from bottom to top, the medium that dielectric layer adopts includes but not limited to SiNx, SiO
xand SiON
xdeng.
When method etching (corrosion) medium utilizing dry method (wet method); because the medium of centre is comparatively loose; then automatically can form cavity; and its up and down two-layer finer and close dielectric layer also can protect the pattern of outermost dielectric layer; adjust the thickness of each layer medium simultaneously; also the medium hole of formation can be made more regular also more controlled; the final grid that fall both avoided when the grid not having medium support to cause are peeled off; also can reduce grid parasitic capacitance simultaneously, reach the object of the frequency characteristic of boost device.
Technical solution of the present invention: a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor manufacture method, comprises following processing step:
1) on substrate, adopt the method for MBE to form resilient coating, channel layer, barrier layer, low-doped GaAs layer and highly doped GaAs layer successively;
2) on highly doped GaAs layer, form two ohmic contact regions respectively as the source electrode of pseudomorphic high electron mobility transistor and drain electrode, and between two ohmic contact regions, utilize the method for dry etching or wet etching to remove highly doped GaAs layer to form a sipes;
3) the five layers of dielectric layer of the surface deposition between two Ohm contact electrodes, deposition process comprises plasma reinforced chemical vapor deposition, electron beam evaporation;
4) utilize dry etching or wet etching to form medium window and cavity, obtain by the thickness proportion of adjustment etch application or five layers of medium the medium cavity needing size;
5) with medium window for mask, utilize the low-doped GaAs layer at wet etching or dry etching window place, formed stria;
6) electron beam evaporation gate electrode metal can be selected;
7) on compound semiconductor epitaxial layer, two ohmic contact regions are formed respectively as the source electrode of transistor and drain electrode.
Advantage of the present invention: the Si-O layer inserting thin layer between the gate medium of three layers of densification-loose-densification, form five layers of dielectric structure, by adjustment dry method (wet method) etching (corrosion) condition, form the suitable lateral erosion degree of depth, the simultaneously also each thickness of dielectric layers ratio of adjustable, in order to control the height of lateral erosion, and then control the size forming medium cavity, wherein, the thickness of porous medium determines the longitudinal size in vacuum cavity, and the most compact medium in both sides plays the effect supporting and ensure vacuum cavity integrality.After grid evaporation is peeled off, the medium cavity that a size is controlled below the grid cover of T-shaped grid, can be formed, the reduction of grid parasitic capacitance and frequency characteristic be promoted and becomes controlled.
Accompanying drawing illustrates:
Fig. 1 is the schematic diagram of common GaAs pseudomorphic high electron mobility transistor;
Fig. 2 is the schematic diagram of the GaAs pseudomorphic high electron mobility transistor in the controllable vacuum medium cavity that the present invention proposes;
Fig. 3 is GaAs epitaxial structure schematic diagram;
Schematic diagram after the evaporation of Fig. 4 source and drain;
Fig. 5 grooving process chart;
Fig. 6 gate medium has grown rear schematic diagram;
Fig. 7 grid medium etching process chart;
Fig. 8 grid grooving process chart;
Fig. 9 grid evaporation technology flow chart;
Schematic diagram after Figure 10 grid metal-stripping.
Embodiment
A kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor manufacture method, comprises following processing step:
1) on substrate, adopt the method for MBE to form resilient coating, channel layer, barrier layer, low-doped GaAs layer and highly doped GaAs layer successively;
2) on highly doped GaAs layer, form two ohmic contact regions respectively as the source electrode of pseudomorphic high electron mobility transistor and drain electrode, and between two ohmic contact regions, utilize the method for dry etching or wet etching to remove highly doped GaAs layer to form a sipes;
3) the five layers of dielectric layer of the surface deposition between two Ohm contact electrodes, deposition process comprises plasma reinforced chemical vapor deposition, electron beam evaporation;
4) utilize dry etching or wet etching to form medium window and cavity, obtain by the thickness proportion of adjustment etch application or five layers of medium the medium cavity needing size;
5) with medium window for mask, utilize the low-doped GaAs layer at wet etching or dry etching window place, formed stria;
6) electron beam evaporation gate electrode metal can be selected;
7) on compound semiconductor epitaxial layer, two ohmic contact regions are formed respectively as the source electrode of transistor and drain electrode.
Described resilient coating adopts AlGaAs, and channel layer is growth InGaAs, and barrier layer is growth AlGaAs, barrier layer grows low-doped GaAs layer and highly doped GaAs layer.
5 layers of described dielectric layer, outermost is two-layer is compact medium layer, and middle is porous medium layer, and all the other are two-layer is most compact medium layer, and dielectric material comprises SiN
x, SiO
xand SiON
xdeng material, each layer thickness needs according to design and determines.
Described 5 layers of dielectric layer, have medium window from top to bottom, wherein, porous medium layer form vacuum cavity.In 5 layers of dielectric layer the thickness of each dielectric layer according to the actual requirements determine.
Described stria is positioned at sipes, and is in medium beneath window.
The medium cavity formed is positioned at below gate electrode metal, and grid peel off rear somatomedin passivation.
Technical scheme of the present invention is further described below in conjunction with accompanying drawing:
As shown in Figure 3, GaAs epitaxial material structure is from top to bottom roughly substrate and resilient coating, channel layer, barrier layer, low-doped GaAs layer and highly doped GaAs layer.
As shown in Figure 4, on the GaAs epitaxial material 306 shown in Fig. 3, the mode of electron beam evaporation is adopted to form Ohm contact electrode 407 and 408.
Ohm contact electrode can be that AuGeNi or any other can form the suitable material of ohmic contact with highly doped GaAs layer, and in nitrogen or any other suitable inert gas, by 400 of about 60s
oc high-temperature thermal annealing becomes ohmic contact.
As shown in 502 steps in Fig. 5, highly doped GaAs layer between source Ohm contact electrode and leakage Ohm contact electrode adopts the method for photoetching, form a photoresist window, then take the method for wet etching, copy photoetching offset plate figure, highly doped GaAs layer forms a sipes.
The bottom of sipes is the surface of low-doped GaAs layer, the distance of the width of sipes, distance both sides Ohm contact electrode, is decided according to the actual requirements, and depends on the precision that in manufacture, photoetching can reach, and the sipes degree of depth is the thickness of highly doped GaAs layer.
As shown in Figure 6, at highly doped GaAs layer and sipes surface deposition five layers of dielectric layer, its dielectric layer 601 and 605 generally suppresses the needs of surface state according to compound semiconductor and elects silicon nitride (SiN) as; Dielectric layer 603 is porous medium, can use but be not limited to silicon nitride (SiN), silica (SiO
2); Dielectric layer 602 and 604 can use but be not limited to silica (SiO
2), dielectric layer 601 and 605 of comparing is finer and close.The method of five layers of dielectric layer deposition comprises atomic layer deposition, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD), and preferred using plasma strengthens chemical vapor deposition technology.
Dielectric layer 605 between source Ohm contact electrode and leakage Ohm contact electrode adopts the method for photoetching, form a photoresist window, then utilize the method for dry etching to form a medium window, medium window width, residing position depend on different application purposes.
As shown in step 702 in Fig. 7, utilize dry method to the difference of different compactness extent dielectric etch speed, medium window place dielectric layer 603 forms certain side etching quantity automatically, is beneficial to the etch resistance of dielectric layer 602 and 604 simultaneously, make the lateral erosion shape of formation more regular.
As shown in Figure 8, recycling dielectric material is mask and adopts the method for wet etching or dry etching, corrodes low-doped GaAs layer and forms stria.The bottom of stria is the surface of fresh barrier layer, be conducive to the formation of following Schottky barrier, and its width depends on the width of medium window substantially, and method and the condition of concrete size and wet etching or dry etching are selected relevant.
As shown in the step 901 in Fig. 9, by medium window, gate electrode metal 902 is deposited on the surface of stria, and part metals is deposited on the edge of surface near medium window of dielectric layer 605, therefore gate electrode metal 902 defines the structure of T-shape.
Gate electrode metal can select all can form the metal system of Schottky contacts with compound semiconductor barrier layer, and the method for deposit can select electron beam evaporation.
As shown in Figure 10, can form the T-shape gate device with controlled regular shape medium cavity after grid metal-stripping and surface passivation, dielectric passivation can be selected to use Si
3n
4medium or Si
3n
4with SiO
2complex media carry out passivation.
The manufacture method of pseudomorphic high electron mobility transistor, adopt as any suitable growing methods such as MBE on substrate successively epitaxial growth obtain the resilient coating of device, channel layer, barrier layer, low-doped GaAs layer and highly doped GaAs layer.
Highly doped GaAs layer makes two ohmic contact regions respectively as source electrode and drain electrode, and highly doped GaAs layer between two electrodes adopts the method for dry etching or wet etching form sipes, the distance of sipes width and distance two electrodes depends on the purposes of made device, and the degree of depth of sipes depends on the thickness of highly doped GaAs layer.
After sipes completes, successively at source and drain Ohm contact electrode and sipes surface deposition five layers of medium, its material compactness extent is followed successively by generally/and fine and close/loose/fine and close/general, selectable dielectric material includes but not limited to silicon nitride (SiN), nitrogenize silicon/oxidative silicon (SiN/SiO
2) one in complex media, the method for dielectric deposition includes but not limited to atomic layer deposition, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD).On dielectric layer, within sipes, utilize the method for dry etching to form medium window afterwards, medium window width, residing position depend on different application purposes, recycling dielectric material is the method process barrier layer surface that mask adopts wet etching or dry etching, forms stria.Finally by electron beam evaporation gate electrode metal, within the scope of medium window adjacent edges, in deposit, gate electrode metal makes it to form T-type structure on barrier layer in medium window and above medium, completes the making of vacuum cavity grid structure pseudomorphic high electron mobility transistor.
Claims (7)
1. a vacuum cavity grid structure pseudomorphic high electron mobility transistor manufacture method, is characterized in that the method comprises following processing step:
1) on substrate, adopt the method for MBE to form resilient coating, channel layer, barrier layer, low-doped GaAs layer and highly doped GaAs layer successively;
2) on highly doped GaAs layer, form two ohmic contact regions respectively as the source electrode of pseudomorphic high electron mobility transistor and drain electrode, and between two ohmic contact regions, utilize the method for dry etching or wet etching to remove highly doped GaAs layer to form a sipes;
3) the five layers of dielectric layer of the surface deposition between two Ohm contact electrodes, deposition process comprises plasma reinforced chemical vapor deposition, electron beam evaporation;
4) utilize dry etching or wet etching to form medium window and cavity, obtain by the thickness proportion of adjustment etch application or five layers of medium the medium cavity needing size;
5) with medium window for mask, utilize the low-doped GaAs layer at wet etching or dry etching window place, formed stria;
6) electron beam evaporation gate electrode metal can be selected;
7) on compound semiconductor epitaxial layer, two ohmic contact regions are formed respectively as the source electrode of transistor and drain electrode.
2. a kind of vacuum cavity according to claim 1 grid structure pseudomorphic high electron mobility transistor manufacture method, it is characterized in that described resilient coating adopts AlGaAs, channel layer is growth InGaAs, and barrier layer is growth AlGaAs, barrier layer grows low-doped GaAs layer and highly doped GaAs layer.
3. a kind of vacuum cavity according to claim 1 grid structure pseudomorphic high electron mobility transistor manufacture method, it is characterized in that 5 layers of described dielectric layer, outermost is two-layer is compact medium layer, and middle is porous medium layer, all the other are two-layer is most compact medium layer, and dielectric material comprises SiN
x, SiO
xand SiON
xdeng material, each layer thickness needs according to design and determines.
4. a kind of vacuum cavity according to claim 3 grid structure pseudomorphic high electron mobility transistor manufacture method, is characterized in that 5 layers of dielectric layer, has medium window from top to bottom, wherein, porous medium layer forms vacuum cavity.
5. a kind of vacuum cavity according to claim 4 grid structure pseudomorphic high electron mobility transistor manufacture method, in 5 layers of dielectric layer the thickness of each dielectric layer according to the actual requirements determine.
6. a kind of vacuum cavity according to claim 1 grid structure pseudomorphic high electron mobility transistor manufacture method, is characterized in that stria is positioned at sipes, and is in medium beneath window.
7. a kind of vacuum cavity according to claim 1 grid structure pseudomorphic high electron mobility transistor manufacture method, it is characterized in that the medium cavity formed is positioned at below gate electrode metal, grid peel off rear somatomedin passivation.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707150A (en) * | 2019-11-13 | 2020-01-17 | 中国电子科技集团公司第十三研究所 | double-T-shaped nano gate and preparation method thereof |
| CN110808207A (en) * | 2019-11-13 | 2020-02-18 | 中国电子科技集团公司第十三研究所 | T-shaped nano gate and preparation method thereof |
| CN114144891A (en) * | 2021-07-16 | 2022-03-04 | 英诺赛科(苏州)科技有限公司 | Nitrogen-based semiconductor device and method for manufacturing the same |
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| CN102280476A (en) * | 2011-08-08 | 2011-12-14 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacturing method thereof |
| CN103887335A (en) * | 2014-02-25 | 2014-06-25 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacture method for improving frequency characteristic |
-
2015
- 2015-12-04 CN CN201510878221.3A patent/CN105448713B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0927505A (en) * | 1995-07-13 | 1997-01-28 | Nippondenso Co Ltd | Semiconductor device and manufacturing method therefor |
| JP2000223504A (en) * | 1999-02-03 | 2000-08-11 | Sanyo Electric Co Ltd | Field-effect semiconductor device and its manufacture |
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| CN103887335A (en) * | 2014-02-25 | 2014-06-25 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacture method for improving frequency characteristic |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110707150A (en) * | 2019-11-13 | 2020-01-17 | 中国电子科技集团公司第十三研究所 | double-T-shaped nano gate and preparation method thereof |
| CN110808207A (en) * | 2019-11-13 | 2020-02-18 | 中国电子科技集团公司第十三研究所 | T-shaped nano gate and preparation method thereof |
| CN110808207B (en) * | 2019-11-13 | 2023-09-26 | 中国电子科技集团公司第十三研究所 | T-shaped nano gate and preparation method thereof |
| CN114144891A (en) * | 2021-07-16 | 2022-03-04 | 英诺赛科(苏州)科技有限公司 | Nitrogen-based semiconductor device and method for manufacturing the same |
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| CN105448713B (en) | 2018-02-27 |
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