CN110707150A - double-T-shaped nano gate and preparation method thereof - Google Patents
double-T-shaped nano gate and preparation method thereof Download PDFInfo
- Publication number
- CN110707150A CN110707150A CN201911107664.7A CN201911107664A CN110707150A CN 110707150 A CN110707150 A CN 110707150A CN 201911107664 A CN201911107664 A CN 201911107664A CN 110707150 A CN110707150 A CN 110707150A
- Authority
- CN
- China
- Prior art keywords
- gate
- layer
- double
- passivation layer
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000002161 passivation Methods 0.000 claims abstract description 44
- 239000000758 substrate Substances 0.000 claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 74
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 49
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 48
- 229920002120 photoresistant polymer Polymers 0.000 claims description 45
- 238000010894 electron beam technology Methods 0.000 claims description 39
- 239000000377 silicon dioxide Substances 0.000 claims description 38
- 235000012239 silicon dioxide Nutrition 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 20
- 230000007797 corrosion Effects 0.000 claims description 17
- 238000005260 corrosion Methods 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 238000001259 photo etching Methods 0.000 claims description 10
- 150000003377 silicon compounds Chemical class 0.000 claims description 9
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 7
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 5
- 238000001704 evaporation Methods 0.000 claims description 4
- 230000003071 parasitic effect Effects 0.000 abstract description 11
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 12
- 239000004926 polymethyl methacrylate Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 229910002601 GaN Inorganic materials 0.000 description 9
- PGMYKACGEOXYJE-UHFFFAOYSA-N pentyl acetate Chemical compound CCCCCOC(C)=O PGMYKACGEOXYJE-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 229910002704 AlGaN Inorganic materials 0.000 description 4
- 229910017083 AlN Inorganic materials 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 238000001035 drying Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- NTIZESTWPVYFNL-UHFFFAOYSA-N Methyl isobutyl ketone Chemical compound CC(C)CC(C)=O NTIZESTWPVYFNL-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 229910021389 graphene Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 229910052982 molybdenum disulfide Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- FRIKWZARTBPWBN-UHFFFAOYSA-N [Si].O=[Si]=O Chemical compound [Si].O=[Si]=O FRIKWZARTBPWBN-UHFFFAOYSA-N 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28581—Deposition of Schottky electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
- H01L21/28587—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds characterised by the sectional shape, e.g. T, inverted T
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention relates to the technical field of microelectronic devices, and particularly discloses a double-T-shaped nano gate and a preparation method thereof. The double T-shaped nano gate is grown on a substrate with a medium passivation layer, and the medium passivation layer comprises a bottom medium passivation layer and a top medium passivation layer; the double-T-shaped nano grid sequentially comprises a grid root, a grid waist and a grid cap from bottom to top; the gate roots penetrate through the dielectric passivation layer to grow on the substrate, the gate roots are not in contact with the bottom dielectric passivation layer, and the lower surface of the gate waist is in contact with the upper surface of the top dielectric passivation layer. The double-T-shaped nano gate root and the gate cap are suspended and do not contact with the dielectric passivation layer, the gate waist covers the top dielectric passivation layer, the stability of the double-T-shaped gate is improved, the distance between the gate cap and the dielectric passivation layer is increased due to the double-T-shaped structure, parasitic capacitance is further reduced, inverted gate stripping caused by no dielectric support is avoided, and the purpose of improving the frequency characteristic of a device is achieved.
Description
Technical Field
The invention relates to the technical field of microelectronic devices, in particular to a double-T-shaped nano gate and a preparation method thereof.
Background
The performance of a High Electron Mobility Transistor (HEMT) device is closely related to the processing technology of the device, and especially the fabrication of the gate line plays a decisive role in the device. The smaller the gate length, the current cutoff frequency (f) of the deviceT) The higher the noise figure of the device, the smaller the noise figure of the device, and the more excellent the device can be obtained by continuously reducing the gate length of the HEMT device. At present, the gate length of advanced GaAs, InP and GaN devices at home and abroad is reduced to the level within 100nm, but as the gate length is shortened, the gate resistance is increased, and the increase of the gate resistance becomes one of important factors for restricting the performance improvement of small-size devices. In order to solve the problem of gate resistance increase, a metal section with a larger size is usually made on top of the gate metal to form a T-shaped gate. The T-shaped gate can effectively reduce the gate length and the gate resistance, and is a core process for improving the working frequency and the working voltage of the transistor.
Because the T-shaped grid is a structure with a wide top and a narrow bottom, the bearing capacity of the grid root is gradually reduced along with the further reduction of the length of the T-shaped grid, and the T-shaped grid is easy to topple. In order to ensure the stability of the T-shaped gate, a dielectric is generally used as a mask, i.e., a layer of silicon nitride is deposited on a substrate, and then gate metal is etched and evaporated to obtain the T-shaped gate. The T-shaped gate with the medium auxiliary support is stable in machinery, and the T-shaped gate is not easy to collapse. However, the introduction of the dielectric increases the parasitic capacitance between the gate and the source and also impairs the high-frequency performance.
Disclosure of Invention
Aiming at the problem that the parasitic capacitance of the dielectric auxiliary T-shaped nano gate prepared by the prior art is higher, the invention provides a double T-shaped nano gate and a preparation method thereof.
In order to solve the technical problems, the invention provides a double-T-shaped nano gate;
and a preparation method of the double T-shaped nano gate.
A first aspect of an embodiment of the present invention provides a double-T-shaped nano gate, which is grown on a substrate having a double-layer dielectric passivation layer, where the double-layer dielectric passivation layer includes a bottom dielectric passivation layer directly grown on an upper surface of the substrate, and a top dielectric passivation layer grown on the bottom dielectric passivation layer. The double-T-shaped nano grid sequentially comprises a grid root, a grid waist and a grid cap from bottom to top; the width of the grid cap is greater than that of the grid waist, and the width of the grid waist is greater than that of the grid root; the grid waist and the grid root form a first-stage T-shaped grid, the grid waist and the grid cap form a second-stage T-shaped grid, the grid root penetrates through the dielectric passivation layer to grow on the substrate, the grid foot is not in contact with the bottom dielectric passivation layer, and the lower surface of the grid waist is in contact with the upper surface of the top dielectric passivation layer.
Optionally, the bottom dielectric passivation layer is a silicon dioxide layer, and the top dielectric passivation layer is a silicon nitride layer.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the double-T-shaped gate provided by the invention grows on the substrate with the double-layer medium passivation layer, the gate root and the gate cap are suspended and are not contacted with the medium passivation layer, and the gate resistance and the parasitic capacitance can be effectively reduced; the gate waist covers the top dielectric passivation layer, stability of the double-T-shaped gate is improved, and the distance between the gate cap and the dielectric passivation layer is increased due to the double-T-shaped structure, so that parasitic capacitance can be further reduced. Therefore, the double-T-shaped gate provided by the invention not only avoids inverted gate caused by no medium support when the gate is stripped, but also can obviously reduce the parasitic capacitance of the gate, and achieves the purpose of improving the frequency characteristic of a device.
The second aspect of the embodiments of the present invention provides a method for preparing a double-T-shaped nano gate, including the following steps:
a, growing a silicon dioxide layer and a silicon nitride layer on the upper surface of a substrate from bottom to top in sequence;
b, coating an electron beam photoresist layer on the silicon nitride layer, and exposing and developing to obtain a photoetching pattern;
step c, etching the silicon nitride layer below the window of the photoetching pattern until the silicon dioxide layer is exposed to form a strip-shaped gate groove;
d, corroding the silicon dioxide layer and the silicon nitride layer which form the strip-shaped gate groove by using corrosive liquid of a silicon compound to obtain a gate root window; wherein the ratio of the corrosion rate of the corrosion liquid of the silicon compound to the corrosion rate of the silicon dioxide and the silicon nitride is larger than a preset value;
e, removing the electron beam photoresist layer to expose the silicon nitride layer;
step f, coating 2-3 layers of electron beam photoresist on the substrate with the exposed silicon nitride layer, exposing and developing to obtain a gate electrode window; wherein, the window width of the upper layer photoresist in the gate electrode window is larger than that of the lower layer photoresist
And g, evaporating and stripping the gate metal to obtain the double-T-shaped nano gate.
Optionally, the thickness of the silicon dioxide layer is 20-200 nm.
Optionally, the thickness of the silicon nitride layer is 20-100 nm.
Optionally, in step b, the thickness of the electron beam resist layer is 50-300 nm.
Optionally, the total thickness of the silicon dioxide layer and the silicon nitride layer is equal to the gate root height of the preset double-T-shaped nano gate.
Optionally, the thickness of the silicon nitride layer is not greater than 1/2 of the gate root height of the preset double-T-shaped nano gate.
Optionally, in the step f, the total thickness of the electron beam photoresist is not less than 1.5 times of the total height of the preset double-T-shaped nano gate.
Optionally, in step f, the thickness of the bottom layer electron beam photoresist in direct contact with the silicon nitride layer is equal to the gate waist height of the preset double-T-shaped nano gate.
Optionally, in the step d, the preset value is 3: 1.
Optionally, in step c, after the etching is stopped, the remaining thickness of the silicon dioxide layer is 10-15 nm.
Optionally, in step b, the electron beam resist is PMMA or ZEP 520.
Optionally, in step b, when the electron beam photoresist is ZEP520, the exposure dose is 100-2。
Optionally, in step b, when the electron beam resist is PMMA, the exposure dose is 400-2。
OptionallyWhen the substrate is an epitaxial wafer, the epitaxial wafer is made of doped Si, doped SiC, diamond, Ga2O3GaAs, InP, GaN, AlN, graphene, MOS2AlGaN/GaN, InAlN/GaN, AlN/GaN, AlGaN/GaAs, or InGaAs/InP.
Optionally, the gate metal is a metal composition capable of forming a schottky contact with a semiconductor.
Optionally, the gate metal is Ni/Au, Ti/Pt/Au or Ti/Au.
Optionally, the silicon dioxide layer and the silicon nitride layer are prepared by PECVD, LPCVD or ALD techniques.
Optionally, in the step e, the electron beam photoresist is a double-layer photoresist such as PMMA/PMMA-MAA or ZEP/PMGI, or a triple-layer photoresist such as PMMA/PMMA-MAA/PMMA or ZEP/PMGI/ZEP.
Adopt the produced beneficial effect of above-mentioned technical scheme to lie in: the preparation method of the double-T-shaped nano gate provided by the invention has the advantages that the silicon dioxide-silicon nitride double-layer medium structure grows on the substrate, and the corrosion rate of SiN in the wet corrosion process is far lower than that of SiO2Forming proper lateral etching depth and height by controlling wet etching conditions so as to obtain a gate root with a smaller size and a dielectric cavity with a larger size in the following; and then, a gate waist and a gate cap window are prepared by an electron beam exposure process, after gate evaporation stripping, a gate cap and a gate root are formed and suspended, and the gate waist covers a double-T-shaped gate structure on a silicon nitride dielectric passivation layer, so that the problem of gate inversion easily caused by T-shaped gate stripping is solved, the gate parasitic capacitance is effectively reduced, and the frequency characteristic of the device is obviously improved.
The preparation method provided by the invention adopts a method combining processes such as electron beam exposure, wet etching, dry etching and the like, prepares the double-T-shaped gate with the suspended gate cap and gate root by controlling the structure of the dielectric layer and reasonably setting the exposure dose and the wet etching time of the photoetching pattern, obviously reduces the parasitic capacitance of the device, has simple and easy process, improves the mechanical strength and the yield of the device, and reduces the production cost.
Drawings
FIG. 1 is a schematic structural diagram of a device fabricated in an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of the device processed in step 1 according to the embodiment of the present invention;
FIG. 3 is a schematic structural diagram of the device processed in step 2 according to the embodiment of the present invention;
FIG. 4 is a schematic structural diagram of the device processed in step 3 according to the embodiment of the present invention;
FIG. 5 is a schematic structural diagram of the device processed in step 4 according to the embodiment of the present invention;
FIG. 6 is a schematic structural diagram of the device processed in step 5 according to the embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a device processed in step 6 according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a device processed in step 7 according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a device processed in step 8 according to an embodiment of the present invention;
FIG. 10 is a schematic structural diagram of a device processed in step 9 according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of a device processed in step 10 according to an embodiment of the present invention;
101, a semiconductor wafer; 102. a silicon dioxide layer; 103. a silicon nitride layer; 104. electron beam resist; 105. photoetching a pattern window; 106. a strip-shaped grid groove; 107. a grid root window; 108. bottom electron beam photoresist; 109. top electron beam photoresist; 110. a gate electrode window; 111. a metal sample; 112. double T-shaped nano gates; 11121. a gate cap; 1122. a grid waist; 1123 grid root.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
In one embodiment, referring to fig. 1, the embodiment of the present invention provides a double-T-shaped nano-gate 112, including a gate cap 1121, a gate waist 1122 and a gate root 1123, wherein the width of the gate cap 1121 is greater than the width of the gate waist 1122, and the width of the gate waist 1122 is greater than the width of the gate root 1123. The double-T-shaped nanometer gate 112 is grown on the substrate 101, and the bottom dielectric passivation layer 102 and the top dielectric passivation layer 103 are sequentially grown on the upper surface of the substrate 101 from bottom to top. The gate root 1123 grows on the substrate 101 through the top dielectric passivation layer 103, the gate root 1123 is suspended, i.e., does not contact the bottom dielectric passivation layer 102, and the gate waist 1122 covers the upper surface of the top dielectric passivation layer 103. The top dielectric passivation layer 103 acts as a support for the gate waist 1122, thereby increasing the stability of the double T-gate 112 and preventing gate inversion. The gate root 1123 is suspended, and the parasitic capacitance of the device is obviously reduced.
Optionally, the bottom dielectric passivation layer 102 is a silicon dioxide layer, and the top dielectric passivation layer 103 is a silicon dioxide layer.
Referring to fig. 2 to 10, an embodiment of the invention provides a method for manufacturing a dual T-shaped nano gate, including the following steps:
step 1, referring to fig. 2, growing a silicon dioxide layer 102 and a silicon nitride layer 103 on the upper surface of a semiconductor wafer 101 with a complete growth structure in sequence from bottom to top;
step 2, referring to fig. 3, coating electron beam photoresist 104 on the silicon nitride layer 103;
step 3, referring to fig. 4, exposing the electron beam lithography 104 according to the designed gate root width and exposure dose, and developing the exposed photoresist to obtain a lithography pattern window 105;
step 4, referring to fig. 5, etching the silicon nitride layer 103 below the photo-etching pattern window 105 until the silicon dioxide layer 102 is exposed, and forming a strip-shaped gate groove 106;
step 5, referring to fig. 6, etching the silicon dioxide layer 102 and the silicon nitride layer 103 with the strip-shaped gate trench 106 formed therein by using a silicon compound etching solution to obtain a gate root window 107; wherein the ratio of the corrosion rate of the corrosion liquid of the silicon compound to the corrosion rate of the silicon dioxide and the silicon nitride is larger than a preset value;
step 6, referring to fig. 7, removing the electron beam photoresist on the surface of the silicon nitride layer 103 to expose the silicon nitride layer 103;
step 7, referring to fig. 8, sequentially coating a bottom layer electron beam photoresist 108 and a top layer electron beam photoresist 109 on the substrate with the exposed silicon nitride layer 103 from top to bottom;
step 8, referring to fig. 9, exposing and developing the bottom layer electron beam photoresist 108 and the top layer electron beam photoresist 109 to obtain a gate electrode window 110; wherein, the window width of the gate electrode window top layer photoresist 109 is larger than the window width of the bottom layer photoresist 108;
step 9, referring to fig. 10, evaporating the gate electrode material to the gate electrode window 110 by using an electron beam evaporation process to obtain an evaporated metal sample 111;
step 10, referring to fig. 11, the evaporated metal sample 111 is stripped by using a general stripping technique, and the residual electron beam photoresist is removed, so as to obtain the double-T-shaped nano gate 112.
The material of the semiconductor wafer 101 in this embodiment can be doped Si, doped SiC, diamond, Ga2O3GaAs, InP, GaN, AlN, graphene or MOS2The common semiconductor material may be a HEMT structure material such as AlGaN/GaN, InAlN/GaN, AlN/GaN, AlGaN/GaAs, or InGaAs/InP, but is not limited thereto.
In this embodiment, in step 2, the e-beam photoresist may be an etching-resistant e-beam photoresist conventional in the art, such as PMMA series or ZEP520 series, without limitation.
In this embodiment, in step 9, the gate metal is a metal composition capable of forming a schottky contact with the semiconductor, such as Ni/Au, Ti/Pt/Au, Ti/Au, etc., which is not limited herein.
In one embodiment, in step 2, E-beam resist 104 has a thickness of 50-300 nm. The thickness of the electron beam resist 104 may be selected according to the predetermined thickness of the actual gate root.
In one embodiment, the electron beam resist is spin-coated at 3000-.
In one embodiment, the electron beam resist 104 is ZEP-520 with an exposure dose of 100-2The beam current is less than or equal to 2 nA. And developing for 2-5min by adopting n-amyl acetate after exposure, then fixing for 1-2min by adopting IPA, and drying by using nitrogen to obtain a photoetching pattern.
In another embodiment, the electron beam resist 104 is C4 or A4 of PMMA series, and the exposure dose is 400-2The beam current is less than or equal to 2 nA. After exposure, developing for 2-5min by using a developing solution (MIBK: IPA 1:3), then fixing for 1-2min by using IPA, and drying by using nitrogen to obtain a photoetching pattern.
In one embodiment, the silicon dioxide layer 102 has a thickness of 20-200 nm.
In one embodiment, the silicon nitride layer 103 has a thickness of 20-100 nm.
In one embodiment, the total thickness of the silicon dioxide layer 102 and the silicon nitride layer 103 is selected to be equal to the predetermined thickness of the gate root of the double-T-shaped nano-gate.
In one embodiment, the thickness of the silicon nitride layer 103 is not greater than 1/2 for the gate root height of the pre-defined double-T nano-gate.
The thickness of the silicon nitride layer 103 is set to be not more than 1/2 of the height of the gate root of the preset double-T-shaped nano gate, so that a vacuum dielectric cavity with larger size can be formed at the position of the gate root, and the parasitic capacitance of the gate is obviously reduced.
In one embodiment, the ratio of the etching rate of the etching solution of the silicon compound to the etching rate of silicon dioxide and silicon nitride is greater than 3: 1.
The ratio of the corrosion rate of the corrosive liquid of the silicon compound to the corrosion rate of the silicon dioxide and the silicon nitride is more than 3:1, so that a double-T-shaped gate with a dielectric cavity at the bottom of a gate root is conveniently formed.
In one embodiment, the silicon compound etching solution is a BOE etching solution.
And 5, selecting the etching time according to the ratio of the BOE to the etching rates of the silicon nitride and the silicon dioxide and the width of the preset vacuum medium hole. The corrosion rate according to SiN is much lower than that of SiO2Smaller grid roots are easier to obtain, and vacuum holes with larger sizes are obtained. The gate waist of the prepared double-T-shaped gate directly covers the SiN layer, the T-shaped gate is fixed, the problem of gate inversion is solved, the double-T-shaped gate is suspended, the double-T-shaped gate is not directly contacted with a passivation medium, the resistance of the gate is reduced, and meanwhile, the metal contact area of the medium passivation layer and the double-T-shaped gate is reduced, so that parasitic capacitance is effectively inhibited.
The experimental data show that for silicon nitride and silicon dioxide grown according to the conventional process, the corrosion rate of BOE to silicon dioxide is 500-600nm/min, and the corrosion rate to silicon nitride is 50-60nm/min, so the ratio of the corrosion rates to silicon dioxide and silicon nitride is about 10: 1. The preset value of the etching rate is 10, so that the etching time can be shortened, and a double-T-shaped gate with smaller size can be obtained.
In one embodiment, in step 4, the silicon nitride layer 103 under the lithography pattern window 105 is etched by RIE dry etching process until the silicon dioxide layer 102 is exposed.
In one embodiment, in step 4, after the etching is stopped, the remaining thickness of the silicon dioxide layer 102 is 10-15 nm.
Part of the silicon dioxide layer 102 is left after the RIE etching is finished, so that damage to the substrate can be avoided.
In one embodiment, the silicon dioxide layer 102 and the silicon nitride layer 103 may be obtained by PECVD, LPCVD, and ALD techniques.
In one embodiment, in step 7, the total thickness of the bottom layer e-beam photoresist 108 and the top layer e-beam photoresist 109 is not less than 1.5 times the total height of the predetermined double-T-shaped nano-gate.
And (4) setting the total thickness of the electron beam photoresist in the step (7) to be 1.5 times of the total height of the double-T-shaped nano gate, so that the electron beam photoresist can be stripped and removed conveniently in the later period.
In one embodiment, in step 7, the thickness of the bottom layer e-beam photoresist 108 is equal to the gate waist height of the preset double-T-shaped nano-gate.
In one embodiment, in step 7, the bottom e-beam resist 108 may be PMMA or ZEP, and the top e-beam resist 109 may be PMMA-MAA or PMGI.
In another embodiment, in step 7, the electron beam resist may be a three-layer resist, such as PMMA/PMMA-MAA/PMMA or ZEP/PMGI/ZEP.
During coating, the thickness of PMMA and ZEP is 50-300nm, the thickness of PMMA-MAA and PMGI is 200-800nm, and the total thickness of the final three-layer glue and the double-layer glue is not less than 1.5 times of the total height of the preset double-T-shaped gate.
In an embodiment, in step 7, when three layers of photoresist are coated, the window width of the middle and upper layers of photoresist is required to be greater than the window width of the lower layer of photoresist, specifically, the window width of the bottom layer of electron beam photoresist is the smallest, then the top layer of electron beam photoresist, and the window width of the middle layer of electron beam photoresist is the largest.
In step 7, during the electron beam exposure and development, the exposure dose is determined according to the selected combination of the photoresist and the widths of the gate waist and the gate cap of the preset double-T-shaped gate.
The exposure dose of PMMA/PMMA-MAA and PMMA/PMMA-MAA/PMMA is 400-2And the beam current is less than or equal to 2nA, developing for 2-5min by using a developing solution (MIBK: IPA 1:3) after exposure, then fixing for 1-2min by using IPA, and drying by using nitrogen gas to obtain a photoetching pattern. The exposure dose of ZEP/PMGI and ZEP/PMGI/ZEP was 150-2The beam current is less than or equal to 2 nA. After exposure, ZEP/PMGI required two development, PMGI required TMAH development and ZEP required n-amyl acetate development. ZEP/PMGI/ZEP required three development passes, developing ZEP with n-amyl acetate, then PMGI with TMAH, and finally developing ZEP with n-amyl acetate.
In one embodiment, the wafer is stripped and stripped by a stripping liquid such as acetone or NMP.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents or improvements made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A double T-shaped nanometer gate is grown on a substrate with a medium passivation layer, and is characterized in that the medium passivation layer comprises a bottom medium passivation layer and a top medium passivation layer; the double-T-shaped nano grid sequentially comprises a grid root, a grid waist and a grid cap from bottom to top, wherein the width of the grid cap is greater than that of the grid waist, and the width of the grid waist is greater than that of the grid root; the gate roots penetrate through the dielectric passivation layer to grow on the substrate, the gate roots are not in contact with the bottom dielectric passivation layer, and the lower surface of the gate waist is in contact with the upper surface of the top dielectric passivation layer.
2. The double-T-shaped nano-gate of claim 1, wherein the bottom dielectric passivation layer is a silicon dioxide layer and the top dielectric passivation layer is a silicon nitride layer.
3. The method for preparing a double-T-shaped nano gate as claimed in claim 1 or 2, which is characterized by comprising the following steps:
a, growing a silicon dioxide layer and a silicon nitride layer on the upper surface of a substrate from bottom to top in sequence;
b, coating an electron beam photoresist layer on the silicon nitride layer, and exposing and developing to obtain a photoetching pattern;
step c, etching the silicon nitride layer below the window of the photoetching pattern until the silicon dioxide layer is exposed to form a strip-shaped gate groove;
d, corroding the silicon dioxide layer and the silicon nitride layer which form the strip-shaped gate groove by using corrosive liquid of a silicon compound to obtain a gate root window; wherein the ratio of the corrosion rate of the corrosion liquid of the silicon compound to the corrosion rate of the silicon dioxide and the silicon nitride is larger than a preset value;
e, removing the electron beam photoresist layer to expose the silicon nitride layer;
f, coating 2-3 layers of electron beam photoresist on the substrate with the silicon nitride layer exposed, exposing and developing to obtain a gate electrode window, wherein the window width of the upper layer photoresist in the gate electrode window is larger than that of the lower layer photoresist;
and g, evaporating and stripping the gate metal to obtain the double-T-shaped nano gate.
4. The method of claim 3, wherein the silicon dioxide layer has a thickness of 20-200 nm; or the thickness of the silicon nitride layer is 20-100 nm; or in the step b, the thickness of the electron beam photoresist layer is 50-300 nm.
5. The method of claim 3, wherein the total thickness of the silicon dioxide layer and the silicon nitride layer is equal to a predetermined height of a gate root of the double-T-shaped nano gate.
6. The method of claim 3, wherein the thickness of the silicon nitride layer is not greater than 1/2 for the gate root height of the double-T nano gate.
7. The method of claim 3, wherein in step f, the total thickness of the electron beam photoresist is not less than 1.5 times the total height of the predetermined double-T-shaped nano gate.
8. The method according to claim 7, wherein in step f, the thickness of the bottom electron beam photoresist in direct contact with the silicon nitride layer is equal to the gate waist height of the preset double-T-shaped nano gate.
9. The method of claim 3, wherein in step d, the predetermined value is 3: 1.
10. The method according to claim 3, wherein in step c, the remaining thickness of the silicon dioxide layer is 10-15nm after the etching is stopped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911107664.7A CN110707150B (en) | 2019-11-13 | 2019-11-13 | double-T-shaped nano gate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911107664.7A CN110707150B (en) | 2019-11-13 | 2019-11-13 | double-T-shaped nano gate and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110707150A true CN110707150A (en) | 2020-01-17 |
| CN110707150B CN110707150B (en) | 2023-06-27 |
Family
ID=69205942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911107664.7A Active CN110707150B (en) | 2019-11-13 | 2019-11-13 | double-T-shaped nano gate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110707150B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713185A (en) * | 2020-12-21 | 2021-04-27 | 西安电子科技大学 | T-shaped gate with supporting structure, preparation method thereof and semiconductor power device |
| CN113690132A (en) * | 2021-07-30 | 2021-11-23 | 华南理工大学 | double-T-shaped gate preparation method based on double-layer passivation precise etching |
| CN114813851A (en) * | 2021-01-22 | 2022-07-29 | 西湖大学 | Volatile organic pollutant detector and preparation method thereof |
Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175243A (en) * | 1991-12-26 | 1993-07-13 | Toshiba Corp | Manufacture of semiconductor device |
| CN1374687A (en) * | 2001-03-13 | 2002-10-16 | 中国科学院微电子中心 | Manufacture of high electron mobility transistor capable of obtaining grid |
| US20030119233A1 (en) * | 2001-12-20 | 2003-06-26 | Nec Compound Semiconductor Devices, Ltd. | Method of fabricating semiconductor device with T-type gate electrode |
| US20070099368A1 (en) * | 2005-11-03 | 2007-05-03 | Ahn Ho K | Field effect transistor and method for manufacturing the same |
| US20080124852A1 (en) * | 2005-11-29 | 2008-05-29 | Electronics And Telecommunications Research Institute | Method of forming T- or gamma-shaped electrode |
| US20090146184A1 (en) * | 2007-12-05 | 2009-06-11 | Electronics And Telecommunications Research Institute | Semiconductor device with t-gate electrode and method for fabricating the same |
| WO2010151736A1 (en) * | 2009-06-25 | 2010-12-29 | The University Of North Carolina At Chapel Hill | Chimeric factor vii molecules |
| CN102280476A (en) * | 2011-08-08 | 2011-12-14 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacturing method thereof |
| CN102437182A (en) * | 2011-12-01 | 2012-05-02 | 中国科学院半导体研究所 | SiO2/SiN double layer passivation layer T-typed grid AlGaN/GaN HEMT and manufacturing method thereof |
| JP2013219301A (en) * | 2012-04-12 | 2013-10-24 | Nippon Telegr & Teleph Corp <Ntt> | Electrode formation method |
| US20130341678A1 (en) * | 2012-06-26 | 2013-12-26 | Freescale Semiconductor, Inc. | Semiconductor Device with Selectively Etched Surface Passivation |
| US20140017885A1 (en) * | 2012-07-11 | 2014-01-16 | Electronics And Telecommunications Research Institute | Method of manufacturing field effect type compound semiconductor device |
| CN105118774A (en) * | 2015-07-22 | 2015-12-02 | 中国电子科技集团公司第十三研究所 | Method for making nano T-shaped gate |
| US20150364567A1 (en) * | 2013-05-21 | 2015-12-17 | The 13Th Research Institute Of China Electronics Technology Group Corporation | Method for manufacturing graphene transistor based on self-aligning technology |
| CN105448713A (en) * | 2015-12-04 | 2016-03-30 | 中国电子科技集团公司第五十五研究所 | Manufacturing method of vacuum cavity gate structure pseudomorphic high electron mobility transistor |
| CN105789037A (en) * | 2016-03-18 | 2016-07-20 | 中国电子科技集团公司第五十五研究所 | Preparation method for small-sized gate of microwave millimeter wave chip |
| CN105977147A (en) * | 2016-07-29 | 2016-09-28 | 中国电子科技集团公司第十三研究所 | Damage-free automatic-terminating etching method for nano-gate preparation |
| CN109103245A (en) * | 2018-07-26 | 2018-12-28 | 厦门市三安集成电路有限公司 | A kind of double-T shaped grid and production method and application |
| CN109461655A (en) * | 2018-09-21 | 2019-03-12 | 中国电子科技集团公司第五十五研究所 | Nitride high electronic migration rate transistor fabrication process with multi-gate structure |
-
2019
- 2019-11-13 CN CN201911107664.7A patent/CN110707150B/en active Active
Patent Citations (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05175243A (en) * | 1991-12-26 | 1993-07-13 | Toshiba Corp | Manufacture of semiconductor device |
| CN1374687A (en) * | 2001-03-13 | 2002-10-16 | 中国科学院微电子中心 | Manufacture of high electron mobility transistor capable of obtaining grid |
| US20030119233A1 (en) * | 2001-12-20 | 2003-06-26 | Nec Compound Semiconductor Devices, Ltd. | Method of fabricating semiconductor device with T-type gate electrode |
| US20070099368A1 (en) * | 2005-11-03 | 2007-05-03 | Ahn Ho K | Field effect transistor and method for manufacturing the same |
| US20080124852A1 (en) * | 2005-11-29 | 2008-05-29 | Electronics And Telecommunications Research Institute | Method of forming T- or gamma-shaped electrode |
| US20090146184A1 (en) * | 2007-12-05 | 2009-06-11 | Electronics And Telecommunications Research Institute | Semiconductor device with t-gate electrode and method for fabricating the same |
| WO2010151736A1 (en) * | 2009-06-25 | 2010-12-29 | The University Of North Carolina At Chapel Hill | Chimeric factor vii molecules |
| CN102280476A (en) * | 2011-08-08 | 2011-12-14 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacturing method thereof |
| CN102437182A (en) * | 2011-12-01 | 2012-05-02 | 中国科学院半导体研究所 | SiO2/SiN double layer passivation layer T-typed grid AlGaN/GaN HEMT and manufacturing method thereof |
| JP2013219301A (en) * | 2012-04-12 | 2013-10-24 | Nippon Telegr & Teleph Corp <Ntt> | Electrode formation method |
| US20130341678A1 (en) * | 2012-06-26 | 2013-12-26 | Freescale Semiconductor, Inc. | Semiconductor Device with Selectively Etched Surface Passivation |
| US20140017885A1 (en) * | 2012-07-11 | 2014-01-16 | Electronics And Telecommunications Research Institute | Method of manufacturing field effect type compound semiconductor device |
| US20150364567A1 (en) * | 2013-05-21 | 2015-12-17 | The 13Th Research Institute Of China Electronics Technology Group Corporation | Method for manufacturing graphene transistor based on self-aligning technology |
| CN105118774A (en) * | 2015-07-22 | 2015-12-02 | 中国电子科技集团公司第十三研究所 | Method for making nano T-shaped gate |
| CN105448713A (en) * | 2015-12-04 | 2016-03-30 | 中国电子科技集团公司第五十五研究所 | Manufacturing method of vacuum cavity gate structure pseudomorphic high electron mobility transistor |
| CN105789037A (en) * | 2016-03-18 | 2016-07-20 | 中国电子科技集团公司第五十五研究所 | Preparation method for small-sized gate of microwave millimeter wave chip |
| CN105977147A (en) * | 2016-07-29 | 2016-09-28 | 中国电子科技集团公司第十三研究所 | Damage-free automatic-terminating etching method for nano-gate preparation |
| CN109103245A (en) * | 2018-07-26 | 2018-12-28 | 厦门市三安集成电路有限公司 | A kind of double-T shaped grid and production method and application |
| CN109461655A (en) * | 2018-09-21 | 2019-03-12 | 中国电子科技集团公司第五十五研究所 | Nitride high electronic migration rate transistor fabrication process with multi-gate structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112713185A (en) * | 2020-12-21 | 2021-04-27 | 西安电子科技大学 | T-shaped gate with supporting structure, preparation method thereof and semiconductor power device |
| CN114813851A (en) * | 2021-01-22 | 2022-07-29 | 西湖大学 | Volatile organic pollutant detector and preparation method thereof |
| CN113690132A (en) * | 2021-07-30 | 2021-11-23 | 华南理工大学 | double-T-shaped gate preparation method based on double-layer passivation precise etching |
| WO2023006036A1 (en) * | 2021-07-30 | 2023-02-02 | 华南理工大学 | Double t-shaped gate preparation method based on double-layer passivation and accurate etching |
| CN113690132B (en) * | 2021-07-30 | 2024-04-19 | 华南理工大学 | Double-layer passivation accurate etching-based preparation method of double-T-shaped gate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110707150B (en) | 2023-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7419862B2 (en) | Method of fabricating pseudomorphic high electron mobility transistor | |
| CN110808207B (en) | T-shaped nano gate and preparation method thereof | |
| US9257535B2 (en) | Gate-all-around metal-oxide-semiconductor transistors with gate oxides | |
| KR100922575B1 (en) | Semiconductor device with T-gate electrode and method for fabricating thereof | |
| US20080124852A1 (en) | Method of forming T- or gamma-shaped electrode | |
| CN109103245A (en) | A kind of double-T shaped grid and production method and application | |
| CN103887335B (en) | Manufacture method of pseudomorphic high electron mobility transistor for improving frequency characteristic | |
| JP2005191022A (en) | Field effect transistor and manufacturing method therefor | |
| CN113690132B (en) | Double-layer passivation accurate etching-based preparation method of double-T-shaped gate | |
| CN110707150A (en) | double-T-shaped nano gate and preparation method thereof | |
| US20170170313A1 (en) | Method of Producing a Pre-Patterned Structure for Growing Vertical Nanostructures | |
| CN110808208B (en) | Preparation method of T-shaped nano gate | |
| JP2008193005A (en) | Manufacturing method for semiconductor device | |
| JPH03248439A (en) | Manufacture of compound semiconductor device | |
| CN113257896B (en) | Multi-field-plate radio frequency HEMT device and preparation method thereof | |
| JP3631506B2 (en) | Method for manufacturing field effect transistor | |
| CN114447113A (en) | Novel Fin structure GaN HEMT device based on under-grid imaging and preparation method thereof | |
| JP3109590B2 (en) | Method for manufacturing semiconductor device | |
| JP3640272B2 (en) | Manufacturing method of semiconductor device | |
| CN112885899A (en) | Self-aligned low-ohmic contact resistance GaN HEMT device and manufacturing method thereof | |
| CN107170809B (en) | GaNHEMT device based on self-alignment process and manufacturing method thereof | |
| JP3486641B2 (en) | Method for manufacturing field effect transistor | |
| JPS59205765A (en) | Manufacture of semiconductor device | |
| CN211480036U (en) | GaN HEMT device based on self-alignment process | |
| JP2776053B2 (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |