CN109461655A - Nitride high electronic migration rate transistor fabrication process with multi-gate structure - Google Patents
Nitride high electronic migration rate transistor fabrication process with multi-gate structure Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
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- 230000005012 migration Effects 0.000 title claims abstract description 20
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 20
- 238000005036 potential barrier Methods 0.000 claims abstract description 17
- 238000001312 dry etching Methods 0.000 claims abstract description 10
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract 7
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 20
- 230000004888 barrier function Effects 0.000 claims description 17
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- 229940126062 Compound A Drugs 0.000 description 1
- NLDMNSXOCDLTTB-UHFFFAOYSA-N Heterophylliin A Natural products O1C2COC(=O)C3=CC(O)=C(O)C(O)=C3C3=C(O)C(O)=C(O)C=C3C(=O)OC2C(OC(=O)C=2C=C(O)C(O)=C(O)C=2)C(O)C1OC(=O)C1=CC(O)=C(O)C(O)=C1 NLDMNSXOCDLTTB-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
Abstract
Proposed by the present invention is a kind of nitride high electronic migration rate transistor fabrication process with multi-gate structure, includes the following steps: that (1) provides the first Ohmic contact as source electrode, the second Ohmic contact as drain electrode in AlGaN potential barrier；(2) first T-shape gate electrode is prepared；(3) step 1)~6 are repeated) prepare multiple T-shape gate electrodes；(4) using each gate electrode as exposure mask, multiple-grid AlGaN/GaN HEMT device is prepared using the method for dry etching.Advantage: 1) each gate electrode of multi-gate device is individually formed, and can get smaller gate electrode spacing, effectively promotes the performance of nitride high electronic migration rate transistor when as control class device application；2) the increased processing step of manufacturing process is less, reduces technical process to the greatest extent to device performance and the issuable adverse effect of reliability while guaranteeing low cost；3) good protection is capable of forming to the epi-layer surface under each gate electrode.
Description
Technical field
The present invention relates to a kind of nitride high electronic migration rate transistor fabrication process with multi-gate structure, belongs to
Transistor fabrication techniques field.
Background technique
Aluminum gallium nitride compound (AlGaN)/gallium nitride (GaN) high electron mobility transistor (HEMT) is used as the loose taboo of the third generation
Band compound semiconductor device, the characteristics such as its breakdown voltage is high, current density is big are that existing Si and GaAs etc. is partly led
Not available for body technique, so that it has unique advantage in microwave applications field.AlGaN/GaN HEMT conduct in recent years
The research of microwave power device and linear large power microwave switch device is continuously obtained propulsion, especially as microwave high power switch etc.
Class is controlled in application, in conjunction with the good heat-sinking capability of device itself, AlGaN/GaN HEMT device compares Si and GaAs device more
It is advantageous.
In the structure of conventional transistor only controlled by a gate electrode electric current device source electrode and drain electrode it
Between by with interruption, multiple-gate transistor is then to control electric current in device by two, three even more gate electrodes
Between source electrode and drain electrode by with interruption.Multiple-gate transistor is compared with for the transistor of single gate electrode, and advantage exists
In improving the control ability to electric current, for concrete application, such as microwave power switch MMIC circuit design, can effectively drop
The complexity and chip area of low circuit help to reduce chip manufacturing cost.
Fig. 1 is AlGaN/GaN HEMT device structural schematic diagram typically with a gate electrode, device gate electricity in figure
Pole 17 uses T-shape grid structure, and T-shape grid structure is generally adopted for microwave power and control class AlGaN/GaN HEMT device
With.On the one hand the purpose that AlGaN/GaN HEMT as microwave power device uses T-shape grid structure is to reduce grid resistance, promoted
The frequency characteristic of device；Another aspect T-shape grid structure has the function of electric field strength in modulation channel, and device can be effectively reduced
Peak electric field strength in part channel, suppression device current collapse promote device reliability.AlGaN/ as control class device
GaN HEMT is equally to reduce grid resistance using first purpose of T-shape grid structure, promotes the frequency characteristic of device；Specifically
AlGaN/GaN HEMT as linear large power microwave switch device is also played using the purpose of T-shape grid structure and is reduced in channel
The effect of electric field strength avoids table so that electronics in channel be inhibited to be excited into the probability of device surface state under high electric field
Influence of the face state charge and discharge to the devices switch time.
Fig. 2 and Fig. 3 is respectively to have there are two the AlGaN/GaN HEMT device structural schematic diagram with three gate electrodes, is based on
The identical effect with device in Fig. 1, device gate electrode 17 uses T-shape grid structure in figure.In order to realize the T-shape in Fig. 1
Grid structure gate electrode, existing traditional handicraft need to evaporate gate electrode metal and removing by lithographic definition gate electrode, large area
Removal is located at the excess metal on photoresist to realize.And in Fig. 2 and Fig. 3 have there are two and three gate electrodes device and
Speech, is limited by the resolution ratio of lithographic equipment and the mechanical property of photoresist, is disposably formed multiple gate electrodes using traditional handicraft
The problem of bringing is that the spacing between multiple gate electrodes can not be too small, generally requires and is maintained at 1 μm, and for multiple controls
For the device of electrode processed, the spacing reduced between each electrode be for improving performance it is necessary, such as being answered as switch
The device of multiple gate electrodes, the insertion loss that epitaxial layer introduces between multiple gate electrodes are whole by the entire device of strong influence
Loss on body.Therefore, it is necessary to a kind of new technique be invented, so that the spacing between each gate electrode of multi-gate device of production
It is as small as possible.
Summary of the invention
It is existing it is an object of the invention to overcome, a kind of nitride high electronic migration rate crystal control of multi-gate structure is provided
Method is made, each gate electrode of multiple-grid AlGaN/GaN HEMT device is individually formed using stepped process, may make that device is each
Spacing as small as possible is obtained in the case where short circuit does not occur for guarantee between gate electrode.
Technical solution of the invention:
Nitride high electronic migration rate transistor fabrication process with multi-gate structure, includes the following steps:
(1) the first Ohmic contact is provided in AlGaN potential barrier as source electrode, the second Ohmic contact as drain electrode；
(2) first T-shape gate electrode is prepared；
(3) step 1)~6 are repeated) prepare multiple T-shape gate electrodes；
(4) using each gate electrode as exposure mask, multiple-grid AlGaN/GaN HEMT device is prepared using the method for dry etching.
Advantages of the present invention:
1) each gate electrode of multi-gate device is individually formed, and can get smaller gate electrode spacing, is effectively promoted as control class
The performance of nitride high electronic migration rate transistor when device is applied；
2) the increased processing step of manufacturing process is less, reduces technical process to the greatest extent to device while guaranteeing low cost
The issuable adverse effect of part performance and reliability；
3) good protection is capable of forming to the epi-layer surface under each gate electrode.
Detailed description of the invention
Attached drawing 1 is the general structure schematic diagram of single grid AlGaN/GaN HEMT device.
Attached drawing 2 is the general structure schematic diagram of double grid AlGaN/GaN HEMT device.
Attached drawing 3 is the general structure schematic diagram of three grid AlGaN/GaN HEMT devices.
Attached drawing 4-12 is each step pair of one embodiment with the nitride high electronic migration rate transistor of multi-gate structure
The structural schematic diagram answered.
Attached drawing 13-17 is each step of another embodiment with the nitride high electronic migration rate transistor of multi-gate structure
Corresponding structural schematic diagram.
Wherein 11,21,32,41 be substrate, and 12,22,32,42 be GaN buffer layer, and 13,23,33,43 be AlGaN potential barrier
Layer, 14,15,24,25,34,35,44,45 be Ohm contact electrode, and 16,26,36,46,61,62 be dielectric layer, 47,48,63,
64 be grid foot window, and 49 be schottky barrier metal layer, and 50,65 be photoresist layer, and 51,66 be window, 17,27,28,37,38,
39,52,53,67,68 be gate electrode.
Specific embodiment
Nitride high electronic migration rate transistor fabrication process with multi-gate structure, includes the following steps:
(1) the first Ohmic contact is provided in AlGaN potential barrier as source electrode, the second Ohmic contact as drain electrode；
(2) first T-shape gate electrode is prepared；
(3) step 1)~6 are repeated) prepare multiple T-shape gate electrodes；
(4) using each gate electrode as exposure mask, multiple-grid AlGaN/GaN HEMT device is prepared using the method for dry etching.
The preparation of (2) first T-shape gate electrodes of step, comprises the technical steps that:
1) one layer of dielectric layer is deposited to be covered in source electrode, drain electrode and AlGaN potential barrier；
2) the corresponding grid foot window of each gate electrode is formed on the dielectric layer between source electrode and drain electrode；
3) it deposits in schottky barrier metal layer to the corresponding grid foot window of each gate electrode and passivation dielectric layer；
4) coating photoresist layer forms the window of first gate electrode to schottky barrier metal layer surface, exposure, development；
5) deposit gate electrode metal layer is into the window of first gate electrode of photoresist layer and definition, and is gone by stripping technology
Gate electrode metal layer except photoresist layer and thereon forms first T-shape gate electrode；
The step 1) dielectric layer is silicon nitride or silica, the method for dielectric layer deposition be sputtering, electron beam evaporation, etc. from
Daughter enhances one of chemical vapour deposition, thickness of dielectric layers 100-200nm.
Schottky barrier metal layer is one of Ni, Pt, W, WN or multiple combinations in the step 3), with a thickness of 50-
100nm。
The step 5) gate electrode metal layer is to sequentially consist of Ti, Pt, Au and Ti, basecoat Ti thickness
For 50nm-100nm, Pt is with a thickness of 50nm-100nm, and Au is with a thickness of 300nm-600nm, and the Ti on Au metal is with a thickness of 30nm-
50nm。
The preparation of (2) first T-shape gate electrodes of step, comprises the technical steps that:
1) it deposits on first medium layer to source electrode, drain electrode and AlGaN potential barrier；
2) in deposition of second dielectric layer to first medium layer；
3) the corresponding grid foot window of each gate electrode is formed in the second dielectric layer between source electrode and drain electrode；
4) it coats photoresist layer and forms the window for defining first gate electrode by exposure, development, removal is located at first later
The first medium layer that a gate electrode window is not covered by second dielectric layer；
5) deposit gate electrode metal layer is into the window of first gate electrode of photoresist layer and definition, and is gone by stripping technology
Gate electrode metal layer except photoresist layer and thereon forms first T-shape gate electrode；
First medium layer is single layer SiO in the step 1)2Or SiN/SiO2Compound medium layer, when first medium layer is single layer
SiO2When, with a thickness of 10-20nm；When first medium layer is SiN/SiO2When compound medium layer, it is in contact with AlGaN potential barrier
One layer is SiN, with a thickness of 5-10nm, SiO2With a thickness of 10-20nm.
Second dielectric layer is SiN in the step 2, with a thickness of 100-200nm.
Removal is located at the first medium layer that first gate electrode window is not covered by second dielectric layer in the step 4):
If first medium layer is SiO2When, it is removed using diluted hydrofluoric acid solution；If first medium layer is SiN/SiO2Compound medium layer
When, SiO is removed using diluted hydrofluoric acid solution2, then using the SiN in the method removal compound medium layer of dry etching.
Technical solution of the present invention is described further with reference to the accompanying drawing.
As shown in figure 4, the general structure schematic diagram of the used epitaxial material of AlGaN/GaN HEMT, include substrate 41,
GaN buffer layer 42 and AlGaN potential barrier 43.The material used in substrate 41 in AlGaN/GaN HEMT, GaN buffer layer 42
And the formation of AlGaN potential barrier 43 can refer to pertinent literature report；In addition in Fig. 4 to be that AlGaN/GaN HEMT is used outer
The general structure schematic diagram for prolonging material, shows the epitaxial material structure there is also other forms, and other structure types can refer to
Pertinent literature is not described further.
As shown in figure 5, providing Ohm contact electrode in AlGaN potential barrier 43 as source electrode 44 and drain electrode 45, source
Preferably distance is 3 microns to 5 microns to the spacing of electrode 44 and drain electrode 45.The formation of source electrode 44 and drain electrode 45 generally needs
To need to deposit the photoresist layer in 45 region of source electrode 44 and drain electrode, deposit by coating photoresist layer, exposure, development removal
Ohmic contact metal layer and removing removal photoresist layer and ohmic contact metal layer thereon, for coating photoresist layer, expose
Light, development and photoresist is removed with stripping technology and metal layer thereon is well known in the art, herein no longer
It repeats.Source electrode 44 and drain electrode 45, which can be used, includes but are not limited to the multiple layer metals such as Ti/Al/Ni/Au, Ti/Al/Mo/Au
System generally also needs that source electrode 44 and drain electrode 45 and the semiconductor layer under it is made to form good Europe by high annealing
Nurse contact, annealing temperature are preferably 800 DEG C -850 DEG C.
Embodiment 1
After the completion of source electrode 44 and drain electrode 45, one layer of dielectric layer 46 is deposited as shown in Figure 6, and dielectric layer 46 is covered on source electricity simultaneously
In pole 44, drain electrode 45 and AlGaN potential barrier 43, material workable for dielectric layer 46 includes silicon nitride (SiN) and silica
(SiO2One of), the method that dielectric layer 46 deposits includes sputtering, electron beam evaporation, plasma reinforced chemical vapor deposition
(PECVD), preferably dielectric material and deposition process are SiN and PECVD, preferably with a thickness of 100-200nm.
As shown in fig. 7, forming the window 47 for being referred to as grid foot on dielectric layer 46 between source electrode 44 and drain electrode 45
With 48, the formation of grid foot window 47 and 48 generally require by coating photoresist layer, exposure, development and etc. in grid foot window 47
With form window in the photoresist layer of 48 tops, using photoresist layer be that exposure mask uses the method for dry plasma by window
In dielectric layer 46 remove, and grid foot window 47 and 48 is obtained on dielectric layer 46 after removing the photoresist on dielectric layer 46.
As shown in figure 8, in deposit schottky barrier metal layer 49 to grid foot window 47 and 48 and passivation dielectric layer 46, Xiao
The effect of special base barrier metal layer 49 is to form schottky junctions with the AlGaN epitaxial layer 43 in grid foot window 47 and 48 on one side
Touching, another effect are the surfaces for playing AlGaN epitaxial layer 43 in protection grid foot window 47 and 48, prevent subsequent technique from producing to it
It is raw to destroy and stain.Schottky barrier metal layer 49 is preferably the metals such as Ni, Pt, W, WN or their combination, thickness
Preferably 50-100nm.
As shown in figure 9, coating photoresist layer 50 arrives 49 surface of schottky barrier metal layer, exposure, development form window 51,
Gate electrode metal layer is deposited into photoresist layer 50 and window 51, and grid by stripping technology removal photoresist layer and thereon
Electrode metal layer forms gate electrode 52 as shown in Figure 10.The effect of gate electrode 52 is the grid resistance for reducing device, promotes device
Frequency characteristic.Gate electrode metal layer is preferably deposited by the way of evaporation, since schottky barrier metal layer 49 successively
Deposit the multiple layer metal system of Ti/Pt/Au/Ti form, wherein Ti is preferably with a thickness of 50nm-100nm, Pt preferably with a thickness of
50nm-100nm, Au are preferably with a thickness of 300nm-600nm, and the Ti on Au metal is preferably with a thickness of 30nm-50nm.
As shown in figure 11, gate electrode 53 is obtained using the method as same gate electrode 52, gate electrode 53 uses and gate electrode
52 identical multiple layer metal systems, each metal layer thickness used by the two are also identical.
Using gate electrode 52 and gate electrode 53 as exposure mask, schottky barrier metal layer is removed using the method for dry etching
49, the schottky barrier metal layer 49 under gate electrode 52 and gate electrode 53 is left behind, figure as shown in figure 12, gate electrode are formed
52 and gate electrode 53 respectively be located at they below schottky barrier metal layer 49 formed two independent T-shape electrodes, from
And realize the production of double grid AlGaN/GaN HEMT device in Fig. 2.
Although the present embodiment is described just for the production of double grid AlGaN/GaN HEMT device, this method is same
It is suitble to the production of the even more gate electrode AlGaN/GaN HEMT devices of three grid.For with more multi-gated electrode device manufacture,
Grid foot window, large area deposit schottky barrier metal layer, the grid gold for being respectively formed each gate electrode can be equally formed simultaneously
Belong to, the Schottky barrier metal in addition to below grid metal is removed as exposure mask large area dry etching using the grid metal of each gate electrode
Layer is to form the production of the even more gate electrode AlGaN/GaN HEMT devices of three grid.
Embodiment 2
After completing source electrode 44 and the production of drain electrode 45 as shown in Figure 5, AA dielectric layer 61 and medium B are successively deposited as shown in figure 13
On layer 62 to source electrode 44, drain electrode 45 and AlGaN potential barrier 43, material workable for medium A layer 61 includes the SiO of single layer2
Either by SiN and SiO2The compound medium layer of composition, when for SiO2When, thickness is preferably 10-20nm；When for SiN and
SiO2When the compound medium layer of composition, one layer to be in contact with AlGaN potential barrier is SiN, preferably with a thickness of 5-10nm, thereon
SiO2Thickness is preferably 10-20nm.Medium B layer 62 is SiN, preferably with a thickness of 100-200nm.Medium A layer 61 and B
The method that dielectric layer 62 deposits includes sputtering, electron beam evaporation, plasma reinforced chemical vapor deposition (PECVD), preferably
Deposition process is PECVD.
The window 63 for being referred to as grid foot is formed on the medium B layer 62 between source electrode 44 and drain electrode 45 as shown in figure 14
With 64, the formation of grid foot window 63 and 64 generally require by coating photoresist layer, exposure, development and etc. in grid foot window 63
With form window in the photoresist layer of 64 tops, using photoresist layer be that exposure mask uses the method for dry plasma by window
In medium B layer 62 remove, and grid foot window 63 and 64 is obtained on medium B layer 62 after removing the photoresist on medium B layer 62.
The key that medium A layer 61 in grid foot window 63 and 64 is able to not be removed during dry method removes medium B layer 62 is it
For the SiO of single layer2Either by SiN and SiO2The compound medium layer of composition, SiO2It is more difficult the method for dry etching compared to SiN
It is removed, so that the medium A layer 61 in grid foot window 63 and 64 is retained, to play to 43 surface of AlGaN epitaxial layer
Protective effect.
Photoresist layer 65 is coated as shown in figure 15 and window 66 is formed by exposure, development, and removal is positioned at window 66 later
In the medium A layer 61 that is not covered by medium B layer 62.When medium A layer 61 is SiO2When, diluted hydrofluoric acid solution can be used
Removal, hydrofluoric acid are easy that removal SiO can be easy to2Dielectric layer, without being had an impact to for the medium B layer 62 of SiN medium.
When medium A layer 61 is SiN and SiO2When the compound medium layer of composition, SiO can be removed using diluted hydrofluoric acid solution2, then
Using the SiN in the method removal compound medium layer of dry etching, at this moment medium B layer 62 can be had an impact, remove compound A and be situated between
Also medium B layer 62 can be partially removed in matter layer 61 while SiN, but since two kinds of thickness differ larger, brought shadow
Sound can be avoided by reasonably designing.
Deposit gate electrode metal layer into photoresist layer 65 and window 66, and by stripping technology removal photoresist layer and
Gate electrode metal layer thereon forms T-shape gate electrode 67 as shown in figure 16.The effect of gate electrode 67, deposit mode and
Composition is the same as embodiment 1.
As shown in figure 17, T-shape gate electrode 68 is obtained using the method as same gate electrode 67, gate electrode 68 uses and grid
The identical multiple layer metal system of electrode 67, each metal layer thickness used by the two is also identical, and gate electrode 67 and gate electrode 68 are made
For two independent electrodes, to realize the production of double grid AlGaN/GaN HEMT device in Fig. 2.
Although the present embodiment is described just for the production of double grid AlGaN/GaN HEMT device, this method is same
It is suitble to the production of the even more gate electrode AlGaN/GaN HEMT devices of three grid.For with more multi-gated electrode device manufacture,
Grid foot window can be equally formed simultaneously, be respectively formed the grid metal of each gate electrode to form the even more gate electrodes of three grid
The production of AlGaN/GaN HEMT device.
Claims (9)
1. the nitride high electronic migration rate transistor fabrication process with multi-gate structure, it is characterised in that include the following steps:
(1) the first Ohmic contact is provided in AlGaN potential barrier as source electrode, the second Ohmic contact as drain electrode；
(2) first T-shape gate electrode is prepared；
(3) step 1)~6 are repeated) prepare multiple T-shape gate electrodes；
(4) using each gate electrode as exposure mask, multiple-grid AlGaN/GaN HEMT device is prepared using the method for dry etching.
2. as described in claim 1 with the nitride high electronic migration rate transistor fabrication process of multi-gate structure, feature
It is the preparation of first T-shape gate electrode of step 2, comprises the technical steps that:
1) one layer of dielectric layer is deposited to be covered in source electrode, drain electrode and AlGaN potential barrier；
2) the corresponding grid foot window of each gate electrode is formed on the dielectric layer between source electrode and drain electrode；
3) it deposits in schottky barrier metal layer to the corresponding grid foot window of each gate electrode and passivation dielectric layer；
4) coating photoresist layer forms the window of first gate electrode to schottky barrier metal layer surface, exposure, development；
5) deposit gate electrode metal layer is into the window of first gate electrode of photoresist layer and definition, and is gone by stripping technology
Gate electrode metal layer except photoresist layer and thereon forms first T-shape gate electrode.
3. with the nitride high electronic migration rate transistor fabrication process of multi-gate structure according to right 2, it is characterized in that
The step 1) dielectric layer is silicon nitride or silica, and the method for dielectric layer deposition is sputtering, electron beam evaporation, plasma
Enhance one of chemical vapour deposition, thickness of dielectric layers 100-200nm.
4. with the nitride high electronic migration rate transistor fabrication process of multi-gate structure according to right 2, it is characterized in that
Schottky barrier metal layer is one of Ni, Pt, W, WN or multiple combinations in the step 3), with a thickness of 50-100nm.
5. with the nitride high electronic migration rate transistor fabrication process of multi-gate structure according to right 2, it is characterized in that
The step 5) gate electrode metal layer, sequentially consists of Ti, Pt, Au and Ti, basecoat Ti is with a thickness of 50nm-
100nm, Pt are with a thickness of 50nm-100nm, and Au is with a thickness of 300nm-600nm, and the Ti on Au metal is with a thickness of 30nm-50nm.
6. as described in claim 1 with the nitride high electronic migration rate transistor fabrication process of multi-gate structure, feature
It is the preparation of first T-shape gate electrode of step 2, comprises the technical steps that:
1) it deposits on first medium layer to source electrode, drain electrode and AlGaN potential barrier；
2) in deposition of second dielectric layer to first medium layer；
3) the corresponding grid foot window of each gate electrode is formed in the second dielectric layer between source electrode and drain electrode；
4) it coats photoresist layer and forms the window for defining first gate electrode by exposure, development, removal is located at first later
The first medium layer that a gate electrode window is not covered by second dielectric layer；
5) deposit gate electrode metal layer is into the window of first gate electrode of photoresist layer and definition, and is gone by stripping technology
Gate electrode metal layer except photoresist layer and thereon forms first T-shape gate electrode.
7. with the nitride high electronic migration rate transistor fabrication process of multi-gate structure according to right 6, it is characterized in that
First medium layer is single layer SiO in the step 1)2Or SiN/SiO2Compound medium layer, when first medium layer is single layer SiO2When,
With a thickness of 10-20nm；When first medium layer is SiN/SiO2When compound medium layer, one layer to be in contact with AlGaN potential barrier is
SiN, with a thickness of 5-10nm, SiO2With a thickness of 10-20nm.
8. with the nitride high electronic migration rate transistor fabrication process of multi-gate structure according to right 6, it is characterized in that
Second dielectric layer is SiN in the step 2, with a thickness of 100-200nm.
9. with the nitride high electronic migration rate transistor fabrication process of multi-gate structure according to right 6, it is characterized in that
Removal is located at the first medium layer that first gate electrode window is not covered by second dielectric layer in the step 4): if first is situated between
Matter layer is SiO2When, it is removed using hydrofluoric acid solution；If first medium layer is SiN/SiO2When compound medium layer, using hydrofluoric acid
Solution removes SiO2, then using the SiN in the method removal compound medium layer of dry etching.
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