CN104064593A - Semiconductor device - Google Patents
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- CN104064593A CN104064593A CN201310731532.8A CN201310731532A CN104064593A CN 104064593 A CN104064593 A CN 104064593A CN 201310731532 A CN201310731532 A CN 201310731532A CN 104064593 A CN104064593 A CN 104064593A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 183
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 239000000460 chlorine Substances 0.000 claims description 20
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 12
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 12
- 229910052801 chlorine Inorganic materials 0.000 claims description 12
- 239000011737 fluorine Substances 0.000 claims description 12
- 229910052731 fluorine Inorganic materials 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000009413 insulation Methods 0.000 abstract 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 7
- 229910002601 GaN Inorganic materials 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 229910002704 AlGaN Inorganic materials 0.000 description 2
- 229910000952 Be alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 150000001450 anions Chemical class 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- CVOFKRWYWCSDMA-UHFFFAOYSA-N 2-chloro-n-(2,6-diethylphenyl)-n-(methoxymethyl)acetamide;2,6-dinitro-n,n-dipropyl-4-(trifluoromethyl)aniline Chemical compound CCC1=CC=CC(CC)=C1N(COC)C(=O)CCl.CCCN(CCC)C1=C([N+]([O-])=O)C=C(C(F)(F)F)C=C1[N+]([O-])=O CVOFKRWYWCSDMA-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- OBNDGIHQAIXEAO-UHFFFAOYSA-N [O].[Si] Chemical compound [O].[Si] OBNDGIHQAIXEAO-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor device comprises a first semiconductor layer formed by a first nitride semiconductor, a second semiconductor layer formed on the first semiconductor layer, a source electrode formed on the second semiconductor layer, a drain electrode formed on the second semiconductor layer, a first grid electrode formed on the second semiconductor layer between the source electrode and the drain electrode, a second grid electrode formed on the second semiconductor layer between the source electrode and the first grid electrode via an insulation film, and a third grid electrode formed on the second semiconductor layer between the drain electrode and the first grid electrode via the insulation film, the second semiconductor layer is formed by a second nitride semiconductor whose band gap is larger than the first nitride semiconductor, the first grid electrode is connected with the second semiconductor layer in a Schottky manner, the second grid electrode is electrically connected with the first grid electrode, and the third grid electrode is electrically connected with the first grid electrode.
Description
The application requires taking Japanese patent application No. 2013-59337 (applying date: on March 22nd, 2013) as basic priority of applying for.The application is by comprising the full content of basis application with reference to this basis application.
Technical field
Embodiments of the present invention relate to semiconductor device.
Background technology
The switch element using in Switching Power Supply or inverter circuit etc. requires high withstand voltage, low on-resistance.And, can improve these those the long relations that disappear between withstand voltage and conducting resistance by its good material behavior with the switch element of nitride-based semiconductor.Therefore, think and be expected to realize low on-resistance and high withstand voltageization.
As the switch element that uses nitride-based semiconductor, there is the HEMT(High Electron Mobility Transistor that uses the heterogeneous structure of AlGaN/GaN: High Electron Mobility Transistor).And, one of construct as the gate electrode of the HEMT that uses the heterogeneous structure of AlGaN/GaN, there is Schottky type gate electrode structure.In Schottky type gate electrode structure, the relative semiconductor layer of gate electrode carries out Schottky joint.
The HEMT of Schottky type gate electrode structure, due to the gate insulating film not possessing as a reason of charge trap, so threshold variation is smaller.But in the HEMT of Schottky type gate electrode structure, grid leakage current when cut-off becomes problem.
Summary of the invention
Embodiments of the present invention provide a kind of semiconductor device that reduces grid leakage current.
The semiconductor device of execution mode, possesses: the first semiconductor layer, is made up of the first nitride-based semiconductor; The second semiconductor layer, is formed on above-mentioned the first semiconductor layer, is made up of the second nitride-based semiconductor that band gap is large compared with above-mentioned the first nitride-based semiconductor; Source electrode, is formed on the second semiconductor layer; And drain electrode, be formed on above-mentioned the second semiconductor layer.Also possess: first grid electrode, be formed on above-mentioned the second semiconductor layer between above-mentioned source electrode and drain electrode, carry out Schottky with above-mentioned the second semiconductor layer and engage; Second grid electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned source electrode and above-mentioned first grid electrode across dielectric film, is electrically connected with first grid electrode; And the 3rd gate electrode, be formed on above-mentioned the second semiconductor layer between above-mentioned drain electrode and above-mentioned first grid electrode across dielectric film, be electrically connected with first grid electrode.
Embodiment
In this specification, transistorized " threshold value is low " represents that relatively threshold value is in the situation of negative direction, and in addition, transistorized " threshold value is high " represents that relatively threshold value is in the situation of positive direction.
For example, in the case of to normal conducting (normally on), threshold value is that two transistorized threshold values bearing compare, the low expression absolute value of threshold value is large, threshold value is high represents that absolute value is little.
In addition, for example, in the case of to normal cut-off (normally off), threshold value is that two positive transistorized threshold values compare, the low expression absolute value of threshold value is little, threshold value is high represents that absolute value is large.
(the first execution mode)
Fig. 1 is the constructed profile that represents the structure of the semiconductor device of present embodiment.The semiconductor device of present embodiment is the HEMT of normal conducting.The HEMT that uses heterojunction, because channel mobility is high, so can make conducting resistance little, is suitable for power electronics semiconductor device.In addition, high channel mobility is also suitable for high frequency action.
The first semiconductor layer 14 that the semiconductor device of present embodiment possesses substrate 10, forms resilient coating 12 on substrate 10, forms on resilient coating 12, the second semiconductor layer 16 forming on the first semiconductor layer 14.
Substrate 10 is for example made up of silicon (Si).Beyond silica removal, for example, also can apply sapphire (Al
2o
3) or carborundum (SiC).
Resilient coating 12 possesses the function that the lattice making between substrate 10 and the first semiconductor layer 14 does not mate mitigation.Resilient coating 12 is for example by aluminium gallium nitride alloy (Al
xga
1-xn(0 < X < 1)) multi-ply construction form.
The first semiconductor layer 14 is action layers (channel layer), and the second semiconductor layer 16 is barrier layer (electron supply layers).The second semiconductor layer 16 is formed by the nitride-based semiconductor that band gap is large compared with the first semiconductor layer 14.
The first nitride-based semiconductor that forms the first semiconductor layer 14 is for example gallium nitride or the aluminium gallium nitride alloy (Al of non-doping
xga
1-Xn(0≤X≤1)).The first nitride-based semiconductor is that N-shaped or p-type can.The thickness of the first semiconductor layer 14 is for example 0.5～3 μ m.
In addition, the second nitride-based semiconductor of formation the second semiconductor layer 16 is for example the aluminium gallium nitride alloy (Al of N-shaped
yga
1-Yn(0 < Y≤1, X < Y)).The second nitride-based semiconductor also can non-ly adulterate.The thickness of the second semiconductor layer 16 is for example 20～50nm.
In addition, first and second nitride-based semiconductor is not necessarily limited to above-mentioned material, also can apply above-mentioned nitride-based semiconductor in addition.
Between the first semiconductor layer 14 and the second semiconductor layer 16, form heterojunction boundary.In the time of transistorized turn-on action, form two-dimensional electron gas at heterojunction boundary place as charge carrier.
On the second semiconductor layer 16, form source electrode 18 and drain electrode 20.Source electrode 18 and drain electrode 20 are for example metal electrodes, and metal electrode is for example electrode taking aluminium (Al) as principal component.Source electrode 18 and drain electrode 20, and the second semiconductor layer 16 between, be ohmic contact.Source electrode 18 is for example 10 μ m left and right with the distance of drain electrode 20.
And, on the second semiconductor layer 16 between source electrode 18 and drain electrode 20, form first grid electrode 22.First grid electrode 22 carries out Schottky joint with respect to the second semiconductor layer 16.The grid length of first grid electrode is for example 1 μ m.
First grid electrode 22 is for example metal electrode.Metal electrode is for example nickel (Ni) electrode, titanium (Ti) electrode or platinum (Pt).Also can be alloy or the lit-par-lit structure of these metals.In addition,, for the low resistance of gate electrode, also can make gold that resistance is low (Au) etc. stacked on upper strata.
In addition,, on the second semiconductor layer 16 between source electrode 18 and first grid electrode 22, be formed with second grid electrode 26 across dielectric film 24.Second grid electrode 26 is electrically connected with first grid electrode 22.The grid length of second grid electrode 26 is for example 1 μ m.
And, on the second semiconductor layer 16 between drain electrode 20 and first grid electrode 22, be formed with the 3rd gate electrode 28 across dielectric film 24.The 3rd gate electrode 28 is electrically connected with first grid electrode 22.The grid length of the 3rd gate electrode 28 is for example 1 μ m.
Dielectric film 24 is as the gate insulating film performance function of second and third gate electrode 26,28.Dielectric film 24 is for example to form as material easily and the high silicon nitride film of stability.But dielectric film 24 is not limited to silicon nitride film, for example, can apply the other materials such as silicon oxide film, oxygen silicon nitride membrane, pellumina.
Second grid electrode 26 and the 3rd gate electrode 28 are for example metal electrodes.Metal electrode is for example nickel (Ni) electrode, titanium (Ti) electrode or platinum (Pt).Also can be alloy or the lit-par-lit structure of these metals.In addition,, for the low resistance of gate electrode, also can make gold that resistance is low (Au) etc. stacked on upper strata.
In addition, in Fig. 1, the frame line A of dotted line represents the transistor configurations of controlling with first grid electrode 22, and the frame line B of dotted line represents the transistor configurations of controlling with second grid electrode 26, and the frame line C of dotted line represents the transistor configurations of controlling with the 3rd gate electrode 28.
Fig. 2 A, Fig. 2 B are the figure of the effect of the semiconductor device of explanation present embodiment.Fig. 2 A represents the transistor configurations of controlling with first grid electrode 22 of present embodiment and the key diagram of grid voltage interdependence transistor configurations, drain current controlled with the 3rd gate electrode 26.Fig. 2 B is the key diagram of the grid voltage interdependence of the drain current of the HEMT of explanation present embodiment.In each figure, transverse axis is all grid voltage, and the longitudinal axis is all drain current.
In Fig. 2 A, represent the characteristic of the transistor configurations (following, also referred to as structure A) of controlling with first grid electrode 22 with dotted line A.The first threshold (Vth1) of structure A possesses negative value., as the transistor of normal conducting.Structure A is the transistor of Schottky type gate electrode structure.
In structure A, if grid voltage exceedes first threshold (Vth1) and increases to positive side, drain current increases.On the other hand, if grid voltage exceedes first threshold (Vth1) and increases to minus side, temporarily become immobilising drain current and again start to flow.In other words,, after pinch off (pinch off), if becoming greatly drain current, the negative absolute value of grid voltage transfers increase to.This electric current is grid leakage current mobile between gate electrode and drain electrode.The structure A only forming with schottky junction with gate electrode, is difficult to suppress this grid leakage current.
On the other hand, in Fig. 2 A, represent the characteristic of the transistor configurations (following, also referred to as structure C) of controlling with the 3rd gate electrode 28 with single-point line C.The 3rd threshold value (Vth3) of structure C possesses negative value., as the transistor of normal conducting.And, in structure B, between gate electrode and semiconductor layer, possess insulating barrier, be MIS(Metal Insulator Semicomnductor: metal-insulator semiconductor (MIS)) and the transistor of type gate electrode structure.
In structure C, also in the time that grid voltage exceedes the 3rd threshold value (Vth3) and increase to positive side, drain current increase.But, owing to having dielectric film 24 between the 3rd gate electrode 28 and the second semiconductor layer 16, so even if grid voltage exceedes the 3rd threshold value (Vth3) and increases to minus side, between gate electrode 28 and drain electrode 20, mobile grid leakage current is also small.
In addition, in Fig. 2 A, though do not show, with the transistor configurations of second grid electrode control (following, also referred to as structure B) be also the transistor of MIS type gate electrode structure, its characteristic is also identical with the characteristic of constructing C.
In the HEMT of present embodiment, the structure A of the structure B of MIS type gate electrode structure, Schottky type gate electrode structure, the structure C of MIS type gate electrode structure become the transistor configurations being connected in series between source electrode 18 and drain electrode 20.Thereby, about the grid voltage interdependence of the drain current of this HEMT, if the characteristic of supposition structure B and structure C is identical, as shown in Figure 2 B, be to make the structure A of Fig. 2 A and construct the overlapping and characteristic that obtains of the characteristic of C.,, with the less side's of the drain current in structure A and structure C drain current, carry out the drain current of regulation HEMT entirety.
In present embodiment, first threshold (Vth1) is than second and third threshold value (Vth2, Vth3) height.Thereby the magnitude relationship of first threshold (Vth1) and the 3rd threshold value (Vth3) is as shown in Fig. 2 A, B.
From HEMT on the whole, as shown in Figure 2 B, drain current flows when grid voltage is 0V, in conducting state.And if grid voltage is increased to negative direction from 0V, the first threshold (Vth1) of the structure A first constructing at Schottky type gate electrode locates to become pinch off state, transistor becomes cut-off.And then, if grid voltage is increased to minus side, make the mobile grid leakage current of first grid electrode 22 at Schottky type gate electrode structure.
On the other hand, the structure C of MIS type gate electrode structure is compared with structure A, locate to become pinch off state in the 3rd threshold value (Vth3) of minus side.Therefore,, in HEMT entirety, even if grid voltage is increased to minus side, at the minus side of the 3rd threshold value (Vth3), also be truncated by structure C at the mobile grid leakage current of first grid electrode 22.Therefore, as a result of and grid leakage current is suppressed.
Like this, in the HEMT of present embodiment, by Schottky type gate electrode structure and MIS type gate electrode structure are connected in series, can suppressor grid leakage current.In addition, it not trap by the electric charge due to interfacial state (interface state) etc. and second and third threshold value (Vth2 of the MIS type gate electrode structure of threshold variation easily occurs, Vth3), but by being difficult to the first threshold (Vth1) of the Schottky type gate electrode structure that threshold variation occurs, carry out the threshold value of regulation HEMT entirety.
Thereby even the threshold variation of second and third threshold value (Vth2, Vth3), HEMT entirety is also difficult to observe this impact.Thus, grid leakage current is suppressed, and, realize the HEMT that threshold variation is little.
In addition, as shown in Fig. 2 A, B, voltage (the white arrow in Fig. 2) height that second and third threshold value (Vth2, Vth3) preferably applies when to first, second and the cut-off of the 3rd gate electrode 22,26,28.This be because, thus, in the time that HEMT end, keep structure B and construct the pinch off state of C, grid leakage current can further suppress.
In addition, second and third threshold value (Vth2, Vth3), be preferably greater than or equal to 0.1V and be less than or equal to 1V with the absolute value (the Δ Vth in Fig. 2) of the difference of first threshold (Vth1).This be because, if likely there is following situation in not enough 0.1V, that is: in the case of second and third threshold value (Vth2, Vth3) variation, threshold value becomes than first threshold (Vth1) height, the threshold value of HEMT entirety by easily change second or the 3rd threshold value (Vth2, Vth3) specify.In addition,, if exceed 1V, the blocking of grid leakage current of the Schottky type gate electrode structure based on MIS type gate electrode structure (structure B, C) (structure A) likely becomes insufficient.; if second and third threshold value (Vth2; Vth3) with first threshold (Vth1) too from; in the situation that grid voltage is shifted from first threshold (Vth1) to minus side; owing to not producing the pinch off of structure B, C in the short time, so blocking of grid leakage current likely becomes insufficient.
In addition, in the HEMT of present embodiment, Schottky type gate electrode structure, MIS type gate electrode constructs threshold value separately, first, second, third threshold value can be by providing element structure, material, impurity concentration etc. to utilize parsing or numerical computations to calculate.
In addition, the grid of second and third gate electrode 26,28 are long preferably longer than the grid of first grid electrode 22.This is because thus, the shut-off feature of structure B, the C of MIS type gate electrode structure improves, the shut-off feature raising of grid leakage current.
(the second execution mode)
The semiconductor device of present embodiment is except first grid electrode is the 3rd nitride-based semiconductor of p-type and the lit-par-lit structure of metal, identical with the first execution mode.Thereby, for omitting and describe with the content of the first execution mode repetition.
Fig. 3 is the constructed profile that represents the structure of the semiconductor device of present embodiment.As shown in Figure 3, in the semiconductor device of present embodiment, first grid electrode is the 3rd nitride-based semiconductor 22a of p-type and the lit-par-lit structure of metal 22b.
, the transistor configurations with the control of first grid electrode shown in the frame line A of dotted line (structure A) possesses so-called junction gate electrode structure.Junction gate electrode structure is also identical with Schottky type gate electrode structure, due to the gate insulating film not possessing as a reason of charge trap, so threshold variation is little.
The 3rd nitride-based semiconductor 22a of p-type contains the gallium nitride (GaN) of magnesium (Mg) as p-type impurity.
According to present embodiment, by the 3rd nitride-based semiconductor 22a of p-type, the electromotive force of the first semiconductor layer (channel layer) 14 is raised.Therefore the first threshold (Vth1) that, easily makes to construct A moves to positive direction., easily make first threshold (Vth1) improve.Thus, easily form the HEMT of normal cut-off.
In addition, identical with the first execution mode, realize the HEMT that grid leakage current is suppressed and threshold variation is little.
(the 3rd execution mode)
The semiconductor device of present embodiment, the thickness of the second semiconductor layer under second and third gate electrode is thinner than the thickness of the second semiconductor layer under first grid electrode, identical with the first execution mode.Thereby, for first execution mode repeat content, omit describe.
Fig. 4 is the constructed profile that represents the structure of the semiconductor device of present embodiment.As shown in Figure 4, in the semiconductor device of present embodiment, the thickness of the second semiconductor layer 16 under second and third gate electrode 26,28 is thinner than the thickness of the second semiconductor layer 16 under first grid electrode 22.
The transistor configurations (structure C) that, use the 3rd gate electrode 28 shown in the frame line C of the transistor configurations of controlling with second grid electrode 26 shown in the frame line B of dotted line (structure B), dotted line is controlled possesses so-called depression (recess) structure.
According to present embodiment, by making to construct B and structure C for depression structure, easily make the structure B of MIS type gate electrode structure and the threshold value of structure C improve.In addition, by change cave in structure the degree of depth, it is easy that the adjustment of threshold value also becomes.
Thereby, easily by the first threshold (Vth1) of structure A, with the difference of second and third threshold value (Vth2, Vth3) of structure B, C be adjusted into just when.Particularly, easily make first threshold (Vth1), approach with second and third threshold value (Vth2, Vth3).
Thereby, realize the HEMT of easier suppressor grid leakage current.In addition, realizing in the HEMT this point that threshold variation is little, identical with the first execution mode.
(the 4th execution mode)
The semiconductor device of present embodiment, the thickness of the second semiconductor layer under second and third gate electrode is thinner than the thickness of the second semiconductor layer under first grid electrode, identical with the second execution mode.Thereby, for second execution mode repeat content, omit describe.
Fig. 5 is the constructed profile that represents the structure of the semiconductor device of present embodiment.As shown in Figure 5, in the semiconductor device of present embodiment, the thickness of the second semiconductor layer 16 under second and third gate electrode 26,28 is thinner than the thickness of the second semiconductor layer 16 under first grid electrode 22.
The transistor configurations (structure C) that, use the 3rd gate electrode 28 shown in the frame line C of the transistor configurations of controlling with second grid electrode 26 shown in the frame line B of dotted line (structure B), dotted line is controlled possesses so-called depression structure.
According to present embodiment, by making to construct B and structure C for depression structure, easily make the structure B of MIS type gate electrode structure and the threshold value of structure C improve.In addition, by change cave in structure the degree of depth, it is easy that the adjustment of threshold value also becomes.Thereby, easily by the first threshold (Vth1) of structure A, with the difference of second and third threshold value (Vth2, Vth3) of structure B, C be adjusted into just when.Particularly, easily make first threshold (Vth1) and second and third threshold value (Vth2, Vth3) approach.
Thereby, realize the HEMT of easier suppressor grid leakage current.In addition, realizing in the HEMT this point that threshold variation is little, identical with the second execution mode.
(the 5th execution mode)
The semiconductor device of present embodiment possesses the semiconductor regions that contains fluorine or chlorine in the second semiconductor layer under second and third gate electrode, identical with the first execution mode.Thereby, for first execution mode repeat content, omit describe.
Fig. 6 is the constructed profile that represents the structure of the semiconductor device of present embodiment.As shown in Figure 6, in the semiconductor device of present embodiment, in the second semiconductor layer 16 under second and third gate electrode 26,28, possesses the semiconductor regions 30 that contains fluorine (F) or chlorine (Cl).
Semiconductor regions 30 for example can be by forming fluorine (F) or chlorine (Cl) Implantation in the second semiconductor layer 16.
According to present embodiment, by semiconductor regions 30 is set, can improve the threshold value as structure B and the structure C of MIS type gate electrode structure.That is, by fluorine (F) or chlorine (Cl) as anion are imported in the second semiconductor layer 16, produce the effect of offsetting electric field, can improve threshold value.
In addition,, by changing fluorine (F) or chlorine (Cl) amount, it is easy that the adjustment of threshold value also becomes.Thereby, easily by the first threshold (Vth1) of structure A, with the difference of second and third threshold value (Vth2, Vth3) of structure B, C be adjusted into just when.Particularly, easily make first threshold (Vth1) and second and third threshold value (Vth2, Vth3) approach.
Thereby, realize the HEMT of easier suppressor grid leakage current.In addition, realizing in the HEMT this point that threshold variation is little, identical with the first execution mode.
(the 6th execution mode)
The semiconductor device of present embodiment, possesses the semiconductor regions that contains fluorine or chlorine in the second semiconductor layer under second and third gate electrode, identical with the second execution mode.Thereby, for second execution mode repeat content, omit describe.
Fig. 7 is the constructed profile that represents the structure of the semiconductor device of present embodiment.As shown in Figure 7, in the semiconductor device of present embodiment, in the second semiconductor layer 16 under second and third gate electrode 26,28, possesses the semiconductor regions 30 that contains fluorine (F) or chlorine (Cl).
Semiconductor regions 30 for example can be by forming fluorine (F) or chlorine (Cl) Implantation in the second semiconductor layer 16.
According to present embodiment, by semiconductor regions 30 is set, can improve the threshold value of structure B and the structure C of MIS type gate electrode structure.That is, by fluorine (F) or chlorine (Cl) as anion are imported in the second semiconductor layer 16, produce the effect of offsetting electric field, can improve threshold value.
In addition,, by changing fluorine (F) or chlorine (Cl) amount, it is easy that the adjustment of threshold value also becomes.Thereby, easily by the first threshold (Vth1) of structure A, with the difference of second and third threshold value (Vth2, Vth3) of structure B, C be adjusted into just when.Particularly, easily make first threshold (Vth1) and second and third threshold value (Vth2, Vth3) approach.
Thereby, realize the HEMT of easier suppressor grid leakage current.In addition, realizing in the HEMT this point that threshold variation is little, identical with the second execution mode.
In above execution mode, exemplify the profile construction that the first to the 3rd gate electrode separates physically and be illustrated.But the integrated physically structure of the first to the 3rd gate electrode is also passable.
In addition, in above execution mode, the example using HEMT as semiconductor device is illustrated, but for the field effect transistor beyond HEMT, also can apply the present invention.In addition, field effect transistor has been combined to the elements such as Schottky barrier diode and the integrated circuit that obtains is also contained in the scope of semiconductor device of the present invention.
Several execution mode of the present invention has been described, but these execution modes are to point out as an example, and are not intended to limit scope of invention.These new execution modes can be implemented with other various forms, in the scope of purport that does not depart from invention, can carry out various omissions, replacement, change.These execution modes and distortion thereof are included in scope of invention and purport, and are included in the invention and equivalency range thereof that claim records.
Brief description of the drawings
Fig. 1 is the constructed profile that represents the structure of the semiconductor device of the first execution mode.
Fig. 2 A, Fig. 2 B are the figure of the effect of the semiconductor device of explanation the first execution mode.
Fig. 3 is the constructed profile that represents the structure of the semiconductor device of the second execution mode.
Fig. 4 is the constructed profile that represents the structure of the semiconductor device of the 3rd execution mode.
Fig. 5 is the constructed profile that represents the structure of the semiconductor device of the 4th execution mode.
Fig. 6 is the constructed profile that represents the structure of the semiconductor device of the 5th execution mode.
Fig. 7 is the constructed profile that represents the structure of the semiconductor device of the 6th execution mode.
Claims (20)
1. a semiconductor device, is characterized in that,
Possess:
The first semiconductor layer, is made up of the first nitride-based semiconductor;
The second semiconductor layer, is formed on above-mentioned the first semiconductor layer, is made up of the second nitride-based semiconductor that band gap is large compared with above-mentioned the first nitride-based semiconductor;
Source electrode, is formed on above-mentioned the second semiconductor layer;
Drain electrode, is formed on above-mentioned the second semiconductor layer;
First grid electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned source electrode and above-mentioned drain electrode, carries out Schottky engage with above-mentioned the second semiconductor layer;
Second grid electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned source electrode and above-mentioned first grid electrode across dielectric film, is electrically connected with above-mentioned first grid electrode; And
The 3rd gate electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned drain electrode and above-mentioned first grid electrode across dielectric film, is electrically connected with above-mentioned first grid electrode.
2. the semiconductor device of recording as claim 1, is characterized in that,
Above-mentioned first threshold is higher than above-mentioned Second Threshold and the 3rd threshold value.
3. the semiconductor device of recording as claim 1, is characterized in that,
The thickness of above-mentioned the second semiconductor layer under above-mentioned second grid electrode and above-mentioned the 3rd gate electrode is thinner than the thickness of above-mentioned the second semiconductor layer under above-mentioned first grid electrode.
4. the semiconductor device of recording as claim 1, is characterized in that,
In above-mentioned the second semiconductor layer under above-mentioned second grid electrode and above-mentioned the 3rd gate electrode, possesses the semiconductor regions that contains fluorine or chlorine.
5. the semiconductor device of recording as claim 1, is characterized in that,
Above-mentioned Second Threshold and the 3rd threshold value are higher than the voltage in the time ending, above-mentioned first grid electrode, second grid electrode and the 3rd gate electrode being applied.
6. the semiconductor device of recording as claim 1, is characterized in that,
Above-mentioned Second Threshold and the 3rd threshold value, be less than or equal to 1V with the absolute value of the difference of above-mentioned first threshold.
7. the semiconductor device of recording as claim 1, is characterized in that,
The grid length of above-mentioned second grid electrode and the 3rd gate electrode is longer than the grid of above-mentioned first grid electrode.
8. the semiconductor device of recording as claim 1, is characterized in that,
Above-mentioned the first nitride-based semiconductor is Al
xga
1-Xn, wherein 0≤X≤1, above-mentioned the second nitride-based semiconductor is Al
yga
1-Yn, wherein 0 < Y≤1, X < Y.
9. the semiconductor device of recording as claim 1, is characterized in that,
Above-mentioned dielectric film is silicon nitride film.
10. the semiconductor device of recording as claim 1, is characterized in that,
Between above-mentioned source electrode and above-mentioned the second semiconductor layer and be ohmic contact between above-mentioned drain electrode and above-mentioned the second semiconductor layer.
11. 1 kinds of semiconductor devices, is characterized in that,
Possess:
The first semiconductor layer, is made up of the first nitride-based semiconductor;
The second semiconductor layer, is formed on above-mentioned the first semiconductor layer, is made up of the second nitride-based semiconductor that band gap is large compared with above-mentioned the first nitride-based semiconductor;
Source electrode, is formed on above-mentioned the second semiconductor layer;
Drain electrode, is formed on above-mentioned the second semiconductor layer;
First grid electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned source electrode and above-mentioned drain electrode, is the 3rd nitride-based semiconductor of p-type and the lit-par-lit structure of metal;
Second grid electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned source electrode and above-mentioned first grid electrode across dielectric film, is electrically connected with above-mentioned first grid electrode; And
The 3rd gate electrode, is formed on above-mentioned the second semiconductor layer between above-mentioned drain electrode and above-mentioned first grid electrode across dielectric film, is electrically connected with above-mentioned first grid electrode.
12. semiconductor devices of recording as claim 11, is characterized in that,
Above-mentioned first threshold is higher than above-mentioned Second Threshold and the 3rd threshold value.
13. as the semiconductor device of claim 9 or 11 records, it is characterized in that,
The thickness of above-mentioned the second semiconductor layer under above-mentioned second grid electrode and above-mentioned the 3rd gate electrode is thinner than the thickness of above-mentioned the second semiconductor layer under above-mentioned first grid electrode.
14. semiconductor devices of recording as claim 11, is characterized in that,
In above-mentioned the second semiconductor layer under above-mentioned second grid electrode and above-mentioned the 3rd gate electrode, possesses the semiconductor regions that contains fluorine or chlorine.
15. semiconductor devices of recording as claim 12, is characterized in that,
Above-mentioned Second Threshold and the 3rd threshold value are higher than the voltage in the time ending, above-mentioned first grid electrode, second grid electrode and the 3rd gate electrode being applied.
16. semiconductor devices of recording as claim 12, is characterized in that,
Above-mentioned Second Threshold and the 3rd threshold value, be less than or equal to 1V with the absolute value of the difference of above-mentioned first threshold.
17. semiconductor devices of recording as claim 11, is characterized in that,
The grid length of above-mentioned second grid electrode and the 3rd gate electrode is longer than the grid of above-mentioned first grid electrode.
18. semiconductor devices of recording as claim 11, is characterized in that,
Above-mentioned the first nitride-based semiconductor is Al
xga
1-Xn, wherein 0≤X≤1, above-mentioned the second nitride-based semiconductor is Al
yga
1-Yn, wherein 0 < Y≤1, X < Y, above-mentioned the 3rd nitride-based semiconductor is Al
zga
1-Zn, wherein 0≤Z≤1.
19. semiconductor devices of recording as claim 11, is characterized in that,
Above-mentioned dielectric film is silicon nitride film.
20. semiconductor devices of recording as claim 11, is characterized in that,
Between above-mentioned source electrode and above-mentioned the second semiconductor layer and be ohmic contact between above-mentioned drain electrode and above-mentioned the second semiconductor layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107393954A (en) * | 2017-08-02 | 2017-11-24 | 电子科技大学 | A kind of GaN hetero-junctions vertical field effect pipe |
| CN109461655A (en) * | 2018-09-21 | 2019-03-12 | 中国电子科技集团公司第五十五研究所 | Nitride high electronic migration rate transistor fabrication process with multi-gate structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP6646363B2 (en) * | 2015-06-02 | 2020-02-14 | 株式会社アドバンテスト | Semiconductor device |
| US10276681B2 (en) | 2016-02-29 | 2019-04-30 | Infineon Technologies Austria Ag | Double gate transistor device and method of operating |
| US10530360B2 (en) | 2016-02-29 | 2020-01-07 | Infineon Technologies Austria Ag | Double gate transistor device and method of operating |
| JP7021034B2 (en) * | 2018-09-18 | 2022-02-16 | 株式会社東芝 | Semiconductor device |
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| US20070102727A1 (en) * | 2005-11-02 | 2007-05-10 | Sharp Kabushiki Kaisha | Field-effect transistor |
| CN101789445A (en) * | 2008-12-22 | 2010-07-28 | 三垦电气株式会社 | Semiconductor device |
| CN102201441A (en) * | 2010-03-26 | 2011-09-28 | 三垦电气株式会社 | Semiconductor device |
| JP2012028705A (en) * | 2010-07-27 | 2012-02-09 | Sumitomo Electric Ind Ltd | Semiconductor device |
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2013
- 2013-03-22 JP JP2013059337A patent/JP2014187085A/en not_active Abandoned
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|---|---|---|---|---|
| US20070102727A1 (en) * | 2005-11-02 | 2007-05-10 | Sharp Kabushiki Kaisha | Field-effect transistor |
| CN101789445A (en) * | 2008-12-22 | 2010-07-28 | 三垦电气株式会社 | Semiconductor device |
| CN102201441A (en) * | 2010-03-26 | 2011-09-28 | 三垦电气株式会社 | Semiconductor device |
| JP2012028705A (en) * | 2010-07-27 | 2012-02-09 | Sumitomo Electric Ind Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107393954A (en) * | 2017-08-02 | 2017-11-24 | 电子科技大学 | A kind of GaN hetero-junctions vertical field effect pipe |
| CN107393954B (en) * | 2017-08-02 | 2019-11-01 | 电子科技大学 | A kind of GaN hetero-junctions vertical field effect pipe |
| CN109461655A (en) * | 2018-09-21 | 2019-03-12 | 中国电子科技集团公司第五十五研究所 | Nitride high electronic migration rate transistor fabrication process with multi-gate structure |
| CN109461655B (en) * | 2018-09-21 | 2022-03-11 | 中国电子科技集团公司第五十五研究所 | Method for manufacturing nitride high electron mobility transistor with multi-gate structure |
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