CN102623498A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN102623498A
CN102623498A CN2011102411974A CN201110241197A CN102623498A CN 102623498 A CN102623498 A CN 102623498A CN 2011102411974 A CN2011102411974 A CN 2011102411974A CN 201110241197 A CN201110241197 A CN 201110241197A CN 102623498 A CN102623498 A CN 102623498A
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semiconductor layer
layer
semiconductor device
semiconductor element
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斋藤涉
藤本英俊
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Abstract

According to one embodiment, the semiconductor element includes a first semiconductor layer. The first semiconductor layer contains AlXGa1-XN. A top layer of the first semiconductor layer is terminated by nitrogen. The semiconductor element includes a second semiconductor layer containing non-doped or first conductivity-type AlYGa1-YN formed on the first semiconductor layer. The semiconductor element includes a third semiconductor layer containing AlZGa1-ZN formed on the second semiconductor layer. The semiconductor element includes a first major electrode connected to the third semiconductor layer. The semiconductor element includes a second major electrode connected to the third semiconductor layer. The semiconductor element includes a gate electrode provided on the third semiconductor layer between the first major electrode and the second major electrode.

Description

Semiconductor element
The cross reference of related application
The application is based on the No.2011-014502 of Japanese patent application formerly that submitted on January 26th, 2011 and require its priority of enjoyment, and its full content is quoted into the present invention.
Technical field
This execution mode relates to semiconductor element.
Background technology
In the circuit of Switching Power Supply, converter etc., use the power semiconductor of switch element, diode etc.Such power semiconductor is asked to high withstand voltage low on-resistanceization.There is contradiction (trade-off) relation between component pressure and the conducting resistance by the element material decision.This contradictory relation can be used for improving through wide bandgap semiconductor is made as the switch element material.
Wherein, as the element that becomes low on-resistance easily, for example there is HFET (HFET) with aluminium gallium nitride alloy (AlGaN)/heterogeneous structure of gallium nitride (GaN).In HFET,, realize low on-resistanceization through the high degree of excursion of heterogeneous interface raceway groove and the high electron concentration that produces through piezoelectric polarization.
But owing in HFET, produce electronics (2 dimension electron cloud) through piezoelectric polarization, therefore usually, threshold voltage of the grid is for negative.Therefore, HFET is normal conducting (normally on).In the power electronic device purposes of Switching Power Supply etc., the secure context of the impulse current when preventing energized etc. considers that threshold voltage of the grid just is preferably.That is, in the purposes of power electronic device, the normal action by (normally off) is absolutely necessary.
For HFET is often ended, the means of introducing the means of p type GaN layer, the means of introducing recess gate (recess gate) structure, introducing MOS type raceway groove structure at the gate electrode downside are arranged.But control, cup depth control for the impurity concentration of p type GaN layer need the complex processing technology.Therefore, in the HFET of reality, threshold voltage of the grid (Vth) is easy to generate deviation.In addition, in MOS type raceway groove structure, though the deviation of threshold voltage of the grid is inhibited, become the structure that forms inversion channel in the MIS gate interface, degree of excursion is low, and conducting resistance increases.
Summary of the invention
Execution mode of the present invention provide conducting resistance low, often carry out by action, semiconductor element that reliability is high.
According to execution mode, semiconductor element possesses: the 1st semiconductor layer, the N face is grown up on supporting substrates, comprises Al XGa 1-XN (0≤X＜1); The 2nd semiconductor layer is formed on above-mentioned the 1st semiconductor layer, comprises the Al of non-impurity-doped or the 1st conductivity type YGa 1-YN (0＜Y≤1, X＜Y); And the 3rd semiconductor layer, be formed on above-mentioned the 2nd semiconductor layer, comprise Al ZGa 1-ZN (0≤Z＜1, Z＜Y).The gate electrode that the semiconductor element of execution mode possesses the 1st main electrode that is connected with above-mentioned the 3rd semiconductor layer, the 2nd main electrode that is connected with above-mentioned the 3rd semiconductor layer and on above-mentioned the 3rd semiconductor layer between above-mentioned the 1st main electrode and above-mentioned the 2nd main electrode, is provided with.The thickness of above-mentioned the 3rd semiconductor layer is optionally attenuation under above-mentioned gate electrode.
According to the embodiment of the present invention, can provide conducting resistance low, carry out normal turn-on action, semiconductor element that reliability is high.
Description of drawings
Fig. 1 is the major part sketch map of the nitride semiconductor device of the 1st execution mode, and Fig. 1 (a) is the major part schematic cross-section, and Fig. 1 (b) is the major part schematic top plan view.
Fig. 2 is the major part schematic cross-section of the nitride semiconductor device of reference example.
Fig. 3 is the major part schematic cross-section of nitride semiconductor device of the 1st variation of the 1st execution mode.
Fig. 4 is the major part schematic cross-section of nitride semiconductor device of the 2nd variation of the 1st execution mode.
Fig. 5 is the major part schematic cross-section of the nitride semiconductor device of the 2nd execution mode.
Fig. 6 is the major part schematic cross-section of nitride semiconductor device of the 1st variation of the 2nd execution mode.
Fig. 7 is the major part schematic cross-section of nitride semiconductor device of the 2nd variation of the 2nd execution mode.
Fig. 8 is the major part schematic cross-section of the nitride semiconductor device of the 3rd execution mode.
Embodiment
Below, with reference to the description of drawings execution mode.Below shown in figure in, given identical symbol to identical inscape.
(the 1st execution mode)
Fig. 1 is the major part sketch map of the nitride semiconductor device of the 1st execution mode, and Fig. 1 (a) is the major part schematic cross-section, and Fig. 1 (b) is the major part schematic top plan view.X-X ' the cross section of Fig. 1 (b) has been shown among Fig. 1 (a).
In nitride semiconductor device 1A, on supporting substrates 10, range upon range of have a plurality of semiconductor crystal layers.Each semiconductor crystal layer is N face (nitrogen face) grown layer.That is, the upper surface of each semiconductor crystal layer is the face that ends at the N face.Each semiconductor crystal layer for example forms through epitaxial growth method.
Supporting substrates 10 for example is carborundum (SiC) substrate.On supporting substrates 10, be provided with resilient coating 11.Resilient coating 11 for example has two-layer semiconductor layer.For example, resilient coating 11 has aluminum nitride buffer layer (AlN resilient coating) 11a that contacts with supporting substrates 10 and is arranged on gallium nitride resilient coating (GaN resilient coating) 11b on the AlN resilient coating 11a.The upper surface of the upper surface of AlN resilient coating 11a and GaN resilient coating 11b is the face that ends at the N face.In execution mode, will comprise that the semiconductor layer of resilient coating 11 is made as the 1st semiconductor layer.The composition of the 1st semiconductor layer is Al XGa 1-XN (0≤X＜1).
In nitride semiconductor device 1A, on resilient coating 11, be provided with non-impurity-doped or n type and stop (barrier) layer 15.In this manual, for example, the n type is made as the 1st conductivity type, the p type is made as the 2nd conductivity type.Barrier layer 15 for example is aluminium gallium nitride alloy barrier layer (AlGaN barrier layer).Barrier layer 15 is N face grown layers.That is, the upper surface on barrier layer 15 is the face that ends at the N face.In execution mode, will comprise that the semiconductor layer on barrier layer 15 is made as the 2nd semiconductor layer.The composition of the 2nd semiconductor layer is Al YGa 1-YN (0＜Y≤1, X＜Y).
On barrier layer 15, be provided with undoped channel layer 16.Channel layer 16 for example is gallium nitride channel layer (a GaN channel layer).Channel layer 16 is N face grown layers.That is, the upper surface of channel layer 16 is the face that ends at the N face.In execution mode, will comprise that the semiconductor layer of channel layer 16 is made as the 3rd semiconductor layer.The 3rd semiconductor layer also can comprise aluminium (Al).The composition of the 3rd semiconductor layer is Al ZGa 1- ZN (0≤Z＜1, Z＜Y).Except after the thickness of channel layer 16 the depressed part 16r that states for example be about 10 times of thickness on barrier layer 15.The thickness on barrier layer 15 for example is 30nm.But the thickness on barrier layer 15 is not limited to these values with the ratio of the thickness of channel layer 16 and the thickness on barrier layer 15.
Channel layer 16 is connected with source electrode 20 as the 1st main electrode.Channel layer 16 is connected with drain electrode 21 as the 2nd main electrode.On channel layer 16, be provided with gate insulating film 30.Between source electrode 20 and drain electrode 21, be provided with gate electrode 31 across gate insulating film 30.That is, gate insulating film 30 is arranged between gate electrode 31 and the channel layer 16.Source electrode 20, drain electrode 21 and gate electrode 31 are seen from the direction vertical with the interarea of supporting substrates 10, are extended with strip.
As the material of gate electrode 31, select the little material of work function.For example, as the material of gate electrode 31, select platinum (Pt), palladium (Pd) etc.But the material of gate electrode 31 is not limited to these materials.
In nitride semiconductor device 1A, the thickness of channel layer 16 is in 31 times optionally attenuation of gate electrode.For example, the channel layer 16 under the gate electrode 31 is sagged to barrier layer 15 sides.That is, in the channel layer 16 under gate electrode 31, be provided with depressed part 16r, this depressed part 16 comprises than the low bottom surface 16b of the upper surface 16a of channel layer 16 and the side 16w of taper.Gate electrode 31 further extends to the bottom surface 16b side of depressed part 16r from the upper surface 16a of channel layer 16.Between bottom surface 16b and side 16w and gate electrode 31, clip grid oxidation film 30.
Each semiconductor crystal layer of nitride semiconductor device 1A forms through the growth process (process) that the N face is exposed at upper surface side outward.Therefore, the electronics 1e that produces through piezoelectric polarization produces on the heterogeneous interface between barrier layer 15 and the channel layer 16, rather than on the heterogeneous interface between resilient coating 11 and the barrier layer 15, produces.For example, the heterogeneous interface raceway groove produces in gate insulating film 30 sides.Through being made as such structure, in nitride semiconductor device 1A, handle deviation and diminish, become low on-resistance, and realize normal by action.
Here for relatively, in Fig. 2, represent the nitride semiconductor device 100 of example as a reference.
Fig. 2 is the major part schematic cross-section of the nitride semiconductor device of reference example.
In nitride semiconductor device shown in Figure 2 100, on supporting substrates 10, be provided with resilient coating 110.For example, on supporting substrates 10, be provided with aluminum nitride buffer layer 110a.On aluminum nitride buffer layer 110a, be provided with gallium nitride resilient coating 110b.
The upper surface of the upper surface of AlN resilient coating 110a and GaN resilient coating 110b is for ending at the face of gallium (Ga) face.On resilient coating 11, be provided with undoped channel layer (GaN channel layer) 160.On channel layer 160, be provided with the barrier layer (AlGaN barrier layer) 150 of non-impurity-doped or n type.The thickness on barrier layer 150 be channel layer 160 thickness about 1/10.For example, the thickness that the barrier layer 150 of depressed part 150r is not set is 30nm.The upper surface of the upper surface on barrier layer 150 and channel layer 160 is the face that ends at the gallium face.That is, each semiconductor crystal layer of nitride semiconductor device 100 is formed on the supporting substrates 10 through the growth process that the gallium face is exposed at upper surface side outward.
In nitride semiconductor device 100, the heterogeneous interface of electronics 100e between barrier layer 150 and channel layer 160 that produces through piezoelectric polarization produces.The heterogeneous interface raceway groove is formed on resilient coating 110 sides.In this nitride semiconductor device 100, normal in order to realize by action, adopted the means of thinning barrier layer 150.For example, the barrier layer under gate electrode 31 150 is provided with depressed part 150r.
But the thickness of the Film Thickness Ratio channel layer 160 on barrier layer 150 is thin, and the technology that original thin 150 further attenuation ground, barrier layer are controlled is complicated.For example, need be several nanoscales (for example, about 5nm) with the THICKNESS CONTROL on the barrier layer 150 of the bottom of depressed part 150r.
In addition; In the nitride semiconductor device 100; If under cut-off state, between source electrode 20 and drain electrode 21, apply high voltage, then the electronics 100e in the heterogeneous interface raceway groove might be captured (trap) to the interface (passivation interface) between grid oxidation film 30 and the barrier layer 150.
For example, if under cut-off state, between source electrode 20 and drain electrode 21, apply high voltage, cause in the end of gate electrode 31 that then electric field is concentrated.The electronics that is quickened by high electric field leaps to the grid oxidation film 30 as passivating film via barrier layer 150, and might become trapped in the interface between grid oxidation film 30 and the barrier layer 150.In a single day electronics become trapped in passivation interface, even then electronics is in conducting state or applies the state that voltage descended at nitride semiconductor device 100 and also is difficult for being released.Therefore, through the electronics that is captured, the heterogeneous interface raceway groove is exhausted by part property ground, and conducting resistance might increase (generation of current collapse phenomenon).
In addition, in nitride semiconductor device 100, the electronics that is quickened by high electric field leaps in the grid oxidation film 30, so grid oxidation film 30 might produce defective.Thus, in nitride semiconductor device 100, might flutter and cause that reliability worsens.
In addition, as realizing normal other means, the means that on the barrier layer under the gate electrode 31 150, form p type GaN layer are arranged by action.But the processing of the impurity concentration of control p type GaN layer is complicated.
With respect to this, each semiconductor crystal layer of nitride semiconductor device 1A shown in Figure 1 is a N face grown layer.Therefore, the heterogeneous interface of electronics 1e between barrier layer 15 and channel layer 16 that produces through piezoelectric polarization produces.And under cut-off state, for gate electrode is exhausted for 31 times, optionally the channel layer 16 under the attenuate gate electrode 31 uses the little material of work function to gate electrode 31.
For example, through the channel layer 16 under the attenuate gate electrode 31 optionally, thus the piezoelectric polarization optionally under the suppressor grid electrode 31, and optionally reduce the electron concentration of the heterogeneous interface raceway groove under the gate electrode 31.The thickness of channel layer 16 is than the thicker on barrier layer 15.Therefore, when forming depressed part 16r, do not require accuracy about the control of etch depth.And, being made as the little material of work function through material with gate electrode 31, the flat band voltage according to the work function difference by gate electrode 31 and channel layer 16 produces exhausts for 31 times gate electrode under cut-off state more easily.Thus, in nitride semiconductor device 1A, realize normal by action.
And then, in nitride semiconductor device 1A, need not form the processing of above-mentioned p type GaN layer.That is the complex processing that, need not control the impurity concentration of p type GaN layer.
Therefore, in nitride semiconductor device 1A, the deviation of threshold voltage of the grid (Vth) reduces.
In addition, nitride semiconductor device 1A is not a MOS type raceway groove structure.For example; HFET as hybird architecture with MOS type raceway groove; Following structure is arranged: only grid part is removed the AlGaN barrier layer, as MOS raceway groove structure, forms the AlGaN barrier layer in displacement zone (between gate electrode and the source electrode and between gate electrode and the drain electrode).Among the HFET of this MOS type raceway groove structure,, make between source electrode and the drain electrode and switch on through being formed on the inversion channel under the gate electrode.
On the other hand, the nitride semiconductor device 1A of execution mode does not form inversion channel under conducting state.That is, in nitride semiconductor device 1A, under gate electrode 31, do not form inversion channel, but form the heterogeneous interface raceway groove.Therefore, in nitride semiconductor device 1A, the raceway groove degree of excursion is high, realizes low on-resistance.
In addition, in nitride semiconductor device 1A, the thickness of channel layer 16 is than the thicker on barrier layer 15.Therefore, gate insulating film 30 spatially separates through channel layer 16 with heterogeneous interface.Therefore, in nitride semiconductor device 1A, above-mentioned current collapse phenomenon is inhibited, and conducting resistance increases, and is difficult for causing that reliability worsens.
Like this, nitride semiconductor device 1A has low on-resistance, carries out often ending action, and has high reliability.
Then, the variation to nitride semiconductor device 1A describes.Below each semiconductor crystal layer of the nitride semiconductor device of explanation is a N face grown layer.
(the 1st variation of the 1st execution mode)
Fig. 3 is that the major part cross section of nitride semiconductor device of the 1st variation of the 1st execution mode is not intended to.
In nitride semiconductor device 1B, the thickness of channel layer 16 is in source electrode 20 times and 21 times optionally attenuation of drain electrode.That is, the channel layer under source electrode 20 16 is provided with groove (trench) 16ta.In groove 16ta, be provided with source electrode 20.In nitride semiconductor device 1B, the channel layer 16 under drain electrode 21 is provided with groove 16tb.In groove 16tb, be provided with drain electrode 21.That is, source electrode 20 and drain electrode 21 are formed with the groove contact for channel layer 16.
Thus, the space length to channel layer 16 of source electrode 20 and drain electrode 21 shortens.As a result, the Ohmic resistance to channel layer 16 of source electrode 20 and drain electrode 21 reduces.That is, in nitride semiconductor device 1B, 1A compares with nitride semiconductor device, and conducting resistance further reduces.
(the 2nd variation of the 1st execution mode)
Fig. 4 is the major part schematic cross-section of nitride semiconductor device of the 2nd variation of the 1st execution mode.
In nitride semiconductor device 1C, be the p type as the conductivity type of at least a portion on the barrier layer 11 of the 1st semiconductor layer, perhaps, the resistivity of at least a portion on barrier layer 11 is higher than the resistivity of channel layer 16.
For example, in nitride semiconductor device 1C, between resilient coating 11a and barrier layer 15, be provided with the resilient coating 11p of p type.Resilient coating 11p comprises Al UGa 1-UN (0≤U≤1).
Through resilient coating 11p is arranged on the barrier layer 15 times, in nitride semiconductor device 1C, 1A compares with nitride semiconductor device, and the current potential of resilient coating 11p rises.Thus, even between source electrode 20 and drain electrode 21, apply high voltage, electronics also is difficult to flow to resilient coating 11p, suppressed to be arranged on channel layer 16 under resilient coating in the leakage current that flows through.
In addition, in nitride semiconductor device 1C, through the resilient coating 11p of p type being set, clamping barrier layer 15, the current potential rising at the interface between barrier layer 15 and the channel layer 16.Thus, further promote exhausting under the gate electrode 31.That is, in nitride semiconductor device 1C, 1A compares with nitride semiconductor device, and threshold voltage of the grid is more to moving on the occasion of (plus) lateral deviation.As a result, in nitride semiconductor device 1C, realize more reliably often ending.
Between resilient coating 11a and barrier layer 15, except the resilient coating 11p that the p type is set, also resilient coating 11b likewise is set with nitride semiconductor device 1A, can doping carbon (C) among this resilient coating 11b, iron (Fe) etc.Thus, the resistivity of resilient coating 11b (Ω cm) is higher than the resistivity of channel layer 16, even between source electrode 20 and drain electrode 21, apply high voltage, in resilient coating 11b, also is difficult for flowing through leakage current.Like this, high-resistance resilient coating 11b is set in nitride semiconductor device 1C.
(the 2nd execution mode)
Fig. 5 is the major part schematic cross-section of the nitride semiconductor device of the 2nd execution mode.
In nitride semiconductor device 2A, be formed with p type GaN layer 40a on the surface of channel layer 16.That is, between channel layer 16 and gate insulating film 30, be provided with p type GaN layer 40a.P type GaN layer 40a comprises Al UGa 1-UThe 4th semiconductor layer of N (0≤U≤1).Because on channel layer 16, be provided with p type GaN layer 40a, so the rising of the current potential of heterogeneous interface raceway groove, the raceway groove under the gate electrode 31 is easy to exhaust.Thus, in nitride semiconductor device 2A, 1A compares with nitride semiconductor device, and threshold voltage of the grid is more to moving on the occasion of lateral deviation.As a result, in nitride semiconductor device 2A, realize more reliably often ending.
P type GaN layer 40a is arranged on the undoped channel layer 16, so the alloy among the p type GaN layer 40a is difficult to spread to channel layer 16 sides.Thus, the controlled of impurity concentration of p type GaN layer 40a uprises.In addition, the heterogeneous interface of nitride semiconductor device 2A is undoped, so the raceway groove degree of excursion is high, keeps low on-resistance.
In addition, in nitride semiconductor device 2A, the end of p type GaN layer 40a is connected with source electrode 20.On the channel layer 16 between p type GaN layer 40a and the drain electrode 21, be provided with gate insulating film 30.Thus, the hole that produces through avalanche breakdown is discharged to source electrode 20 rapidly via p type GaN layer 40a.As a result, nitride semiconductor device 2A has high avalanche capability.
In nitride semiconductor device 2A, replace p type GaN layer 40a and p type InGaN layer or other p type semiconductor layer be arranged between channel layer 16 and the gate insulating film 30 also obtain identical effect.Except p type GaN layer 40a, p type InGaN layer, other p type semiconductor layer except the single crystal growing layer, also can be polycrystal layer, uncrystalline layer.Chemical vapour deposition (CVD)) etc. for example (Chemical Vapor Deposition: decompression method of piling forms through CVD for polycrystal layer, uncrystalline layer.
(the 1st variation of the 2nd execution mode)
Fig. 6 is the major part schematic cross-section of nitride semiconductor device of the 1st variation of the 2nd execution mode.
In nitride semiconductor device 2B, be formed with p type GaN layer 40b on the surface of channel layer 16.That is, between channel layer 16 and gate insulating film 30, be provided with p type GaN layer 40b.The composition of p type GaN layer 40b is identical with above-mentioned p type GaN layer 40a.P type GaN layer 40b do not cover the entire upper surface of channel layer 16.P type GaN layer 40b optionally is arranged on gate electrode 31 times.P type GaN layer 40b also can optionally be arranged on the bottom surface 16b of depressed part 16r.
Because on the channel layer under the gate electrode 31 16, be provided with p type GaN layer 40b, so the rising of the current potential of the heterogeneous interface raceway groove under the gate electrode 31, the raceway groove under the gate electrode 31 is easy to exhaust.Thus, in nitride semiconductor device 2B, 1A compares with nitride semiconductor device, and threshold voltage of the grid is more to moving on the occasion of lateral deviation.As a result, in nitride semiconductor device 2B, realize more reliably often ending.
(the 2nd variation of the 2nd execution mode)
Fig. 7 is the major part schematic cross-section of nitride semiconductor device of the 2nd variation of the 2nd execution mode.
In nitride semiconductor device 2C, above-mentioned grid oxidation film 30 is not set.On the surface of channel layer 16, be formed with p type GaN layer 40b.That is, in nitride semiconductor device 2C, p type GaN layer 40b optionally is arranged on the bottom surface 16b of depressed part 16r.P type GaN layer 40b do not cover the entire upper surface of channel layer 16.And gate electrode 32 is connected with p type GaN layer 40b.Gate electrode 32 does not contact with channel layer 16.
Because the surface of the channel layer 16 under gate electrode 32 is provided with p type GaN layer 40b, so the rising of the current potential of the heterogeneous interface raceway groove under the gate electrode 32, the raceway groove under the gate electrode 32 is easy to exhaust.Thus, in nitride semiconductor device 2C, 1A compares with nitride semiconductor device, and threshold voltage of the grid is more to moving on the occasion of lateral deviation.As a result, in nitride semiconductor device 2C, realize more reliably often ending.
(the 3rd execution mode)
Fig. 8 is the major part schematic cross-section of the nitride semiconductor device of the 3rd execution mode.
In nitride semiconductor device 3, the thickness on barrier layer 15 is in 31 times optionally attenuation of gate electrode.Barrier layer 15 under gate electrode 31 is provided with depressed part 15r, and this depressed part 15r comprises than the low bottom surface 15b of the upper surface 15a on this barrier layer 15 and the side 15w of taper.Channel layer 16 extends in depressed part 15r.
In nitride semiconductor device 3, the thickness attenuation on the barrier layer 15 under the gate electrode 31, therefore gate electrode 31 times, the electron number that produces through piezoelectric polarization reduces.Thus, in nitride semiconductor device 3,1A compares with nitride semiconductor device, and threshold voltage of the grid is more to moving on the occasion of lateral deviation.As a result, in nitride semiconductor device 3, realize more reliably often ending.
More than, nitride semiconductor device has been described.Execution mode is not limited to above-mentioned execution mode, in the scope of the purport that does not break away from execution mode, can carry out various distortion and implement.
The combination of barrier layer 15/ channel layer 16 that for example, on supporting substrates 10, is provided with also can be GaN layer/InGaN layer, AlN layer/AlGaN layer, InAlN layer/GaN layer.
In addition, as supporting substrates 10, except the SiC substrate, can also use sapphire substrate, silicon (Si) substrate, GaN substrate etc.Do not rely on the kind of supporting substrates 10, no matter be that conductivity or insulating properties all can be through making N long enforcement of looking unfamiliar.In addition, supporting substrates 10 both can be the substrate that is used to make each semiconductor crystal layer growth, also can be to make each semiconductor crystal layer growth paste the substrate of AlN resilient coating 11a afterwards.
In this manual, the N face grown layer of each semiconductor crystal layer can be replaced into (0,0,0 ,-1) face of GaN crystallization.In addition, also can p type GaN layer 40b and source electrode 20 be connected up through the outside and be electrically connected.Thus, the hole that produces through avalanche breakdown is discharged to source electrode 20 rapidly via p type GaN layer 40b.As a result, nitride semiconductor device 2B has high avalanche capability.
In this manual, " nitride-based semiconductor " comprises chemical formula B xIN yAl zGa 1-x-y-zThe semiconductor of all compositions that among the N (0≤x≤1,0≤y≤1,0≤z≤1, x+y+z≤1) ratio of components x, y and z changed in scope separately.In addition; Below composition also be contained in " nitride-based semiconductor ", that is: also be included in addition V group element of N in the above-mentioned chemical formula (nitrogen), also comprise various elements that add in order to control various rerum naturas such as conductivity type and also comprise the various elements that by mistake comprise.
More than, with reference to concrete example execution mode of the present invention has been described.But the present invention is not limited to these concrete examples.That is,, then be contained in scope of the present invention as long as those skilled in the art possess characteristic of the present invention to the structure that these concrete examples have added suitable change design.Each key element that above-mentioned each concrete example possessed and configuration thereof, material, condition, shape, size etc. are not limited to illustrative content, can suitably change.
In addition, as long as each key element that above-mentioned each execution mode possessed then can make up art recognized, comprises characteristic of the present invention and then is contained in scope of the present invention as long as make up these structure.
In addition, in thought category of the present invention, those skilled in the art can expect various change examples and modification, are interpreted as these change examples and revise example also belonging to scope of the present invention.
Several embodiments of the present invention has been described, these execution modes are for example, do not limit scope of invention.These new execution modes can be implemented with other variety of ways, in the scope of the purport that does not break away from invention, can carry out various omissions, displacement, change.These execution modes and distortion thereof are contained in scope of invention and purport, and are contained in record invention and equivalent scope thereof in claims.

Claims (20)

1. semiconductor element is characterized in that possessing:
The 1st semiconductor layer, the N length of looking unfamiliar comprises Al on supporting substrates XGa 1-XN, wherein 0≤X＜1;
The 2nd semiconductor layer is formed on above-mentioned the 1st semiconductor layer, comprises the Al of non-impurity-doped or the 1st conductivity type YGa 1-YN, 0＜Y≤1 wherein, X＜Y,
The 3rd semiconductor layer is formed on above-mentioned the 2nd semiconductor layer, comprises Al ZGa 1-ZN, 0≤Z＜1 wherein, Z＜Y;
The 1st main electrode is connected with above-mentioned the 3rd semiconductor layer;
The 2nd main electrode is connected with above-mentioned the 3rd semiconductor layer; And
Gate electrode is arranged on above-mentioned the 3rd semiconductor layer between above-mentioned the 1st main electrode and above-mentioned the 2nd main electrode;
The thickness of above-mentioned the 3rd semiconductor layer is optionally attenuation under above-mentioned gate electrode.
2. semiconductor element as claimed in claim 1 is characterized in that,
Between above-mentioned gate electrode and above-mentioned the 3rd semiconductor layer, also possesses gate insulating film.
3. semiconductor element as claimed in claim 1 is characterized in that,
The thickness of above-mentioned the 3rd semiconductor layer is under above-mentioned the 1st main electrode and optionally attenuation under above-mentioned the 2nd main electrode.
4. semiconductor element as claimed in claim 1 is characterized in that,
Be formed with the 1st groove and the 2nd groove at above-mentioned the 3rd semiconductor layer;
In above-mentioned the 1st groove, be provided with above-mentioned the 1st main electrode, in above-mentioned the 2nd groove, be provided with above-mentioned the 2nd main electrode.
5. semiconductor element as claimed in claim 1 is characterized in that,
The conductivity type of at least a portion of above-mentioned the 1st semiconductor layer is the 2nd conductivity type.
6. semiconductor element as claimed in claim 1 is characterized in that,
Above-mentioned the 1st semiconductor layer has:
Aluminum nitride buffer layer is arranged on the above-mentioned supporting substrates; And
What on above-mentioned aluminum nitride buffer layer, be provided with comprises Al UGa 1-UThe layer of N, wherein 0≤U≤1.
7. semiconductor element as claimed in claim 1 is characterized in that,
The resistivity of at least a portion of above-mentioned the 1st semiconductor layer is higher than the resistivity of above-mentioned the 3rd semiconductor layer.
8. semiconductor element as claimed in claim 6 is characterized in that,
The resistivity of above-mentioned gallium nitride resilient coating is higher than the resistivity of above-mentioned the 3rd semiconductor layer.
9. semiconductor element as claimed in claim 1 is characterized in that,
The 4th semiconductor layer that also possesses the 2nd conductivity type on the surface of above-mentioned the 3rd semiconductor layer.
10. semiconductor element as claimed in claim 9 is characterized in that,
Between above-mentioned gate electrode and above-mentioned the 3rd semiconductor layer, also possesses gate insulating film;
Above-mentioned the 4th semiconductor layer is arranged between above-mentioned the 3rd semiconductor layer and the above-mentioned gate insulating film.
11. semiconductor element as claimed in claim 9 is characterized in that,
Above-mentioned the 4th semiconductor layer comprises Al UGa 1-UN, wherein 0≤U≤1.
12. semiconductor element as claimed in claim 9 is characterized in that,
Above-mentioned the 4th semiconductor layer comprises In YGa 1-YN, wherein 0≤Y≤1.
13. semiconductor element as claimed in claim 9 is characterized in that,
Above-mentioned the 4th semiconductor layer is polycrystal layer or uncrystalline layer.
14. semiconductor element as claimed in claim 9 is characterized in that,
Above-mentioned the 4th semiconductor layer is connected with above-mentioned the 1st main electrode.
15. semiconductor element as claimed in claim 9 is characterized in that,
On above-mentioned the 3rd semiconductor layer between above-mentioned the 4th semiconductor layer and above-mentioned the 2nd main electrode, be provided with gate insulating film.
16. semiconductor element as claimed in claim 9 is characterized in that,
Be formed with the 1st groove and the 2nd groove at above-mentioned the 3rd semiconductor layer;
In above-mentioned the 1st groove, be provided with above-mentioned the 1st main electrode, in above-mentioned the 2nd groove, be provided with above-mentioned the 2nd main electrode.
17. semiconductor element as claimed in claim 9 is characterized in that,
Above-mentioned the 4th semiconductor layer optionally is provided with under above-mentioned gate electrode.
18. semiconductor element as claimed in claim 17 is characterized in that,
Be formed with the 1st groove and the 2nd groove at above-mentioned the 3rd semiconductor layer;
In above-mentioned the 1st groove, be provided with above-mentioned the 1st main electrode, in above-mentioned the 2nd groove, be formed with above-mentioned the 2nd main electrode.
19. semiconductor element as claimed in claim 1 is characterized in that,
The thickness of above-mentioned the 2nd semiconductor layer is optionally attenuation under above-mentioned gate electrode.
20. semiconductor element as claimed in claim 19 is characterized in that,
Be formed with the 1st groove and the 2nd groove at above-mentioned the 3rd semiconductor layer;
In above-mentioned the 1st groove, be provided with above-mentioned the 1st main electrode, in above-mentioned the 2nd groove, be provided with above-mentioned the 2nd main electrode.
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