JP2008244001A - Nitride semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor device such as an HEMT where a gate leakage current is small. <P>SOLUTION: The HEMT has: an electron running layer 4; an electron supply layer 5 arranged on the electron running layer 4; a source electrode 6; a drain electrode 7; a gate electrode 8 in Schottky-contact with the electron supply layer 5; a gate field plate 12; and first and second insulation films 9, 10. The first insulation film 9 is formed of a silicon oxide for generating compression stress, and arranged on the electron supply layer 5. The second insulation film 10 is formed of a silicon oxide for generating compression stress, and arranged on the gate electrode 8, the gate field plate 12, and the first insulation film 9. The first and second insulation films 9, 10 generate compression stress, so that a Schottky barrier in the gate electrode 8 becomes high, thus reducing a gate leakage current. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

The present invention relates to a nitride semiconductor semiconductor field effect transistor (MESFET) using a nitride semiconductor, a high electron mobility transistor (HEMT), and a Schottky barrier diode (SBD). The present invention relates to a physical semiconductor device.

  A typical conventional HEMT includes an electron transit layer made of undoped GaN formed on a substrate such as silicon or sapphire via a buffer layer, and an electron supply layer made of AlGaN doped with n-type impurities or undoped. And a source electrode, a drain electrode, and a gate electrode (Schottky electrode) formed on the electron supply layer. The electron transit layer and the electron supply layer are made of different materials having different band gaps and are heterojunctioned. Therefore, a well-known two-dimensional electron gas layer or 2DEG layer is formed along the heterojunction surface based on one or both of piezoelectric polarization and spontaneous polarization of the electron supply layer. As is well known, the 2DEG layer is used as a current path (channel) between the drain electrode and the source electrode, and the current flowing through the current path is controlled by a bias voltage applied to the gate electrode.

By the way, a HEMT using a nitride semiconductor is excellent in high frequency and high breakdown voltage characteristics. However, as disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-200248 (Patent Document 1), there is a problem of current collapse and a gate leakage current. Have problems. As is well known, current collapse is performed when an HEMT is used in an AC circuit to which an AC voltage having a high voltage amplitude is applied or a circuit in which a high voltage is applied between a source electrode and a drain electrode. Negative charges (electrons) are trapped in the surface states (traps) in this, the electron concentration of the 2DEG layer is reduced due to the negative charges, and the maximum drain current when HEMT is used in an AC circuit is the DC circuit of HEMT. Phenomenon that is lower than the maximum drain current when used in, or when a high voltage is applied between the source electrode and the drain electrode when the HEMT is off, and then the maximum drain current is reduced when the HEMT is turned on It is a phenomenon. Note that the reduction of the maximum drain current of the HEMT means that the resistance value (on resistance) between the source electrode and the drain electrode when the HEMT is on increases.

In order to solve the above-mentioned problems of HEMT, a laminated insulation composed of a SiN film (silicon nitride film) and a SiO ₂ film (silicon oxide film) on which the surface state (trap) is expected to be reduced on the surface of the electron supply layer Patent Document 1 discloses that a film is formed and a gate field plate for relaxing electric field concentration near the gate electrode is provided on the laminated insulating film. In this case, the thickness of the SiN film is relatively thin, for example, 50 nm, and the thickness of the SiO ₂ film is, for example, 150 nm. When the surface of the electron supply layer made of a nitride semiconductor is covered with a SiN film, the surface level of the electron supply layer is reduced, and current collapse is improved. However, the SiN film generates tensile stress (tensile strain), and when this tensile stress is applied to the surface of the electron supply layer, the two-dimensional electron gas generated in the vicinity of the heterojunction between the electron supply layer and the electron transit layer decreases. , The on-resistance between the source electrode and the drain electrode increases.
In addition, when a SiN film is provided as an interlayer insulating film on the gate electrode, the height of the Schottky barrier of the gate electrode is lowered by the tensile stress (tensile strain) of the SiN film, and the gate between the gate electrode and the source electrode is reduced. Leakage current increases. The problem due to the tensile stress of the SiN film is that a source field plate is provided as disclosed in, for example, Japanese Patent Laid-Open No. 2006-86398 (Patent Document 2), and an SiN film is formed as an interlayer insulating film between the gate electrode and the source field plate. This also occurs in a structure provided with a film. That is, when the SiN film is formed on the gate electrode, the tensile stress of the SiN film acts on the gate electrode and the electron supply layer so as to reduce the height of the Schottky barrier of the gate electrode, and the gate electrode and the source electrode The gate leakage current increases.
Note that the problem of gate leakage current also exists in MESFET and SBD.
JP 2004-200248 A JP 2006-86398 A

  An object of the present invention is to provide a nitride semiconductor device capable of reducing gate leakage current.

The present invention for solving the above problems is as follows.
A main semiconductor region including at least one semiconductor layer of nitride semiconductor;
A first electrode in Schottky contact with one main surface of the main semiconductor region;
A second electrode disposed on one main surface of the main semiconductor region and spaced apart from the first electrode and in ohmic contact with one main surface of the main semiconductor region;
A first insulating film that is disposed on at least a portion between the first electrode and the second electrode on one main surface of the main semiconductor region and is formed of silicon oxide;
And a second insulating film disposed on the first electrode and formed of silicon oxide. The nitride semiconductor device includes: a second insulating film;

In addition, as shown in claim 2, the nitride semiconductor device is
A main semiconductor region including at least one semiconductor layer of nitride semiconductor;
A source electrode disposed on one main surface of the main semiconductor region;
A drain electrode disposed apart from the source electrode on one main surface of the main semiconductor region;
A Schottky contact with the main semiconductor region disposed between the source electrode and the drain electrode on one main surface of the main semiconductor region to control a current path between the source electrode and the drain electrode A gate electrode,
A first insulating film that is disposed on at least a portion between the source electrode and the drain electrode on one main surface of the main semiconductor region and is formed of silicon oxide;
It is desirable to include at least a second insulating film disposed on the gate electrode and formed of silicon oxide.
According to a third aspect of the present invention, the first and second insulating films are preferably silicon oxide films formed by plasma CVD.
According to a fourth aspect of the present invention, each of the first and second insulating films preferably has a thickness in the range of 300 to 800 nm.
Further, according to a fifth aspect of the present invention, there is further provided a gate field plate disposed on the first insulating film and electrically connected to the gate electrode between the gate electrode and the drain electrode. Preferably, the second insulating film is also disposed on the gate field plate.
According to a sixth aspect of the present invention, in the nitride semiconductor device according to the first aspect, the Schottky field further disposed on the first insulating film and electrically connected to the first electrode. It is preferable that a second insulating film is provided on the Schottky field plate.
According to a seventh aspect of the present invention, it is desirable to further include a source field plate disposed on the second insulating film and electrically connected to the source electrode.
In addition, as shown in claim 8, further comprising a third insulating film disposed on the second insulating film and formed of silicon nitride or polyimide resin or both of them. It is desirable.
Further, according to a ninth aspect of the present invention, the silicon nitride or the polyimide is disposed on the source field plate and on a portion of the second insulating film where the source field plate is not provided as viewed in plan. It is desirable to have a third insulating film made of resin.
The main semiconductor region may form a two-dimensional carrier gas layer along an interface between the first nitride semiconductor layer and the first nitride semiconductor layer. The second nitride semiconductor layer is preferably heterojunctioned with the first nitride semiconductor layer.
The main semiconductor region may form a two-dimensional carrier gas layer along an interface between the first nitride semiconductor layer and the first nitride semiconductor layer. And the second nitride semiconductor layer heterojunctioned to the first nitride semiconductor layer, and the source electrode and the drain electrode are electrically coupled to the two-dimensional carrier gas layer, respectively. It is desirable. Note that the source electrode and the drain electrode are electrically coupled to the two-dimensional carrier gas layer, respectively, that the source electrode and the drain electrode are directly connected to the two-dimensional carrier gas layer, respectively, or a semiconductor or a conductor. This means that the connection is indirectly made to the two-dimensional carrier gas layer.
The main semiconductor region may further include a spacer layer made of a nitride semiconductor disposed between the first nitride semiconductor layer and the second nitride semiconductor layer. It is desirable to have.

The nitride semiconductor device of the present invention includes a first insulating film formed of silicon oxide on one main surface of a main semiconductor region made of a nitride semiconductor, and a first insulating layer in Schottky contact with the main semiconductor region. And a second insulating film formed of silicon oxide over the first electrode or the gate electrode. The silicon oxide of the second insulating film has a property of generating a compressive stress (for example, 4.00 × 10 ⁹ dyn / cm ² ). In contrast, silicon nitride (SiN) used in conventional nitride semiconductor devices has a property of generating tensile stress (for example, −6.14 × 10 ⁹ dyn / cm ² ). If a second insulating film made of silicon nitride (SiN) is provided in place of the second insulating film made of silicon oxide according to the present invention, the first electrode or the gate electrode is formed based on tensile stress. The height of the Schottky barrier decreases, and the gate leakage current or the diode leakage current increases. On the other hand, when the second insulating film is formed of silicon oxide according to the present invention, the second insulating film generates compressive stress, so that the height of the Schottky barrier of the first electrode or the gate electrode does not decrease. Therefore, according to the present invention, the leakage current flowing in the first electrode or the gate electrode is reduced when the gap between the first electrode and the second electrode or the source electrode and the drain electrode is off. be able to. If the leakage current is reduced, the power loss based on the leakage current of the nitride semiconductor device is also reduced. Note that the second insulating film disposed on the first electrode or the gate electrode functions as a protective film or an interlayer insulating film of the nitride semiconductor device.

  Next, an embodiment of the present invention will be described with reference to FIGS.

The HEMT as the nitride semiconductor device according to the first embodiment of the present invention is composed of a collection of a large number of cells (units HEMT). FIG. 1 shows only a part of the HEMT, that is, one cell. Of course, one HEMT can be configured by only one cell shown in FIG.
The HEMT of FIG. 1 is a kind of field effect transistor, and includes a substrate 1 made of a single crystal silicon semiconductor, a buffer layer 2 formed on the substrate 1, and a first formed on the buffer layer 2. A main semiconductor region 3 including an electron transit layer 4 as a semiconductor layer and an electron supply layer 5 as a second semiconductor layer, and a source electrode 6, a drain electrode 7 and a gate electrode 8 formed on the main semiconductor region 3. And first, second, and third insulating films 9, 10, 11, a gate field plate 12, a source field plate 13, and a back electrode 14 as an auxiliary electrode. Further, in order to electrically connect the source electrode 6, the drain electrode 7, and the gate electrode 8 to an external circuit, the well-known source bonding pad electrode 21, drain bonding pad electrode 22, and gate bonding pad schematically shown in FIG. A plurality of source electrodes 6 are connected to the source bonding pad electrode 21 via the source connection conductor 24; a plurality of drain electrodes 7 are connected to the drain bonding pad electrode 22 via the drain connection conductor 25; The plurality of gate electrodes 8 are connected to the gate bonding pad electrode 23 through the gate connection conductor 26. In FIG. 2, the source connection conductor 24 and the gate connection conductor 26 intersect each other in plan view. However, since the second insulating film 10 made of silicon oxide according to the present invention functions as an interlayer insulating film. Are electrically separated from each other. In FIG. 2, the gate field plate 12 and the source field plate 13 are not shown in order to clarify the relationship among the source electrode 6, the drain electrode 7, and the gate electrode 8.
Next, each part of the HEMT will be described in detail.

  The substrate 1 has one main surface 15 and the other main surface 16 opposite to the main surface 15, and functions as a growth substrate for epitaxially growing the buffer layer 2 and the main semiconductor region 3. It has a function of a support substrate for supporting and a function of a conductive substrate for providing the back electrode 14. In this embodiment, the substrate 1 is made of silicon in order to reduce costs. However, the substrate 1 can also be formed of silicon carbide (SiC) other than silicon, sapphire, ceramic, or the like.

The buffer layer 2 on one main surface 15 of the substrate 1 is formed by an epitaxial growth method such as a well-known MOCVD method. In FIG. 1, the buffer layer 2 is shown as a single layer for the sake of simplicity, but actually, it is formed of a plurality of layers. In other words, the buffer layer 2 has alternating first sublayers (first sublayer) made of AlN (aluminum nitride) and second sublayers (second sublayer) made of GaN (gallium nitride). Is a multi-layered buffer laminated on the substrate. Since the buffer layer 2 is not directly related to the operation of the HEMT, it can be omitted. Further, the semiconductor material of the buffer layer 2 can be replaced with a Group 3-5 compound semiconductor other than AlN and GaN, or a buffer layer having a single layer structure can be formed.

The main semiconductor region 3 is formed on the buffer layer 2 by a known epitaxial growth method such as the MOCVD method. The electron transit layer 4 as the first nitride semiconductor layer in the main semiconductor region 3 is a 2DEG layer 17 (shown by a dotted line) as a current path (channel) in the vicinity of the heterojunction surface with the electron supply layer 5 on the electron transit layer 4. ) And is obtained by epitaxially growing undoped GaN (gallium nitride) to which an impurity is not added to a thickness of, for example, 1 to 10 μm. Note that the electron supply layer 5 is made of, for example, Al _a Ga _1-a N, other than GaN.
Here, a is a numerical value satisfying 0 ≦ a <1,
It is also possible to form the nitride semiconductor shown by the above, or another nitride compound semiconductor.

The electron supply layer 5 as the second nitride semiconductor layer formed on the electron transit layer 4 has a band gap larger than that of the electron transit layer 4 to obtain the 2DEG layer 17 (shown by a dotted line) and For example, it is formed of a nitride semiconductor having a lattice constant smaller than that of the traveling layer 4 and represented by the following formula.
Al _x Ga _1-X N,
Here, x is a numerical value satisfying 0 <x <1, preferably 0.2 to 0.4, and more preferably 0.3.
Instead of forming the electron supply layer 5 with undoped Al _x Ga _1-x N, a nitride semiconductor made of Al _x Ga _1-x N doped with n-type (first conductivity type) impurities, or A nitride semiconductor having a different composition may be used.

  The source electrode 6 and the drain electrode 7 are formed by depositing, for example, titanium (Ti) to a desired thickness (for example, 25 nm) on one main surface 18 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5, and subsequently aluminum. Each of them is formed by depositing (Al) to a desired thickness (for example, 500 nm) and then forming a desired pattern by a photolithographic technique. The source electrode 6 and the drain electrode 7 of this embodiment are each formed of a laminate of titanium (Ti) and aluminum (Al), but are formed of a metal capable of low resistance contact (ohmic contact) other than this. You can also Since the electron supply layer 5 in the main semiconductor region 3 is extremely thin, the resistance in the thickness direction is negligibly small. Accordingly, the source electrode 6 and the drain electrode 7 are electrically coupled to the 2DEG layer 17.

The first insulating film 9 disposed on one main surface 18 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5, is 300 to 800 nm (preferably 500 nm) by plasma CVD (chemical vapor deposition). ) Formed of a silicon oxide, i.e., SiO _x (where x is a numerical value of 1 to 2 and preferably 2), and is a gate on one main surface 18 of the main semiconductor region 3. The entire region between the electrode 8 and the drain electrode 7 and the entire region between the source electrode 6 and the gate electrode 8 are covered. In order to stabilize and insulate one main surface 18 of the main semiconductor region 3, the entire area between the gate electrode 8 and the drain electrode 7 and the entire area between the source electrode 6 and the gate electrode 8 are first Although it is desirable to cover with the insulating film 9, it can be deformed so as to partially cover it. However, since the HEMT of the embodiment of FIG. 1 has the gate field plate 12, it is necessary to dispose the first insulating film 9 at least under the gate field plate 12.
The first insulating film 9 made of SiO _x or SiO ₂ has a property of generating compressive stress (for example, 4.00 × 10 ⁹ dyn / cm ² ). On the other hand, the SiN film formed on one main surface of the main semiconductor region by the conventional method has a property of generating tensile stress (for example, −6.14 × 10 ⁹ dyn / cm ² ). As described above, in the case of the conventional example in which the SiN film is formed on the surface of the HEMT, the tensile stress of the SiN film is applied to the surface of the electron supply layer, and the SiN film reduces the two-dimensional electron gas (2DEG). This increases the on-resistance between the source electrode and the drain electrode. On the other hand, since the first insulating film 9 made of silicon oxide of this embodiment generates compressive stress, it is possible to solve the disadvantages based on the tensile stress of the conventional SiN film, and to reduce the HEMT with low on-resistance. Can be provided.

Since the second insulating film 10 made of silicon oxide of this embodiment generates compressive stress, the height of the Schottky barrier of the gate electrode 8 is not reduced. Explaining this in detail, FIG. 3A shows an electron transit layer 4 made of GaN and an electron supply layer 5 made of AlGaN in the HEMT having the second insulating film 10 made of silicon oxide according to the present invention. It is a figure which shows an energy level. For comparison, FIG. 3B shows GaN in a HEMT (hereinafter referred to as a comparative example HEMT) in which the second insulating film 10 of FIG. 1 is formed of silicon nitride (SiN) instead of being formed of silicon oxide. It is a figure which shows the energy level of the electron transit layer which consists of, and the electron supply layer which consists of AlGaN. In FIG. 3, Ec represents the boundary between the forbidden band and the lowest level, that is the conduction band of the conduction band, E _F denotes a Fermi level. The barrier between the gate electrode 8 made of Ni (nickel) and the electron supply layer 5 made of AlGaN according to the embodiment of the present invention shown in FIG. It is higher than the corresponding part of the comparative example HEMT shown in (B). This is because the second insulating film 10 is formed of silicon oxide that generates compressive stress, and the first and second insulating films are formed of silicon oxide (SiN) that generates conventional tensile stress ( This means that the reduction in the height of the Schottky barrier can be solved.

As shown in FIG. 3A, when the barrier between the gate electrode 8 and the electron supply layer 5 made of AlGaN increases, the gate leakage current Igs flowing between the gate electrode 8 and the source electrode 6 in the off state of the HEMT is increased. Get smaller. 4 shows the relationship between the drain-source voltage Vds and the gate leakage current Igs when the HEMT according to the present invention is off, and the characteristic line B of FIG. 4 shows the drain-source voltage when the comparative example HEMT is off. The relationship between the source voltage Vds and the gate leakage current Igs is shown. The vertical axis is a logarithmic scale. As is apparent from FIG. 4, the gate leakage current Igs (gate-source leakage current) of the HEMT according to the present invention is significantly lower than that of the comparative example HEMT.
In order to obtain the effect of the first insulating film 9, it is desirable that the thickness of the first insulating film 9 be relatively thick, 300 to 800 nm. If the thickness of the first insulating film 9 is less than 300 nm, the effect based on the compressive stress cannot be obtained sufficiently, and if it is greater than 800 nm, the effect of the gate field plate 12 cannot be obtained sufficiently.

When the first insulating film 9 made of silicon oxide is formed by plasma CVD according to the present embodiment, the crystal damage of one main surface 18 of the main semiconductor region 3 is reduced as compared with the case where it is formed by sputtering. Levels (traps) are reduced, and current collapse can be suppressed.

When the gate electrode 8 and the gate field plate 12 are formed, first, a desired opening is formed in the first insulating film 9 by a well-known photolithography technique. In FIG. 1, the inclination of the wall surface of the opening in which the gate electrode 8 of the first insulating film 9 is disposed is inevitably generated in the etching process. Next, the gate electrode 8 and the gate field plate 12 are formed by, for example, a known lift-off method. That is, a resist film having openings corresponding to the gate electrode 8 and the gate field plate 12 is formed, Ni (nickel) is vapor-deposited (for example, by a sputtering method) to a desired thickness (for example, 25 nm), and Au ( Gold is vapor-deposited (for example, vapor deposition by a sputtering method) to a desired thickness (for example, 250 nm), and then the resist film is removed. Of course, instead of the lift-off method, Ni (nickel) and Au (gold) can be formed in a non-selective manner, and thereafter, another method for making them into a desired pattern can be adopted. The gate electrode 8 thus obtained is in Schottky contact with one main surface 18 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. Note that the gate electrode 8 and the gate field plate 12 may be formed of another metal such as a stacked body of platinum (Pt) and gold (Au) instead of forming the stacked layer of Ni and Au. Further, the linear gate electrode 8 of FIG. 2 can be transformed into a ring shape, a U shape or a U shape so as to surround the source electrode 6 or the drain electrode 7.

The gate electrode 8 is disposed between the source electrode 6 and the drain electrode 7 on one main surface 18 of the main semiconductor region 3, that is, one main surface of the electron supply layer 5. It is used to control the current flowing between. Since the HEMT of the present embodiment is a normally-on type, the source electrode 6 and the drain electrode 7 are turned on in a normally state in which no bias voltage is applied to the gate electrode 8. In order to turn off the HEMT, a bias voltage that makes the potential of the gate electrode 8 negative with respect to the source electrode 6 is applied to the gate electrode 8.

The gate field plate 12 is formed integrally with the gate electrode 8 and extends from the gate electrode 8 onto the first insulating film 9. Here, the portion from the drain electrode 7 side portion where the gate electrode 8 is in contact with one main surface 18 of the main semiconductor region 3 to the end portion of the gate field plate 12 on the drain electrode 7 side is called the gate field plate 12. The breakdown voltage between the gate electrode 8 and the drain electrode 7 changes in proportion to the distance _LGFD between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7.
The characteristic line A in FIG. 5 indicates that the distance L _GD between the gate electrode 8 and the drain electrode 7 is fixed to 16 μm, and the distance L _GFD between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7. Indicates the breakdown voltage between the gate electrode 8 and the drain electrode 7 when the voltage is changed. The characteristic line B fixes the distance L _GD between the gate electrode 8 and the drain electrode 7 to 21.5 μm. The breakdown voltage between the gate electrode 8 and the drain electrode 7 when the distance _LGFD between the drain electrode 7 side end of the plate 12 and the drain electrode 7 is changed is shown. In order to measure the withstand voltage, a voltage for keeping the HEMT in an OFF state is applied between the gate electrode 8 and the source electrode 6 and at the same time between the source electrode 6 and the drain electrode 7. When a voltage is applied, the source-drain voltage is switched to a plurality of stages, the leakage current flowing between the gate electrode 8 and the drain electrode 7 is measured at each stage, and the value of the leakage current reaches a predetermined value The voltage obtained by subtracting the source-gate voltage from the source-drain voltage was taken as the breakdown voltage between the gate electrode 8 and the drain electrode 7. As is well known, when the leakage current increases, the semiconductor element is likely to be destroyed. For this reason, in the semiconductor field, the breakdown voltage is often determined based on the leakage current.

The length L _GF of the gate field plate 12 is _obtained by subtracting the distance L _GFD between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7 from the distance L _GD between the gate electrode 8 and the drain electrode 7. (L _GF = L _GD -L _GFD ). In the characteristic lines A and B of FIG. 5, the distance L _GD between the gate electrode 8 and the drain electrode 7 is fixed, and the distance between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7 is fixed. When L _GFD is increased, the withstand voltage increases as the distance L _GFD increases. As is clear from this, it is necessary to keep the length _LGF of the gate field plate 12 relatively short in order to improve the breakdown voltage. Therefore, it is desirable to shorten the length _LGF of the gate field plate 12 within a range in which the electric field concentration in the vicinity of the end of the gate electrode 8 on the drain electrode 7 side can be relaxed.

The length L _GF of the gate field plate 12 is determined in consideration of the on-resistance PRon between the source electrode 6 and the drain electrode 7. FIG. 6 shows a ratio L _GF / L _GFD between the length L _GF of the gate field plate 12 and the distance L _GFD between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7. The change in relative value is shown. The on-resistance PRon here is the same as the source electrode 6 after applying a pulse voltage for generating a current collapse between the gate electrode 8 and the source electrode 6 and between the source electrode 6 and the drain electrode 7. The on-resistance between the drain electrode 7 is shown.
As is clear from this, _when the value of L _GF / L _GFD is 70% or less, the on-resistance PRon is relatively small and the change of the on-resistance PRon (relative value) with respect to the change of L _GF / L _GFD is relatively small. On the other hand, _when the value of L _GF / L _GFD is larger than 70%, the on-resistance PRon becomes relatively large and the change in the on-resistance PRon (relative value) with respect to the change in L _GF / L _GFD becomes relatively large. Therefore, the ratio L _GF / L _GFD between the length L _GF of the gate field plate 12 and the distance L _GFD between the end of the gate field plate 12 on the drain electrode 7 side and the drain electrode 7 should be 70% or less. Preferably, it is more preferably 1 to 50%, most preferably 1 to 20%, and 20% in the embodiment of FIG. Since the gate field plate 12 suppresses electric field concentration in the vicinity of the gate electrode 8, the length L _GF of the gate field plate 12 is made as short as possible within a range where a desired electric field concentration reducing effect can be obtained. It is desirable. When the value of L _GF / L _GFD is 1% or more, an electric field concentration relaxation effect can be obtained.

The second insulating film 10 electrically isolates the source field plate 13 from the gate electrode 8 and the gate field plate 12, and electrically connects the gate electrode 8 and the gate connection conductor 26 from the source connection conductor 24 and the drain connection conductor 26. And is formed on the gate electrode 8, the gate field plate 12, and the first insulating film 9. More specifically, the second insulating film 10 is a silicon oxide formed by plasma CVD to a thickness of 400 to 800 nm (preferably 500 nm), that is, SiO _x (where x is a value from 1 to 2). , Preferably ^2. ) and has the property of generating a compressive stress (for example, 4.00 × 10 ⁹ dyn / cm ² ) in the same manner as the first insulating film 9. For this reason, the second insulating film 10 made of silicon oxide contributes to the provision of a HEMT having a low on-resistance like the first insulating film 9, and the gate leakage current as described with reference to FIGS. Contributes to the reduction of
Note that the second insulating film 10 extends to a part on the source electrode 7 and the drain electrode 8 in the same manner as the first insulating film 9.

The source field plate 13 is trapped at the interface between the first main surface 18 of the main semiconductor region 3 and the first insulating film 9 to alleviate electric field concentration near the tip of the gate field plate 12 and cause current collapse. For removing (pulling out) the generated electrons, and is disposed on the second insulating film 10 and extends from the source electrode 6 to the drain electrode 8 side over the gate electrode 8 and the gate field plate 12. Exist. Note that a source additional electrode layer 19 is formed on the source electrode 6, a drain additional electrode layer 20 is formed on the drain electrode 8, and the source field plate 13 is formed integrally with the source additional electrode layer 19. Is distinguished from the source additional electrode layer 19. The source additional electrode layer 19 and the drain additional electrode layer 20 contribute to a reduction in electrical connection resistance. The source electrode 6 and the source additional electrode layer 19 may be collectively referred to as a source electrode. In this case, the source electrode 6 becomes a source electrode main portion, and the source additional electrode layer 19 has a source electrode added (sub-electrode). ) Part. In addition, the drain electrode 7 and the drain additional electrode layer 20 can be collectively referred to as a drain electrode. In this case, the drain electrode 7 becomes a drain electrode main portion, and the drain additional electrode layer 20 has a drain electrode added (sub-electrode). ) Part

The source additional electrode layer 19, the drain additional electrode layer 20, and the source field plate 13 are formed by the same process and are shown in a single layer configuration in FIG. This is a laminated structure of a plating base layer) and a plating layer. These manufacturing methods will be described in detail. First, openings are formed in the first and second insulating films 9 and 10 to partially expose the source electrode 6 and the drain electrode 8. Next, Ti, Ni, and Au are sequentially deposited on the source electrode 6, the drain electrode 8, and the second insulating film 10 as metals for the plating base layer. Next, a resist film having openings corresponding to the source additional electrode layer 19, the drain additional electrode layer 20, and the source field plate 13 is formed on the plating base layer. Next, a plating layer is preferably formed to a thickness of 1 to 20 μm, more preferably 3 to 10 μm, and most preferably about 5 μm on the plating base layer exposed in the opening by Au electroplating. Next, after removing the resist film, the remaining plating base layer is removed by a well-known wet etching method to obtain a source additional electrode layer 19, a drain additional electrode layer 20, and a source field plate 13 having a desired pattern.
In place of the wet etching method, a resist film having a desired pattern is formed, and thereafter a plating base layer having a desired pattern is formed. Thereafter, a plating layer is formed on the plating base layer by an electrolytic plating method of Au. Other methods can be employed.

The end of the source field plate 13 on the drain electrode 8 side is connected to the end of the gate field plate 12 on the drain electrode 8 side in order to alleviate electric field concentration near the end of the gate field plate 12 on the drain electrode 8 side. It is located between the electrodes 8. In FIG. 1, the length L _{SF of the} portion where the source field plate 13 protrudes from the gate field plate 12 to the drain electrode 8 side _, and the gap between the drain electrode 8 side end of the source field plate 13 and the drain electrode 8. The distance L _SFD has an important meaning in the properties of the HEMT. According to many experiments by the present applicant, if the length L _{SF of the} portion of the source field plate 13 protruding from the gate field plate 12 to the drain electrode 8 side is too long, the pulse between the source electrode 6 and the drain electrode 8 is lost. It was confirmed that not only the breakdown voltage decreased, but the on-resistance increased. Further, the drain electrode 7 side end of the source field plate 13 and the drain electrode 7 side end of the gate field plate 12 with respect to the distance (L _GFD ) between the end of the gate field plate 12 on the drain electrode 7 side and the drain electrode 7. The preferred range of the ratio (L _sF / L _GFD ) of the distance (L _SF ) between is 1 to 60%, the more preferred range is 1 to 50%, and the most preferred range is 1 to 25% It has been found.

The breakdown voltage between the source electrode 6 and the drain electrode 7 changes in proportion to the distance L _SFD between the end of the source field plate 13 on the drain electrode 7 side and the drain electrode 7. The characteristic line C in FIG. 7 indicates that the distance L _GD between the gate electrode 8 and the drain electrode 7 is fixed to 21.5 μm, and the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7 are fixed. The breakdown voltage between the source electrode 6 and the drain electrode 7 when the distance L _GFD is fixed to 16 μm and the distance L _SFD between the end of the source field plate 13 on the drain electrode 7 side and the drain electrode 7 is changed. The characteristic line D indicates that the distance L _GD between the gate electrode 8 and the drain electrode 7 is fixed to 21.5 μm, and the distance between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7 is shown. the L _GFD fixed to 19 .mu.m, shows the breakdown voltage between the source electrode 6 and the drain electrode 7 when distance L _SFD is a change between the drain electrode 7 side end of the drain electrode 7 of the source field plate 13 . In order to measure the withstand voltage, a voltage for keeping the HEMT in an off state is applied between the gate electrode 8 and the source electrode 6 and at the same time between the source electrode 6 and the drain electrode 7. When a voltage is applied, the source-drain voltage is switched to a plurality of stages, the leakage current flowing between the source electrode 6 and the drain electrode 7 is measured at each stage, and the value of the leakage current becomes a predetermined value The voltage between the source and the drain was set to the breakdown voltage between the source electrode 6 and the drain electrode 7.

The length L _SF of the protruding portion of the source field plate 13 from the gate field plate 12 is _determined from the distance L _GFD between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7. This corresponds to a value (L _GFD −L _SFD ) _obtained by subtracting the distance L _SFD between the 7 side end and the drain electrode 7. Accordingly, the distance L _GD between the gate electrode 8 and the drain electrode 7 is fixed as shown by the characteristic lines C and D in FIG. 7, and the distance between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7 is fixed. When the distance L _GFD is fixed, even if the distance L _SFD between the drain electrode 7 side end of the source field plate 13 and the drain electrode 7 is increased, the withstand voltage only slightly increases and hardly changes. This means that the breakdown voltage does not depend much on the length L _SF of the protruding portion of the source field plate 13.

The length L _GF of the protruding portion of the source field plate 13 is determined in consideration of the ON resistance PRon between the source electrode 6 and the drain electrode 7. Figure 8 is turned with respect to the change of the ratio L _SF / L _GFD and the distance L _GFD between the drain electrode 7 side end of the drain electrode 7 of the projection length of the portion L _SF and the gate field plate 12 of the source field plate 13 The change of resistance PRon (relative value) is shown.
Here, the on-resistance PRon is defined between the source electrode 6 and the drain electrode 7 after a predetermined pulse voltage (for example, 400 V) for generating a current collapse is applied between the source electrode 6 and the drain electrode 7. Of resistance. At the time of applying this pulse voltage, for example, -5 V was applied between the source electrode 6 and the gate electrode 8 to keep the HEMT in the OFF state. Further, the application of the pulse voltage was repeated a predetermined number of times (for example, 500 times).
As apparent from FIG. 8, the on-resistance PRon (relative value) becomes maximum when the value of L _SF / L _GFD is 60%. The on-resistance PRon (relative value) decreases both when the value of L _SF / L _GFD becomes smaller than 60% and when it becomes larger. It turned on to obtain a small and and desired pulse breakdown voltage as possible resistance Pron, between the drain electrode 7 side end of the drain electrode 7 of the protrusion length L _SF and the gate field plate 12 of the source field plate 13 As already explained, the ratio L _SF / L _GFD to the distance L _GFD is preferably 1 to 60%, more preferably 1 to 50%, and most preferably 1 to 25%. Even if L _SF / L _GFD becomes larger than 60%, the on-resistance PRon decreases. However, when the length L _SF of the protruding portion of the source field plate 13 is increased so that the value of L _SF / L _GFD is larger than 60%, the breakdown voltage between the source electrode 6 and the drain electrode 7 is a desired value. Lower than.
Since the source field plate 13 suppresses electric field concentration near the tip of the gate field plate 12, the length L _SF of the protruding portion of the source field plate 13 is within a range where a desired electric field concentration reducing effect can be obtained. If L _SF / L _GFD is 1% or more, the electric field concentration relaxation effect can be obtained.

The third insulating film 11 is for protecting the second insulating film 10 and a portion below the second insulating film 10 from the outside, and is formed of a material having higher moisture resistance than the second insulating film 10. The third insulating film 11 of this embodiment is composed of a SiN film (silicon nitride film) that covers the source additional electrode layer 19, the drain additional electrode layer 20, the source field plate 13 and the second insulating film 10. When the third insulating film 11 is formed, an SiN film having a thickness of preferably 300 to 1000 nm, more preferably 500 nm is formed by a plasma CVD method using a source additional electrode layer 19, a drain additional electrode layer 20, a source field plate 13 and a first field electrode 13. Then, a resist film is formed to expose the source bonding pad electrode 21, the drain bonding pad electrode 22, and the gate bonding pad electrode 23, and the third insulating film 11 is selected. Etching is performed to form an opening in the third insulating film 11, and then the resist film is removed.
A fourth insulating film such as a polyimide resin can be further formed on the third insulating film 11 to a thickness of, for example, 5 to 20 μm. Further, a polyimide resin film can be provided instead of the SiN film of the third insulating film 11. The insulating film made of polyimide resin has the property of generating tensile stress like the SiN film.

The back electrode 14 is for stabilizing the operation of the HEMT, and is formed on the other main surface 14 of the conductive substrate 1 and is electrically connected to the source electrode 6 by a conductor not shown. It is connected.

As is apparent from the above, the HEMT of this example has the following effects.
(1) On the gate electrode 8 provided with the first insulating film 9 made of silicon oxide on one main surface of the main semiconductor region 3 made of nitride semiconductor and in Schottky contact with the main semiconductor region 3 A second insulating film 10 made of silicon oxide is provided. Since the second insulating film 10 made of silicon oxide generates compressive stress, the height of the Schottky barrier of the gate electrode 8 is the same as that of the conventional silicon nitride (SiN) that generates tensile stress. It becomes higher than the height of the Schottky barrier of the gate electrode of the HEMT on which the film is formed. As a result, the gate leakage current can be reduced.
(2) When the compressive stress of the first and second insulating films 9 and 10 acts on one main surface 18 of the main semiconductor region 3, that is, the main surface of the electron supply layer 5, 2DEG based on piezoelectric polarization of the electron supply layer 5 The number of electrons in the layer 17 increases. Thereby, a HEMT with low on-resistance can be provided.
(3) Since the third insulating film 11 made of silicon nitride (SiN) having higher moisture resistance than silicon oxide is provided on the first and second insulating films 9 and 10, moisture resistance is improved. A high HEMT can be provided.
(4) Although the third insulating film 11 made of silicon nitride (SiN) generates tensile stress, the first and second insulating films 9 and 10 are formed to be relatively thick. It is possible to suppress the tensile stress of the film 11 from reaching one main surface 18 of the main semiconductor region 3 and the gate electrode 8.
(5) Since the relatively thick source field plate 13 is disposed between the third insulating film 11 and the second insulating film 10 made of silicon nitride (SiN), the silicon nitride (SiN) is used. The tensile stress of the third insulating film 11 formed can be prevented from reaching one main surface 18 and the gate electrode 8 of the main semiconductor region 3.
(6) The ratio L _GF / L _GFD of the length L _GF of the gate field plate 12 to the distance L _GFD between the drain electrode 7 side end of the gate field plate 12 and the drain electrode 7 is set to 1 to 70%. And the drain electrode 7 side end of the source field plate 13 and the drain electrode 7 side end of the gate field plate 12 with respect to the distance _LGFD between the end of the gate field plate 12 on the drain electrode 7 side and the drain electrode 7. (The length of the protruding portion of the source field plate 13 from the end of the gate field plate 12) The ratio L _sF / L _GFD of L _SF is set in the range of ₁ to 60%, whereby the gate electrode 8 The breakdown voltage between the drain electrode 7 and the drain electrode 7 can be improved, the increase in on-resistance due to the current collapse phenomenon can be suppressed, and the leakage current can be reduced.
(7) The source field plate 13 is formed in the same process as the source additional electrode layer 19 and the drain additional electrode layer 20. Therefore, the source field plate 13 can be easily obtained.
(8) The source additional electrode layer 19, the drain additional electrode layer 20, and the source field plate 13 are formed of an Au plating layer with a plating base layer and are thicker than the source electrode 6 and the drain electrode 7. Therefore, the electrical resistance between the source electrode 6 and the source bonding pad electrode 21, between the drain electrode 7 and the drain bonding pad electrode 22, and the source field plate 13 can be reduced.

Next, the HEMT according to the second embodiment shown in FIG. 9 will be described. However, in FIG. 9 and FIGS. 10 to 12 described later, substantially the same parts as those in FIG.
In the HEMT of FIG. 9, n-type impurity implantation regions 27 and 28 for improving low resistance contact, which are illustrated by hatching, are added to the main semiconductor region 3a, and the third insulating film 11 is formed in the second region. It is provided only on the insulating film 10, and the others are formed substantially the same as the HEMT of the first embodiment shown in FIG. In the n-type impurity implantation regions 27 and 28, after the formation of the electron transit layer 3 and the electron supply layer 4, an n-type impurity made of, for example, Si is implanted into portions corresponding to the source electrode 6 and the drain electrode 7. And is electrically connected to the 2DEG layer 17. The second embodiment shown in FIG. 9 has the same effect as the first embodiment shown in FIG. 1, and the source electrode 6 and the drain electrode 7 are electrically connected to the 2DEG layer 17 via the n-type impurity implantation regions 27 and 28. Since it is connected to, the on-resistance can be reduced. Moreover, since the source additional electrode layer 19, the drain additional electrode layer 20, and the source field plate 13 are exposed, they can be used for electrical connection.

In the HEMT of Example 3 in FIG. 10, an electron supply layer 5a made of Al _x Ga _1-x N containing n-type impurities is provided in the main semiconductor region 3b, and the electron travel made of n-type electron supply layer 5a and GaN. A well-known spacer layer 30 made of undoped AlN is arranged between the layer 4 and contact layers 31 and 32 made of, for example, n-type AlGaN are arranged between the source electrode 6 and the drain electrode 7 and the electron supply layer 5a. The others are substantially the same as the HEMT of the first embodiment shown in FIG. The spacer layer 30 prevents impurities or elements in the electron supply layer 5 a from diffusing into the electron transit layer 4, and suppresses a decrease in electron mobility in the 2DEG layer 17. The contact layers 31 and 32 contribute to a reduction in contact resistance between the source electrode 6 and the drain electrode 7. Since the main part of the HEMT in FIG. 10 is configured in the same manner as in FIG. 1, the HEMT in FIG. 10 has the same effect as the HEMT in FIG.

FIG. 11 shows a Schottky barrier diode or SBD using a nitride semiconductor according to the fourth embodiment. This SBD omits the source electrode 6, the source additional electrode layer 19 and the source field plate 13 from the HEMT of FIG. 1, and replaces the gate electrode 8, the gate field plate 12, the drain electrode 7 and the drain additional electrode layer 20 of FIG. This corresponds to a first electrode 8a, a Schottky field plate or anode field plate 12a, a second electrode 7a, and a cathode additional electrode layer 20a formed substantially the same as these. Note that the first, second, and third insulating films 9, 10, and 11 in FIG. 11 are formed substantially the same as those indicated by the same reference numerals in FIG. In FIG. 11, the distance between the first and second electrodes 8a and 7a is indicated by L _GD ′, the length of the anode field plate 12a is indicated by L _GF ′, and the second of the anode field plate 12a The distance between the end portion on the electrode (cathode electrode) 7a side and the second electrode (cathode electrode) 7a is indicated by L _GFD '. L _GF ′, L _GD ′, and L _GFD ′ in FIG. 11 correspond to L _GF , L _GD , and L _GFD in FIG. 11 and are set under the same conditions as L _GF , L _GD , and _LGFD .

In the SBD of FIG. 11, when a negative voltage having an absolute value higher than a threshold value is applied to the first electrode 8a made of a Schottky electrode, the first electrode 8a and the second electrode 7a are turned off. When the voltage is not applied to the first electrode 8a or when a negative voltage or a positive voltage having an absolute value equal to or lower than the threshold is applied, the first electrode 8a and the second electrode 7a are turned on. It becomes a state. When the SBD is in an ON state, a current flows through the path of the first electrode 8a, the electron supply layer 5, the 2DEG layer 17, the electron supply layer 5, the second electrode 7a, and the cathode additional electrode layer 20a.

The main semiconductor region 3c of the SBD of FIG. 11 is formed in the same manner as the main semiconductor region 3 of the HEMT of FIG. 1, and the first, second and third insulating films 9, 10, and 11 of FIG. Since it is formed to be substantially the same as that indicated by the reference numerals, the same effect as the HEMT of FIG. 1 can be obtained except for the effect of the source field plate 13 of FIG. That is, the first and second insulating films 9 and 10 made of silicon oxide increase the Schottky barrier of the first electrode 8a to reduce the leakage current between the first and second electrodes 8a and 7a, and 2DEG The number of electrons in the layer 17 can be increased.

FIG. 12 shows a MESFET using a nitride semiconductor according to the fifth embodiment.
In this MESFET, a semiconductor layer 4a made of, for example, GaN, instead of the main semiconductor region 3 of the HEMT in FIG. 1, and an n-type GaN layer 4b formed by implanting an n-type impurity (for example, Si) into the semiconductor layer 4a. The other main semiconductor region 3d is formed substantially the same as the HEMT of the first embodiment shown in FIG. The n-type GaN layer 4b functions as a channel layer, that is, a current path.

The MESFET of FIG. 12 also includes the gate electrode 8 that is in Schottky contact with the main semiconductor region 3d, the first and second insulating films 9 and 10 made of silicon oxide, and the gate field. Since the plate 12 and the source field plate 13 are formed in the same manner as in FIG. 1, the effect of increasing the Schottky barrier of the gate electrode 8 and the effect of reducing the electric field concentration by the gate field plate 12 and the source field plate 13 are the same as those of the HEMT in FIG. It can be obtained similarly.

The present invention is not limited to the above-described embodiments, and for example, the following modifications are possible.
(1) The main semiconductor regions 3, 3a, 3b, 3c, and 3d may be formed of another nitride semiconductor such as InGaN, AllnGaN, AlN, and InAlN other than GaN and AlGaN.
(2) The electron supply layers 5 and 5a in the HEMT and SBD embodiments can be replaced with a hole supply layer made of a p-type semiconductor. In this case, a two-dimensional hole gas layer is generated as a two-dimensional carrier gas layer in a region corresponding to the 2DEG layer 17.
(3) A recess is formed in the uppermost electron supply layers 5 and 5a of the main semiconductor regions 3, 3a, 3b, and 3c in the HEMT and SBD embodiments, and the gate electrode 8 or the first electrode is formed in the recess. The present invention can also be applied to a normally-off HEMT or SBD that is turned off when no voltage is applied to the gate electrodes 8 and 8a, that is, in a normally-state, by a method of disposing the electrode 8a.
(4) The gate electrode 8 and the gate field plate 12 of the HEMT can be separated and connected to each other by another conductor. Similarly, the first electrode 8a and the anode field plate 12a of the SBD can be separated and connected to each other by another conductor. Further, the source electrode 6 and the source field plate 13 of the HEMT can be separated and connected to each other by another conductor.
(5) A drain field plate connected to the drain electrode 7 can be provided.
(6) The thickness of the gate field plate 12 can be gradually decreased from the gate electrode 8 toward the drain electrode 7 with an inclination or gradually.
(7) The thickness of the first insulating film 9 under the gate field plate 12 can be gradually increased from the gate electrode 8 toward the drain electrode 7 with an inclination or gradually.
(8) As shown by a chain line in FIG. 10, a cap layer 33 made of, for example, undoped AlGaN is provided on the top of the main semiconductor region 3b to assist the Schottky contact of the gate electrode 8 or to control the surface charge. be able to.
(9) Either or both of the gate field plate 12 and the source field plate 13 can be omitted.
(10) A first insulating film made of SiO _{x on} the entire main surface 18 of the main semiconductor region 3 between the source electrode 6 and the gate electrode 8 and between the drain electrode 7 and the gate electrode 8. Instead of covering with 9, an insulating film made of SiO _x covers only a part between the source electrode 6 and the drain electrode 7 on one main surface 18 of the main semiconductor region 3, and the other is covered with another insulating film such as SiN. Can be covered. In addition, instead of covering the gate electrode 8, the gate field plate 12, and the first insulating film 9 with the second insulating film 10 made of SiO _x , at least the gate electrode 8 is insulated with SiO _x. It can be covered with a film and the rest can be covered with another insulating film such as SiN.

It is sectional drawing which shows a part of HEMT of Example 1 of this invention. It is a top view which shows the HEMT of Example 1 in the state containing a some cell. It is an energy level diagram which shows the height of the Schottky barrier of the gate electrode of HEMT of Example 1 of FIG. 1 and conventional HEMT. It is a figure which shows the gate leakage current of HEMT of Example 1 of FIG. 1, and conventional HEMT. It is a figure which shows the relationship between the distance _LGFD between the drain electrode side edge part of the gate field plate of HEMT of FIG. 1, and a drain electrode, and a proof pressure. _Ratio of the distance L _GFD between the drain electrode side end of the gate field plate of the HEMT of FIG. 1 and the drain electrode and the length L _GF of the gate field plate L _GF / L _GFD ON resistance PRon (relative value) It is a figure which shows the change of (). It is a figure which shows the relationship between the distance L _SFD between the drain electrode side edge part of the source field plate of HEMT of FIG. 1, and a drain electrode, and a proof pressure. The ON resistance PRon (relative value) with respect to the change in the ratio L _SF / L _GFD between the distance L _GFD between the drain electrode side end of the gate field plate of the HEMT of FIG. 1 and the drain electrode and the length L _GF of the source field plate It is a figure which shows the change of (). 6 is a cross-sectional view showing a HEMT of Example 2. FIG. 6 is a cross-sectional view showing a HEMT according to Example 3. FIG. 6 is a cross-sectional view showing an SBD of Example 4. FIG. FIG. 10 is a cross-sectional view showing a MSEFT of Example 5.

Explanation of symbols

1 substrate 2 buffer layer 3 main semiconductor region 4 electron transit layer (first semiconductor layer)
5 Electron supply layer (second semiconductor layer)
6 Source electrode 7 Drain electrode 8 Gate electrode 9 First insulating film 10 Second insulating film 12 Gate field plate 13 Source field plate

Claims (12)

A main semiconductor region including at least one semiconductor layer of nitride semiconductor;
A first electrode in Schottky contact with one main surface of the main semiconductor region;
A second electrode disposed on one main surface of the main semiconductor region and spaced apart from the first electrode and in ohmic contact with one main surface of the main semiconductor region;
A first insulating film that is disposed on at least a portion between the first electrode and the second electrode on one main surface of the main semiconductor region and is formed of silicon oxide;
A nitride semiconductor device comprising: a second insulating film disposed on at least the first electrode and made of silicon oxide. A main semiconductor region including at least one semiconductor layer of nitride semiconductor;
A source electrode disposed on one main surface of the main semiconductor region;
A drain electrode disposed apart from the source electrode on one main surface of the main semiconductor region;
A Schottky contact with the main semiconductor region disposed between the source electrode and the drain electrode on one main surface of the main semiconductor region to control a current path between the source electrode and the drain electrode A gate electrode,
A first insulating film that is disposed on at least a portion between the source electrode and the drain electrode on one main surface of the main semiconductor region and is formed of silicon oxide;
A nitride semiconductor device comprising: a second insulating film disposed on at least the gate electrode and formed of silicon oxide. 3. The nitride semiconductor device according to claim 1, wherein each of the first and second insulating films is a silicon oxide film formed by plasma CVD. 4. The nitride semiconductor device according to claim 1, wherein each of the first and second insulating films has a thickness in a range of 300 to 800 nm. And a gate field plate disposed on the first insulating film between the gate electrode and the drain electrode and electrically connected to the gate electrode, wherein the second insulating film comprises: 5. The nitride semiconductor device according to claim 2, wherein the nitride semiconductor device is also disposed on the gate field plate. And a Schottky field plate disposed on the first insulating film and electrically connected to the first electrode, wherein the second insulating film is disposed on the Schottky field plate. The nitride semiconductor device according to claim 1, further comprising: 6. The device according to claim 2, further comprising a source field plate disposed on the second insulating film and electrically connected to the source electrode. Nitride semiconductor device. Furthermore, it has the 3rd insulating film which is arrange | positioned on the said 2nd insulating film and is formed with the silicon nitride or the polyimide resin, The one of Claim 1 thru | or 7 characterized by the above-mentioned. The nitride semiconductor device described in 1. Third insulation formed on the source field plate and on a portion of the second insulating film where the source field plate is not provided as viewed in plan and made of silicon nitride or polyimide resin 8. The nitride semiconductor device according to claim 7, further comprising a film. In the main semiconductor region, the first nitride semiconductor layer is formed such that a two-dimensional carrier gas layer can be formed along an interface between the first nitride semiconductor layer and the first nitride semiconductor layer. The nitride semiconductor device according to claim 1, further comprising: a second nitride semiconductor layer heterojunctioned to the first nitride semiconductor layer. In the main semiconductor region, the first nitride semiconductor layer is formed such that a two-dimensional carrier gas layer can be formed along an interface between the first nitride semiconductor layer and the first nitride semiconductor layer. And a second nitride semiconductor layer heterojunctioned to,
6. The nitride semiconductor device according to claim 2, wherein the source electrode and the drain electrode are each electrically coupled to the two-dimensional carrier gas layer. 11. The main semiconductor region further includes a spacer layer made of a nitride semiconductor disposed between the first nitride semiconductor layer and the second nitride semiconductor layer. 11. The nitride semiconductor device according to 11.

Images