CN105448713B - A kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method - Google Patents
A kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method Download PDFInfo
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- CN105448713B CN105448713B CN201510878221.3A CN201510878221A CN105448713B CN 105448713 B CN105448713 B CN 105448713B CN 201510878221 A CN201510878221 A CN 201510878221A CN 105448713 B CN105448713 B CN 105448713B
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- 239000002184 metal Substances 0.000 claims description 19
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- 150000001875 compounds Chemical class 0.000 claims description 8
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- 238000000151 deposition Methods 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 7
- 239000003989 dielectric material Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 4
- 229910004205 SiNX Inorganic materials 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 3
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention discloses a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method.This method grows laminated gate medium in semiconductor surface, and using photoresist as mask, utilizes dry method（Or wet method）Etching is for different grid medium etchings（Or corrosion）The difference of speed, pass through etching（Or corrosion）The controllable hole of regular shape size is formed in grid pin both sides, grid evaporation can obtain the T-shaped grid that section pattern is good and parasitic capacitance is controllable after peeling off.Advantage：The Si O layers of thin layer are inserted between the loose fine and close gate medium of three layers of densification, form five layers of dielectric structure, by adjusting dry etching condition, suitable lateral erosion depth is formed, while also can adjust each thickness of dielectric layers ratio, to control the height of lateral erosion, and then control the size for forming medium cavity, after grid evaporation is peeled off, the controllable medium cavity of a size can be formed below the grid cover of T-shaped grid so that grid parasitic capacitance reduces and frequency characteristic lifting becomes controllable.
Description
Technical field：
The present invention relates to a kind of two generation and the grid preparation method of three generations's semiconductor high-mobility field-effect transistor.Belong to half
Conductor technology field.In Engineering applications of microwave and millimeter waves, grid metal medium cavity is formed by suitable process meanses to reduce grid
Parasitic capacitance is to improve the effective means of device high frequency performance.Gate medium cavity proposed by the present invention forming method can pass through tune
The size in whole medium cavity so that grid parasitic capacitance reduces the advantages of more controllable, for improving microwave and millimeter wave device correlation
Application value can be had much.
Background technology：
Compound semiconductor materials compares traditional silicon materials, has the characteristics that mobility is high, energy gap is big, therefore extensively
It is general to be used for the fields such as high frequency, microwave.With the development of compound semiconductor device, wireless communications market, space flight, military issue weapons dress
The field such as standby for microwave transistor performance it is also proposed that higher requirement.In order to realize higher gain, lower noise, more
Fast operating rate, the substantial amounts of energy that various countries are all put into compound semiconductor research and development field.
For microwave and millimeter wave device, it is to reduce device gate length to reduce raceway groove to lift one of Main Means of frequency characteristic
The transition time of electronics reaches the purpose of lifting frequency characteristic.The grid of advanced GaAs, InP, GaN device are grown both at home and abroad at present
Through narrowing down to the level within 100nm, and the increase for the gate resistance brought therewith turns into restriction small size device performance boost
One of an important factor for, in order to solve the problems, such as gate resistance increase, the method for increasing grid cover size is usually taken, namely it is so-called
T-shaped grid, Y types grid or Mushroom Gate.
And this reduce the technological means of grid resistance to reach by increasing grid cover size and do not claim still to be a kind of perfect solution
Certainly scheme, because the introduced parasitic capacitance of large scale grid cover can cause the decline of device frequency characteristic.Especially for small grid
For long device, its intrinsic capacity is small, parasitic capacitance is relatively large, parasitic capacitance turn into influence device frequency characteristic it is main because
Element, so for microwave and millimeter wave device, the core for lifting frequency characteristic is to reduce grid parasitic capacitance.
A kind of method that conventional reduction dielectric constant influences is naked grid technique, i.e., not growing grid before grid metal evaporation is situated between
Matter, desired glue-type is directly obtained by electron-beam direct writing or deep UV lithography on material, after grid metal evaporation, glue-type turned
Grid-type is turned to, stripping obtains metal gate, grows one layer of isotropic medium parcel afterwards, completes grid passivation.Naked grid technique sheet
Body has certain deficiency, including：Due to no dielectric support, grid easily cause down grid when peeling off, and before grid passivation, grid gesture
Build metal to be directly exposed in air, the Schottky contacts of grid potential barrier can be influenceed.
It is another conventional means for reducing grid parasitic capacitance that medium cavity is formed under grid cover metal, because compared to SiNx
Dielectric capacitance, the vacuum of same size（Air）Dielectric capacitance value is about the former 1/7.Generally after the shaping of T-shaped grid metal, profit
The medium of assistant formation is removed with the dry etching of isotropic hardening, recycles the strong method growth protecting of anisotropy to be situated between
Matter, closure cavity is formed because all directions growth rate is different.The problem of technique, is dry etching assistant formation medium
The step of damage can be brought to the surface of device, while the vacuum hole general size to be formed is grown using anisotropic approaches very
Small, the reduction for grid parasitic capacitance is also than relatively limited；And its shape size is difficult to control, this will result in piece between piece
It is discrete.
Therefore a kind of process in the controllable medium cavity of large scale is sought, for improving the especially small long device of grid of device
Frequency characteristic it is significant.
The content of the invention：
Proposed by the present invention is a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method, and purpose exists
In the drawbacks described above present in solution prior art.
To make the medium cavity to be formed controllable, five layers of medium are grown successively in semiconductor surface, are respectively to cause from bottom to top
Close-most fine and close-loose-most fine and close-fine and close dielectric layer, medium includes but is not limited to SiNx, SiO used by dielectric layerxWith
SiONxDeng.
Utilizing dry method（Wet method）Method etching（Corrosion）When medium, because the medium of centre is more loose, then
Cavity can be automatically formed, and its upper and lower two layers finer and close dielectric layer can also protect the pattern of outermost dielectric layer, adjust simultaneously
The thickness of each layer medium, it can also make it that the medium hole to be formed is more regular also more controllable, finally both having avoided does not have medium support
Caused by grid fall grid when peeling off, while grid parasitic capacitance can also be reduced, reach the purpose of the frequency characteristic of lifting device.
The technical solution of the present invention：A kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor making side
Method, comprise the following steps that：
1）Cushion, channel layer, barrier layer, low-doped GaAs layers and height are sequentially formed using MBE method on substrate
Doped gaas layer；
2）Two ohmic contact regions are formed on highly doped GaAs layers respectively as pseudomorphic high electron mobility transistor
Source electrode and drain electrode, and it is highly doped using the removal of the method for dry etching or wet etching between two ohmic contact regions
GaAs layers are to form a sipes；
3）Five layers of dielectric layer of surface deposition between two Ohm contact electrodes, deposition process include plasma enhancing
Chemical vapour deposition, electron beam evaporation；
4）Medium window and cavity are formed using dry etching or wet etching, by adjusting etch application or five layers of medium
Thickness proportion obtain needing the medium cavity of size；
5）Using medium window as mask, using the low-doped GaAs layers at wet etching or dry etching window, formed
Stria；
6）Electron beam evaporation gate electrode metal may be selected；
7）Source electrode and leakage of two ohmic contact regions respectively as transistor are formed on compound semiconductor epitaxial layer
Electrode.
Advantages of the present invention：The Si-O layers of thin layer are inserted between the gate medium of three layers of densification-loose-densification, form five
Layer dielectric structure, by adjusting dry method（Wet method）Etching（Corrosion）Condition, suitable lateral erosion depth is formed, while also can adjust each
Thickness of dielectric layers ratio, to control the height of lateral erosion, and then the size for forming medium cavity is controlled, wherein middle porous medium
Thickness determine the longitudinal size in vacuum cavity, both sides most compact medium plays support and ensures the work of vacuum cavity integrality
With.After grid evaporation is peeled off, the controllable medium cavity of a size can be formed below the grid cover of T-shaped grid so that grid parasitic capacitance
Reduce and frequency characteristic lifting becomes controllable.
Brief description of the drawings：
Fig. 1 is the schematic diagram of common GaAs pseudomorphic high electron mobility transistors；
Fig. 2 is the signal of the GaAs pseudomorphic high electron mobility transistors in controllable vacuum medium cavity proposed by the present invention
Figure；
Fig. 3 is GaAs epitaxial structure schematic diagrames；
Schematic diagram after the evaporation of Fig. 4 source and drain；
Grooving process chart of Fig. 5；
Schematic diagram after the completion of the growth of Fig. 6 gate mediums；
Fig. 7 grid medium etching process charts；
Fig. 8 grid grooving process charts；
Fig. 9 grid evaporation technology flow charts；
Schematic diagram after Figure 10 grid metals are peeled off.
Embodiment
A kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method, is comprised the following steps that：
1）Cushion, channel layer, barrier layer, low-doped GaAs layers and height are sequentially formed using MBE method on substrate
Doped gaas layer；
2）Two ohmic contact regions are formed on highly doped GaAs layers respectively as pseudomorphic high electron mobility transistor
Source electrode and drain electrode, and it is highly doped using the removal of the method for dry etching or wet etching between two ohmic contact regions
GaAs layers are to form a sipes；
3）Five layers of dielectric layer of surface deposition between two Ohm contact electrodes, deposition process include plasma enhancing
Chemical vapour deposition, electron beam evaporation；
4）Medium window and cavity are formed using dry etching or wet etching, by adjusting etch application or five layers of medium
Thickness proportion obtain needing the medium cavity of size；
5）Using medium window as mask, using the low-doped GaAs layers at wet etching or dry etching window, formed
Stria；
6）Electron beam evaporation gate electrode metal may be selected；
7）Source electrode and leakage of two ohmic contact regions respectively as transistor are formed on compound semiconductor epitaxial layer
Electrode.
Described cushion uses AlGaAs, and channel layer is growth InGaAs, and barrier layer is to grow AlGaAs, on barrier layer
Grow low-doped GaAs layers and highly doped GaAs layers.
5 layers of described dielectric layer, two layers of outermost are compact medium layer, and most middle is porous medium layer, and remaining two layers is most
Compact medium layer, dielectric material include SiNx、SiOxAnd SiONxDeng material, each thickness degree according to the design needs depending on.
5 layers of dielectric layer, is provided with medium window from top to bottom, wherein forming vacuum cavity on middle porous medium layer.5
The thickness of each dielectric layer is determined according to the actual requirements in layer dielectric layer.
The stria is located in sipes, and is in medium beneath window.
The medium cavity of formation is below gate electrode metal, and somatomedin is passivated after grid are peeled off.
Technical scheme is further described below in conjunction with the accompanying drawings：
As shown in figure 3, the structure of GaAs epitaxial materials from top to bottom substantially substrate and cushion, channel layer, barrier layer,
Low-doped GaAs layers and highly doped GaAs layers.
As shown in figure 4, on the GaAs epitaxial materials 306 shown in Fig. 3, by the way of electron beam evaporation forming ohm connects
Touched electrode 407 and 408.
Ohm contact electrode can be AuGeNi or any other conjunction that Ohmic contact can be formed with highly doped GaAs layers
Suitable material, and in nitrogen or any other suitable inert gas, pass through the 400 of 60s or sooC high-temperature thermal annealings into
Ohmic contact.
As shown in 502 steps in Fig. 5, the highly doped GaAs layers between source Ohm contact electrode and leakage Ohm contact electrode
On using photoetching method, formed a photoresist window, the method for then taking wet etching, replicate photoetching offset plate figure,
A sipes is formed on highly doped GaAs layers.
The bottom of sipes is the surface of low-doped GaAs layers, the width of sipes, apart from both sides Ohm contact electrode away from
From, be decided according to the actual requirements, and depending on the precision that can reach of photoetching in manufacture, and sipes depth is highly doped GaAs
The thickness of layer.
As shown in fig. 6, in five layers of dielectric layer of highly doped GaAs layers and sipes surface deposition, its dielectric layer 601 and 605
The needs of surface state are typically suppressed according to compound semiconductor and elect silicon nitride (SiN) as；Dielectric layer 603 is porous medium, can
Using but be not limited to silicon nitride（SiN）, silica（SiO2）；Dielectric layer 602 and 604 can be used but be not limited to silica（SiO2）,
The dielectric layer 601 and 605 that compares is finer and close.The method of five layers of dielectric layer deposition include atomic layer deposition, electron beam evaporation, etc. from
Daughter strengthens chemical vapour deposition（PECVD）, preferable using plasma enhancing chemical vapour deposition technology.
The method that photoetching is used on dielectric layer 605 between source Ohm contact electrode and leakage Ohm contact electrode, is formed
One photoresist window, then form a medium window, medium window width, location using the method for dry etching
Depending on different application purposes.
As shown in step 702 in Fig. 7, the difference using dry method to different compactness extent dielectric etch speed, in medium window
Certain side etching quantity is automatically formed at mouthful on dielectric layer 603, while beneficial to the etch resistance of dielectric layer 602 and 604 so that formed
Lateral erosion shape it is more regular.
As shown in figure 8, it is mask and the method for using wet etching or dry etching to recycle dielectric material, corrosion is low
Doped gaas layer forms stria.The bottom of stria is the surface of fresh barrier layer, is advantageous to the shape of following Schottky barrier
Into, and its width is substantially dependent upon the width of medium window, specific size and the method and bar of wet etching or dry etching
Part selection is relevant.
As shown in the step 901 in Fig. 9, by medium window, gate electrode metal 902 is deposited on to the surface of stria, and
And part metals are deposited on the surface of dielectric layer 605 close to the edge of medium window, therefore gate electrode metal 902 forms
The structure of T-shape.
All may be selected in gate electrode metal can form the metal system of Schottky contacts with compound semiconductor barrier layer,
Electron beam evaporation may be selected in the method for deposit.
As shown in Figure 10, can formed after grid metal stripping and surface passivation with controllable regular shape Jie
The T-shape gate device in matter cavity, dielectric passivation may be selected to use Si3N4Medium or Si3N4With SiO2Complex media be passivated.
The preparation method of pseudomorphic high electron mobility transistor, using any suitable growing method such as such as MBE in substrate
On successively epitaxial growth obtain cushion, channel layer, barrier layer, low-doped GaAs layers and the highly doped GaAs layers of device.
Two ohmic contact regions are made on highly doped GaAs layers respectively as source electrode and drain electrode, and in two electrodes
Between highly doped GaAs layers on sipes, sipes width and distance two formed using the method for dry etching or wet etching
The distance of individual electrode depends on the purposes of made device, and the depth of sipes depends on the thickness of highly doped GaAs layers.
It is fine and close in five layers of medium of source and drain Ohm contact electrode and sipes surface deposition, its material successively after the completion of sipes
Degree is followed successively by general/fine and close/loose/fine and close/general, and selectable dielectric material includes but is not limited to silicon nitride（SiN）, nitrogen
Change silicon/oxidative silicon（SiN/SiO2）One kind in complex media, the method for dielectric deposition include but is not limited to atomic layer deposition, electricity
Beamlet evaporation, plasma reinforced chemical vapor deposition（PECVD）.Utilize dry etching within sipes on dielectric layer afterwards
Method forms medium window, and medium window width, location depend on different application purposes, and recycling dielectric material is
Mask forms stria using the method for wet etching or dry etching processing potential barrier layer surface.Finally by electron beam evaporation
Gate electrode metal, grid are electric in deposit in the range of medium window adjacent edges on the intraoral barrier layer of medium window and above medium
Pole metal is allowed to form T-type structure, completes the making of vacuum cavity grid structure pseudomorphic high electron mobility transistor.
Claims (6)
- A kind of 1. vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method, it is characterized in that this method is including following Processing step：1）Cushion, channel layer, barrier layer, low-doped GaAs layers and highly doped are sequentially formed using MBE method on substrate GaAs layers；2）Source electricity of two ohmic contact regions respectively as pseudomorphic high electron mobility transistor is formed on highly doped GaAs layers Pole and drain electrode, and remove highly doped GaAs using the method for dry etching or wet etching between two ohmic contact regions Layer is to form a sipes；3）Five layers of dielectric layer of surface deposition between two Ohm contact electrodes, deposition process include plasma enhanced chemical Vapour deposition, electron beam evaporation；4）Medium window and cavity are formed using dry etching or wet etching, by the thickness for adjusting etch application or five layers of medium Degree ratio obtains needing the medium cavity of size；5）Using medium window as mask, using the low-doped GaAs layers at wet etching or dry etching window, stria is formed；6）Select electron beam evaporation gate electrode metal；7）Source electrode and drain electrode of two ohmic contact regions respectively as transistor are formed on compound semiconductor epitaxial layer；Five layers of described dielectric layer, two layers of outermost are compact medium layer, and most middle is porous medium layer, and remaining two layers is most fine and close Dielectric layer, dielectric material include SiNx、SiOxAnd SiONxMaterial, each thickness degree according to the design needs depending on.
- 2. a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method according to claim 1, its It is characterized in that described cushion uses AlGaAs, channel layer is growth InGaAs, and barrier layer is to grow AlGaAs, raw on barrier layer Long low-doped GaAs layers and highly doped GaAs layers.
- 3. a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method according to claim 1, its It is characterized in five layers of dielectric layer, is provided with medium window from top to bottom, wherein forms vacuum cavity on middle porous medium layer.
- 4. a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method according to claim 3, five The thickness of each dielectric layer is determined according to the actual requirements in layer dielectric layer.
- 5. a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method according to claim 1, its It is characterized in that stria is located in sipes, and is in medium beneath window.
- 6. a kind of vacuum cavity grid structure pseudomorphic high electron mobility transistor preparation method according to claim 1, its It is characterized in the medium to be formed cavity below gate electrode metal, somatomedin is passivated after grid are peeled off.
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| CN110707150B (en) * | 2019-11-13 | 2023-06-27 | 中国电子科技集团公司第十三研究所 | double-T-shaped nano gate and preparation method thereof |
| US20230369424A1 (en) * | 2021-07-16 | 2023-11-16 | Innoscience (Suzhou) Technology Co., Ltd. | Nitride-based semiconductor device and method for manufacturing the same |
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| CN102280476A (en) * | 2011-08-08 | 2011-12-14 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacturing method thereof |
| CN103887335A (en) * | 2014-02-25 | 2014-06-25 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacture method for improving frequency characteristic |
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| CN102280476A (en) * | 2011-08-08 | 2011-12-14 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacturing method thereof |
| CN103887335A (en) * | 2014-02-25 | 2014-06-25 | 中国电子科技集团公司第五十五研究所 | Pseudomorphic high electron mobility transistor and manufacture method for improving frequency characteristic |
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