WO2021086484A1 - Field effect transistor having field plate - Google Patents

Field effect transistor having field plate Download PDF

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Publication number
WO2021086484A1
WO2021086484A1 PCT/US2020/048323 US2020048323W WO2021086484A1 WO 2021086484 A1 WO2021086484 A1 WO 2021086484A1 US 2020048323 W US2020048323 W US 2020048323W WO 2021086484 A1 WO2021086484 A1 WO 2021086484A1
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WO
WIPO (PCT)
Prior art keywords
drain
gate
dielectric layer
semiconductor
field
Prior art date
Application number
PCT/US2020/048323
Other languages
French (fr)
Inventor
Michael S. Davis
Eduardo M. Chumbes
Brian T. APPLETON JR.
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Raytheon Company
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Publication date
Application filed by Raytheon Company filed Critical Raytheon Company
Priority to AU2020375557A priority Critical patent/AU2020375557B2/en
Priority to CN202080057609.6A priority patent/CN114303247A/en
Priority to JP2022525187A priority patent/JP7548676B2/en
Priority to EP20768801.1A priority patent/EP4052301A1/en
Priority to KR1020227003546A priority patent/KR20220029723A/en
Publication of WO2021086484A1 publication Critical patent/WO2021086484A1/en
Priority to IL290252A priority patent/IL290252A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • This disclosure relates generally to field effect transistors and more particularly to field effect transistors having field plate structures.
  • GaN-based Field Effect Transistor (FET) devices are capable of operating at much higher voltages than previous-generation devices based on GaAs or Si. Consequently, RF GaN devices can achieve much higher output powers with comparable power-added efficiencies.
  • FET Field Effect Transistor
  • GaN-based devices still exhibit some challenges when operated at high voltages. During the off-state portion of the RF cycle (where the drain-to-gate voltage reaches a maximum), the electric field maximum located at the drain edge of the gate reaches an extreme level that is typically on the same order as the breakdown field strength of GaN ( ⁇ 3 MV/cm). This peak field has several negative consequences.
  • DC/RF dispersion is characterized by the combination of “current collapse” (reduction of maximum current density under RF operation compared to its DC counterpart) and “knee walkout” (increased on-resistance of the transistor under RF operation compared to its DC counterpart).
  • a field effect transistor structure comprising a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, such electric charge solely producing the electric field.
  • a field effect transistor structure comprising a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and ion implanted electric charge disposed in portions of the dielectric layer.
  • a field effect transistor structure comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer on the surface of the semiconductor over the region between the gate and the drain; and fixed, immobile electric charge, having a predetermined distribution, disposed in the dielectric layer over the region between the gate and the drain.
  • the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain.
  • the charge is electrically isolated from the source and drain.
  • a method for forming a field effect transistor comprising: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor structure; forming a field plate, comprising: providing a dielectric layer disposed on the surface of the semiconductor in regions between the source and the drain, such dielectric layer extending over the gate; and depositing electric charge disposed in portions of the dielectric layer from a source external of the semiconductor structure, a portion of such charge being disposed in the dielectric layer over an upper surface of the semiconductor structure, the charge extending over the region between the gate and the drain.
  • the charge is deposited with a predetermined distribution into the dielectric layer.
  • a field effect transistor comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate comprising: a dielectric layer disposed on the surface of the semiconductor in a region between the source and the drain, the electric charge being disposed in a predetermined distribution in portions of the dielectric layer.
  • a field effect transistor comprising: a semiconductor; a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a plurality of vertically stacked dielectric layers, an upper one of the vertically stacked dielectric layers having fixed, immobile electric charge disposed in portions thereof providing a field plate structure, the fixed, immobile charge solely providing the field plate structure shaping an electric field in a region between the gate and the drain of the transistor, and wherein in the charge solely modifies the electric field in the region between the gate and drain of the transistor.
  • a method for forming a field effect transistor comprising: providing a semiconductor structure having a source, a drain and a gate in contact with a corresponding portions of a surface of the semiconductor; providing a dielectric layer disposed on the surface of the semiconductor over a region between the gate and the drain; and depositing electric ions disposed in portions of the dielectric layer from a source external of the semiconductor structure into the dielectric layer between the gate and the drain.
  • a second dielectric with more suitable material properties may be selectively or non-selectively disposed on the above structure. This second dielectric would extend over the gate; and fixed, immobile electric charge disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the charge being disposed in the dielectric layer in the region extending from the upper surface of the gate to a location between the gate and the drain.
  • the charge in the dielectric layer effectively substitutes for a conventional thin-film metal field plate.
  • the charged dielectric region acts as a self- biased field plate that can produce an electric field to modify the electric field distribution in the transistor and reduce the value of the maximum electric field.
  • This style of field plate eliminates the fabrication and yield difficulties associated with conventional thin- film metal field plates.
  • Introducing charge in the dielectric as described in these embodiments is done via ion implantation. This process involves accelerating ions from a source through an electric field directed into the sample, in this case our dielectric, changing its physical, chemical and/or electric properties. It is a process that is commonly used in semiconductor device fabrication.
  • the ion implant dose and distribution can be adjusted to suit breakdown requirements and to achieve the desired electric field shaping.
  • the ion implant species and implant technique can be selected to suit breakdown requirements and polarity.
  • the ion implant provides very simplified processing to achieve similar field reduction.
  • the ion implant pattern in another embodiment, can be created such that its aerial image will grade the dose implanted into the dielectric in such a way to effectively tilt or slant the field plate to achieve the desired electric field profile.
  • FIGS. 1A-1B through 4A-4B are plan and cross-sectional, diagrammatical sketches of a Field Effect Transistor having a field plate structure according to the disclosure at various stages in the fabrication thereof, the cross-sections being taken along lines IB- IB through 4B-4B, respectively;
  • FIG. 4B’ is a cross-sectional, diagrammatical sketch of a Field Effect Transistor having a field plate structure according to an alternative embodiment of the disclosure
  • FIG. 5 is a cross-sectional, diagrammatical sketch of the Field Effect Transistor having a field plate structure according to the disclosure fabricated in accordance with FIGS. 1A-1B through 4A-4B and configured as a common source amplifier;
  • FIG. 6 A is a plan view of an alternative embodiment of an ion implantation mask adapted for use in the fabrication of the Field Effect Transistor shown in FIGS. 4A and 4B;
  • FIG. 6B is a cross sectional view of the ion implantation mask of FIG. 6 A, such cross section being taken along line 6B-6B in FIG. 6A;
  • FIG. 7 A is a plan view of an alternative embodiment of an ion implantation mask adapted for use in the fabrication of the Field Effect Transistor shown in FIGS. 4A and 4B; and
  • FIG. 7B is a cross sectional view of the ion implantation mask of FIG. 7 A, such cross section being taken along line 7B-7B in FIG. 7A.
  • a mesa structure 10 is shown having a substrate 12, here for example, a semiconductor substrate such as gallium arsenide (GaAs), gallium nitride (GaN), silicon (Si), gallium oxide (Ga2Cb), or silicon carbide (SiC); a gallium nitride (GaN) buffer layer 14 on the substrate 12 and an aluminum gallium nitride (AlGaN) layer 16 on, and forming a heterojunction with, the GaN layer 14.
  • GaAs gallium arsenide
  • GaN gallium nitride
  • Si silicon
  • Ga2Cb gallium oxide
  • SiC silicon carbide
  • AlGaN aluminum gallium nitride
  • a source electrode 18 and a drain electrode 20 are in ohmic contact with the AlGaN layer 16 and a gate electrode 22, disposed between the source electrode 18 and drain electrode 20 is here in Schottky contact with the AlGaN layer 16, the gate electrode being used for controlling a flow of carriers between the source electrode 18 and the drain electrode 20 through a two-dimensional electron gas (2DEG) channel formed by the heterojunction.
  • 2DEG two-dimensional electron gas
  • a layer of dielectric material here silicon nitride (SiN x ), SiCk, AI2O3, or Ta O , for example, is formed over the surface of the structure by plasma enhanced chemical vapor deposition (PECVD), Low Pressure Chemical Vapor Deposition, for example, and patterned using conventional photolithography and etching processes to form a dielectric layer 24 over the surface as shown in FIG. 2B.
  • PECVD plasma enhanced chemical vapor deposition
  • Low Pressure Chemical Vapor Deposition for example
  • the layer 24 extends from a portion of the drain electrode 20, over the surface of the AlGaN layer 16 between the drain electrode 20 and the gate electrode 22, over the top and sides of the gate electrode 22 and then over the surface of the AlGaN layer 16 between the gate electrode 22 and the source electrode 18 and then over a portion of the source electrode 18 as shown. It should be noted that if the dielectric layer 24 is not of sufficient quality, a second dielectric layer 24’, can be deposited over the layer 24 for this purpose as will be described below in connection with FIG. 4B’.
  • a mask 28 having a window 30 therein is disposed over the upper surface of the structures as shown.
  • the distribution is uniform along the direction parallel to the surface of dielectric layer 24 and has a predetermined distribution in the depth of dielectric layer 24; here, for example, a Gaussian distribution having a peak at a predetermined depth into upper surface of dielectric layer 24.
  • ions are deposited into the region between drain and gate utilizing ion implantation of proper species (heavy ion to reduce diffusion in subsequent processing steps), charge (negative for n-channel transistors and positive for p-channel transistors, energy (low energy to create shallow layer in dielectric layer 24), and dose (sufficient dose to create the correct electrical potential of the self-biased field plate).
  • This charge (ions) is deposited utilizing mask 28, here a photolithographically defined mask, to restrict the region of implantation to the region between drain 20 and gate 22 without extending into the region between gate 22 and source 18 so as to eliminate any possible increase of the parasitic gate to source capacitance.
  • the window 30 need not be merely a simple open window to deposit the charge uniformly into layer 24, but may be modified to tailor the charge (ion) distribution and resultant semiconductor field such as a stipple of dots 30’ or stripes 30” as shown for masks 28’ and 28” in FIGS. 6 A and 6B and FIGS.7 A and 7B, respectively to create a diffraction-like grating pattern to tailor the charge distribution and resultant semiconductor field.
  • the apertures 30’ and 30” may be arranged in size and spacing to provide a graded charge distribution.
  • the charge 41 is deposited non-uniformly into the dielectric layer 24.
  • the masks 28’ or 28” provide a predetermined, non-uniform, distribution of ions along the surface of the dielectric layers 24 or 24'.
  • the correct ions to implant should be relatively large (slow thermal diffusion), such as negative ions Sr , Ba , Ra , and Ca , or positive ion of Cs + , and also be electrically stable to modify the semiconductor field over the expected device lifetime.
  • the correct energy would be somewhat low to create a shallow, well defined sheet charge; for example, in a range of 10-40 keV.
  • the correct dose would be determined through simulations and experiments and would depend on the masking method (rectangular or stippled); however, that dose would be on the order of lel3 ions/cm 2 to lei 5 ions/cm 2 .
  • the peak electric field at the drain side of the gate electrode is smaller than it would be if the device had been fabricated without the implanted ions.
  • the device is now capable of operating at higher voltages without its peak electric field exceeding an excessive or critical value.
  • FIG. 5 the Field Effect Transistor 40 structure shown in FIGS.
  • the ion-implanted region extends over a portion of the gate electrode 22 towards the drain electrode 20; it being noted that the ion- implanted region does not extend all the way to the drain electrode 20. It is noted that there is no annealing performed to neutralize the charge of the ions in the dielectric so that they remain charged in a floating configuration in the dielectric. It is noted that the ion implanted region is localized only in a region between the gate and drain in this common source transistor example, to eliminate source electrode side capacitance increase.
  • FIG. 4B SINGLE DIELECTRIC STRUCURE
  • Dielectric layer 24 thickness 60 to 150 nm
  • the implanted charge peak depth 5 to 20 nm into the upper surface of layer 24
  • Dielectric layer 24’ thickness 45 to 150 nm
  • Dielectric layer 24 would be thinner than layer 24’ in the double dielectric configuration for device reasons other than the implanted field plate, such as device passivation
  • the implanted charge peak depth 5 to 20 nm into the upper surface of layer 24’
  • a field effect transistor structure includes: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer on the surface of the semiconductor over the region between the gate and the drain; and fixed, immobile electric charge, having a predetermined distribution, disposed in the dielectric layer over the region between the gate and the drain.
  • the field effect transistor may include the following features, either individually or in combination, to include: wherein the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain; wherein the charge is electrically isolated from the source and drain; or wherein the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain.
  • a method for forming a field effect transistor includes: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor structure; forming a field plate comprising: providing a dielectric layer disposed on the surface of the semiconductor in regions between the source and the drain, such dielectric layer extending over the gate, and depositing electric ions disposed in portions of the dielectric layer from a source external of the semiconductor structure, a portion of such ions being disposed in the dielectric layer over an upper surface of the semiconductor structure, the charge extending over the region between the gate and the drain.
  • the method may include the feature wherein the charge is deposited with a predetermined distribution into the dielectric layer.
  • a field effect transistor includes: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; and a field plate comprising: a dielectric layer disposed on the surface of the semiconductor in a region between the source and the drain, the electric charge being disposed in a predetermined distribution in portions of the dielectric layer.
  • a field effect transistor includes: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a plurality of vertically stacked dielectric layers, an upper one of the vertically stacked dielectric layers having fixed, immobile electric charge disposed in portions thereof providing a field plate structure, the fixed, immobile charge solely providing the field plate structure shaping an electric field in a region between the gate and the drain of the field plate structure of the transistor, and wherein in the charge solely modifies the electric field in the transistor disposed on the surface of the semiconductor in regions between the source and the drain.
  • a method for forming a field effect transistor includes: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; providing a dielectric layer disposed on the surface of the semiconductor in a region between the gate and the drain; and depositing electric ions in portions of the dielectric layer between the gate and the drain.
  • the method may include the following features, either individually or in combination, to include: wherein the dielectric layer having the electric ions therein is electrically isolated from the source and drain or wherein the electric ions have a predetermined distribution in the dielectric layer.
  • a field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain includes: a dielectric layer disposed on the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, and wherein the electric charge solely produces the electric field.
  • a field effect transistor structure according to the disclosure includes: a field plate structure for producing an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and ion implanted electric charge disposed in portions of the dielectric layer.

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Abstract

A field effect transistor having a field plate structure for shaping an electric field in a region between the gate (22) and the drain (20), such field plate structure having: a dielectric layer (24) disposed on the gate and on the surface of the semiconductor in the region between the gate and the drain; and electric charge (41) disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the change extending from the upper surface of the gate into the region between gate and the drain; and wherein the electric charge solely produces the electric field.

Description

FIELD EFFECT TRANSISTOR HAVING FIELD PLATE
TECHNICAL FIELD
[0001] This disclosure relates generally to field effect transistors and more particularly to field effect transistors having field plate structures.
BACKGROUND OF THE INVENTION
[0002] As is known in the art, GaN-based Field Effect Transistor (FET) devices are capable of operating at much higher voltages than previous-generation devices based on GaAs or Si. Consequently, RF GaN devices can achieve much higher output powers with comparable power-added efficiencies. However, GaN-based devices still exhibit some challenges when operated at high voltages. During the off-state portion of the RF cycle (where the drain-to-gate voltage reaches a maximum), the electric field maximum located at the drain edge of the gate reaches an extreme level that is typically on the same order as the breakdown field strength of GaN (~3 MV/cm). This peak field has several negative consequences. First, carrier injection through the gate is greatly enhanced by the large electric field resulting in excessive leakage, which in turn can contribute to either pre mature device breakdown and/or catastrophic device failure. Second, field-enhanced trapping by surface states or traps in the buffer can lead to substantial DC/RF dispersion. DC/RF dispersion is characterized by the combination of “current collapse” (reduction of maximum current density under RF operation compared to its DC counterpart) and “knee walkout” (increased on-resistance of the transistor under RF operation compared to its DC counterpart). These deleterious electric field-induced effects counteract efforts to further improve output power or high-frequency performance by scaling the transistor laterally (smaller source-drain spacing) or by increasing its operating voltage.
[0003] Surface passivation with a dielectric, typically silicon nitride, has helped mitigate DC/RF dispersion at low-to-moderate voltage operation (typically < 25 V, depending on device geometry). However, difficulties are still encountered with device breakdown and DC/RF dispersion at higher voltages. Field plates have been developed in GaN devices to shape the electric field and reduce its peak value. Field plate structures made of thin film metals connected to the gate (gate connected field plate) or the source (source connected field plate) have helped not only to reduce DC/RF dispersion but also to reduce leakage and increase breakdown voltage. These performance improvements are possible because the field plate geometries are designed to better distribute the voltage drop between the gate and the drain and therefore reduce the peak electric field in the device. Minimizing the peak field in the device reduces leakage, reduces DC/RF dispersion, and enhances breakdown voltage. For these reasons, field plate features have been essential in designing RF GaN devices that operate at higher voltages and offer exceptional output powers and efficiencies.
[0004] However, conventional thin-film metal field plates have introduced a host of fabrication difficulties that include defect generation (from photolithography, metal deposition, and metal lift-off processes), poor metal step coverage of the field plate itself, poor dimensional control as a result of metal lift-off processes, and added topography that can impact subsequent processing. Aside from the fabrication difficulties, conventional field plates also increase parasitic gate and drain capacitances which in turn limit transistor gain and maximum operating frequency.
SUMMARY OF THE INVENTION
[0005] In accordance with the present disclosure, a field effect transistor structure is provided comprising a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, such electric charge solely producing the electric field.
[0006] In one embodiment, a field effect transistor structure is provided comprising a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and ion implanted electric charge disposed in portions of the dielectric layer. [0007] In one embodiment, a field effect transistor structure is provided comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer on the surface of the semiconductor over the region between the gate and the drain; and fixed, immobile electric charge, having a predetermined distribution, disposed in the dielectric layer over the region between the gate and the drain.
[0008] In one embodiment, the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain.
[0009] In one embodiment, the charge is electrically isolated from the source and drain.
[0010] In one embodiment, a method is provided for forming a field effect transistor, comprising: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor structure; forming a field plate, comprising: providing a dielectric layer disposed on the surface of the semiconductor in regions between the source and the drain, such dielectric layer extending over the gate; and depositing electric charge disposed in portions of the dielectric layer from a source external of the semiconductor structure, a portion of such charge being disposed in the dielectric layer over an upper surface of the semiconductor structure, the charge extending over the region between the gate and the drain.
[0011] In one embodiment, the charge is deposited with a predetermined distribution into the dielectric layer.
[0012] In one embodiment, a field effect transistor is provided, comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate comprising: a dielectric layer disposed on the surface of the semiconductor in a region between the source and the drain, the electric charge being disposed in a predetermined distribution in portions of the dielectric layer. [0013] In one embodiment, a field effect transistor is provided, comprising: a semiconductor; a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a plurality of vertically stacked dielectric layers, an upper one of the vertically stacked dielectric layers having fixed, immobile electric charge disposed in portions thereof providing a field plate structure, the fixed, immobile charge solely providing the field plate structure shaping an electric field in a region between the gate and the drain of the transistor, and wherein in the charge solely modifies the electric field in the region between the gate and drain of the transistor.
[0014] In one embodiment, a method is provided for forming a field effect transistor, comprising: providing a semiconductor structure having a source, a drain and a gate in contact with a corresponding portions of a surface of the semiconductor; providing a dielectric layer disposed on the surface of the semiconductor over a region between the gate and the drain; and depositing electric ions disposed in portions of the dielectric layer from a source external of the semiconductor structure into the dielectric layer between the gate and the drain.
[0015] In one embodiment, a second dielectric with more suitable material properties may be selectively or non-selectively disposed on the above structure. This second dielectric would extend over the gate; and fixed, immobile electric charge disposed in portions of the dielectric layer, a portion of such charge being disposed in the dielectric layer over an upper surface of the gate and another portion of the charge being disposed in the dielectric layer in the region extending from the upper surface of the gate to a location between the gate and the drain.
[0016] With such an arrangement, the charge in the dielectric layer effectively substitutes for a conventional thin-film metal field plate. The charged dielectric region acts as a self- biased field plate that can produce an electric field to modify the electric field distribution in the transistor and reduce the value of the maximum electric field. This style of field plate eliminates the fabrication and yield difficulties associated with conventional thin- film metal field plates. Introducing charge in the dielectric as described in these embodiments is done via ion implantation. This process involves accelerating ions from a source through an electric field directed into the sample, in this case our dielectric, changing its physical, chemical and/or electric properties. It is a process that is commonly used in semiconductor device fabrication. The ion implant dose and distribution can be adjusted to suit breakdown requirements and to achieve the desired electric field shaping. The ion implant species and implant technique can be selected to suit breakdown requirements and polarity. The ion implant provides very simplified processing to achieve similar field reduction.
[0017] The ion implant pattern, in another embodiment, can be created such that its aerial image will grade the dose implanted into the dielectric in such a way to effectively tilt or slant the field plate to achieve the desired electric field profile.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIGS. 1A-1B through 4A-4B are plan and cross-sectional, diagrammatical sketches of a Field Effect Transistor having a field plate structure according to the disclosure at various stages in the fabrication thereof, the cross-sections being taken along lines IB- IB through 4B-4B, respectively;
[0019] FIG. 4B’ is a cross-sectional, diagrammatical sketch of a Field Effect Transistor having a field plate structure according to an alternative embodiment of the disclosure;
[0020] FIG. 5 is a cross-sectional, diagrammatical sketch of the Field Effect Transistor having a field plate structure according to the disclosure fabricated in accordance with FIGS. 1A-1B through 4A-4B and configured as a common source amplifier;
[0021] FIG. 6 A is a plan view of an alternative embodiment of an ion implantation mask adapted for use in the fabrication of the Field Effect Transistor shown in FIGS. 4A and 4B;
[0022] FIG. 6B is a cross sectional view of the ion implantation mask of FIG. 6 A, such cross section being taken along line 6B-6B in FIG. 6A; [0023] FIG. 7 A is a plan view of an alternative embodiment of an ion implantation mask adapted for use in the fabrication of the Field Effect Transistor shown in FIGS. 4A and 4B; and
[0024] FIG. 7B is a cross sectional view of the ion implantation mask of FIG. 7 A, such cross section being taken along line 7B-7B in FIG. 7A.
[0025] Like reference symbols in the various drawings indicate like elements.
DETAILED DESCRIPTION
[0026] Referring now to FIGS. lAand IB, a mesa structure 10 is shown having a substrate 12, here for example, a semiconductor substrate such as gallium arsenide (GaAs), gallium nitride (GaN), silicon (Si), gallium oxide (Ga2Cb), or silicon carbide (SiC); a gallium nitride (GaN) buffer layer 14 on the substrate 12 and an aluminum gallium nitride (AlGaN) layer 16 on, and forming a heterojunction with, the GaN layer 14. A source electrode 18 and a drain electrode 20 are in ohmic contact with the AlGaN layer 16 and a gate electrode 22, disposed between the source electrode 18 and drain electrode 20 is here in Schottky contact with the AlGaN layer 16, the gate electrode being used for controlling a flow of carriers between the source electrode 18 and the drain electrode 20 through a two-dimensional electron gas (2DEG) channel formed by the heterojunction.
[0027] Referring now to FIGS. 2Aand 2B, a layer of dielectric material, here silicon nitride (SiNx), SiCk, AI2O3, or Ta O , for example, is formed over the surface of the structure by plasma enhanced chemical vapor deposition (PECVD), Low Pressure Chemical Vapor Deposition, for example, and patterned using conventional photolithography and etching processes to form a dielectric layer 24 over the surface as shown in FIG. 2B. The layer 24 extends from a portion of the drain electrode 20, over the surface of the AlGaN layer 16 between the drain electrode 20 and the gate electrode 22, over the top and sides of the gate electrode 22 and then over the surface of the AlGaN layer 16 between the gate electrode 22 and the source electrode 18 and then over a portion of the source electrode 18 as shown. It should be noted that if the dielectric layer 24 is not of sufficient quality, a second dielectric layer 24’, can be deposited over the layer 24 for this purpose as will be described below in connection with FIG. 4B’.
[0028] Continuing with FIGS. 3 A and 3B, a mask 28 having a window 30 therein is disposed over the upper surface of the structures as shown. Ions 41, (here negative charge indicated by the symbol (-) from a source 29 external to the semiconductor structure 10, here the source 29 is an ion implanter, are implanted via ion implantation into the portions of the dielectric layer 24 exposed by the window 30. Here, the distribution is uniform along the direction parallel to the surface of dielectric layer 24 and has a predetermined distribution in the depth of dielectric layer 24; here, for example, a Gaussian distribution having a peak at a predetermined depth into upper surface of dielectric layer 24. More particularly, ions are deposited into the region between drain and gate utilizing ion implantation of proper species (heavy ion to reduce diffusion in subsequent processing steps), charge (negative for n-channel transistors and positive for p-channel transistors, energy (low energy to create shallow layer in dielectric layer 24), and dose (sufficient dose to create the correct electrical potential of the self-biased field plate). This charge (ions) is deposited utilizing mask 28, here a photolithographically defined mask, to restrict the region of implantation to the region between drain 20 and gate 22 without extending into the region between gate 22 and source 18 so as to eliminate any possible increase of the parasitic gate to source capacitance.
[0029] The window 30 need not be merely a simple open window to deposit the charge uniformly into layer 24, but may be modified to tailor the charge (ion) distribution and resultant semiconductor field such as a stipple of dots 30’ or stripes 30” as shown for masks 28’ and 28” in FIGS. 6 A and 6B and FIGS.7 A and 7B, respectively to create a diffraction-like grating pattern to tailor the charge distribution and resultant semiconductor field. For example the apertures 30’ and 30” may be arranged in size and spacing to provide a graded charge distribution. Thus, the charge 41 is deposited non-uniformly into the dielectric layer 24. Thus, the masks 28’ or 28” provide a predetermined, non-uniform, distribution of ions along the surface of the dielectric layers 24 or 24'.
[0030] The correct ions to implant should be relatively large (slow thermal diffusion), such as negative ions Sr , Ba , Ra , and Ca , or positive ion of Cs+, and also be electrically stable to modify the semiconductor field over the expected device lifetime. The correct energy would be somewhat low to create a shallow, well defined sheet charge; for example, in a range of 10-40 keV. The correct dose would be determined through simulations and experiments and would depend on the masking method (rectangular or stippled); however, that dose would be on the order of lel3 ions/cm2 to lei 5 ions/cm2.
[0031] Referring to FIGS. 4 A and 4B, once the ions 41 are in place and the photolithographically defined mask 30 is removed, semiconductor processing is completed with the ion charge un-annealed and remaining in place to distribute the electric field in the gate to drain region. It should be noted that the electric field produced by the field plate structure 41 is provided solely by the electric ions 41 in the dielectric layer 24. It should also be noted that the process described above with regard to the ion implantation is not semiconductor doping, but rather charge implantation with the resulting implanted charge 41 creating an implanted dielectric field plate. When operating bias is applied to the resulting semiconductor device, the peak electric field at the drain side of the gate electrode is smaller than it would be if the device had been fabricated without the implanted ions. In this regard, the device is now capable of operating at higher voltages without its peak electric field exceeding an excessive or critical value.
[0032] Referring now to FIG. 5, the Field Effect Transistor 40 structure shown in FIGS.
4 A and 4B has a ground plane conductor 42 formed on the bottom of the substrate 12. The source electrode 18 is connected to a ground plane conductor 42 through a conductive via 44. The drain electrode 20 is connected to a positive voltage source +V through a resistor R and gate electrode 22 is connected to an RF input signal, as shown, to form a common source amplifier 48. It is noted that here, the ion-implanted region extends over a portion of the gate electrode 22 towards the drain electrode 20; it being noted that the ion- implanted region does not extend all the way to the drain electrode 20. It is noted that there is no annealing performed to neutralize the charge of the ions in the dielectric so that they remain charged in a floating configuration in the dielectric. It is noted that the ion implanted region is localized only in a region between the gate and drain in this common source transistor example, to eliminate source electrode side capacitance increase. EXAMPLES:
SINGLE DIELECTRIC STRUCURE FIG. 4B:
Dielectric layer 24 thickness: 60 to 150 nm
Charge is implanted with a Gaussian-like distribution to a maximum depth: 30 to 50 nm in layer 24
The implanted charge peak depth: 5 to 20 nm into the upper surface of layer 24
DOUBLE DIELECTRIC STRUCURE FIG. 4B’:
Dielectric layer 24’ thickness: 45 to 150 nm
Dielectric layer 24 would be thinner than layer 24’ in the double dielectric configuration for device reasons other than the implanted field plate, such as device passivation
Charge is implanted with a Gaussian-like distribution layer to a maximum depth:
30 to 50 nm in layer 24’
The implanted charge peak depth: 5 to 20 nm into the upper surface of layer 24’
[0033] It should now be appreciated a field effect transistor structure according to the disclosure includes: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer on the surface of the semiconductor over the region between the gate and the drain; and fixed, immobile electric charge, having a predetermined distribution, disposed in the dielectric layer over the region between the gate and the drain. The field effect transistor may include the following features, either individually or in combination, to include: wherein the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain; wherein the charge is electrically isolated from the source and drain; or wherein the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain.
[0034] It should now be appreciated a method for forming a field effect transistor according to the disclosure includes: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor structure; forming a field plate comprising: providing a dielectric layer disposed on the surface of the semiconductor in regions between the source and the drain, such dielectric layer extending over the gate, and depositing electric ions disposed in portions of the dielectric layer from a source external of the semiconductor structure, a portion of such ions being disposed in the dielectric layer over an upper surface of the semiconductor structure, the charge extending over the region between the gate and the drain. The method may include the feature wherein the charge is deposited with a predetermined distribution into the dielectric layer.
[0035] It should now also be appreciated a field effect transistor according to the disclosure includes: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; and a field plate comprising: a dielectric layer disposed on the surface of the semiconductor in a region between the source and the drain, the electric charge being disposed in a predetermined distribution in portions of the dielectric layer.
[0036] It should now also be appreciated a field effect transistor according to the disclosure includes: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a plurality of vertically stacked dielectric layers, an upper one of the vertically stacked dielectric layers having fixed, immobile electric charge disposed in portions thereof providing a field plate structure, the fixed, immobile charge solely providing the field plate structure shaping an electric field in a region between the gate and the drain of the field plate structure of the transistor, and wherein in the charge solely modifies the electric field in the transistor disposed on the surface of the semiconductor in regions between the source and the drain.
[0037] It should now also be appreciated a method for forming a field effect transistor according to the disclosure includes: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; providing a dielectric layer disposed on the surface of the semiconductor in a region between the gate and the drain; and depositing electric ions in portions of the dielectric layer between the gate and the drain. The method may include the following features, either individually or in combination, to include: wherein the dielectric layer having the electric ions therein is electrically isolated from the source and drain or wherein the electric ions have a predetermined distribution in the dielectric layer.
[0038] It should now also be appreciated a field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure according to the disclosure includes: a dielectric layer disposed on the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, and wherein the electric charge solely produces the electric field. [0039] It should now also be appreciated a field effect transistor structure according to the disclosure includes: a field plate structure for producing an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and ion implanted electric charge disposed in portions of the dielectric layer.
[0040] A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, other embodiments are within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:
1. A field effect transistor structure, comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer on the surface of the semiconductor over the region between the gate and the drain; fixed, immobile electric charge, having a predetermined distribution, disposed in the dielectric layer over the region between the gate and the drain.
2. The field effect transistor structure recited in claim 1 wherein the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain.
3. The field effect transistor structure recited in claim 1 wherein the charge is electrically isolated from the source and drain.
4. The field effect transistor structure recited in claim 3 wherein the fixed, immobile electric charge solely enables the field plate structure to shape the electric field in the region between the gate and the drain.
5. A method for forming a field effect transistor, comprising: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor structure; forming a field plate, comprising: providing a dielectric layer disposed on the surface of the semiconductor in regions between the source and the drain, such dielectric layer extending over the gate; depositing electric ions disposed in portions of the dielectric layer from a source external of the semiconductor structure, a portion of such ions being disposed in the dielectric layer over an upper surface of the semiconductor structure, the charge extending over the region between the gate and the drain.
6. The method recited in claim 5 wherein the charge is deposited with a predetermined distribution into the dielectric layer.
7. A field effect transistor, comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a field plate comprising: a dielectric layer disposed on the surface of the semiconductor in a region between the source and the drain, the electric charge being disposed in a predetermined distribution in portions of the dielectric layer.
8. A field effect transistor, comprising: a semiconductor having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; a plurality of vertically stacked dielectric layers, an upper one of the vertically stacked dielectric layers having fixed, immobile electric charge disposed in portions thereof providing a field plate structure, the fixed, immobile charge solely providing the field plate structure shaping an electric field in a region between the gate and the drain of the field plate structure of the transistor, and wherein in the charge solely modifies the electric field in the transistor disposed on the surface of the semiconductor in regions between the source and the drain.
9. A method for forming a field effect transistor, comprising: providing a semiconductor structure having a source, a drain and a gate in contact with corresponding portions of a surface of the semiconductor; providing a dielectric layer disposed on the surface of the semiconductor in a region between the gate and the drain; and depositing electric ions in portions of the dielectric layer between the gate and the drain.
10. The field effect transistor recited in claim 9 wherein the dielectric layer having the electric ions therein is electrically isolated from the source and drain.
11. The field effect transistor recited in claim 9 wherein the electric ions have a predetermined distribution in the dielectric layer.
12. A field effect transistor having a field plate structure for shaping an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on the region between gate and the drain; and electric charge disposed in portions of the dielectric layer, and wherein the electric charge solely produces the electric field.
13. A field effect transistor structure, comprising: a field plate structure for producing an electric field in a region between the gate and the drain, such field plate structure comprising: a dielectric layer disposed on gate and on the surface of the semiconductor in the region between gate and the drain; and ion implanted electric charge disposed in portions of the dielectric layer.
PCT/US2020/048323 2019-11-01 2020-08-28 Field effect transistor having field plate WO2021086484A1 (en)

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