US20100264486A1 - Field plate trench mosfet transistor with graded dielectric liner thickness - Google Patents
Field plate trench mosfet transistor with graded dielectric liner thickness Download PDFInfo
- Publication number
- US20100264486A1 US20100264486A1 US12/426,717 US42671709A US2010264486A1 US 20100264486 A1 US20100264486 A1 US 20100264486A1 US 42671709 A US42671709 A US 42671709A US 2010264486 A1 US2010264486 A1 US 2010264486A1
- Authority
- US
- United States
- Prior art keywords
- field plate
- dielectric
- forming
- thickness
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 claims description 87
- 239000000463 material Substances 0.000 claims description 25
- 239000000945 filler Substances 0.000 claims description 21
- 239000000758 substrate Substances 0.000 claims description 21
- 230000005684 electric field Effects 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims 3
- 230000008569 process Effects 0.000 description 60
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 5
- 238000010168 coupling process Methods 0.000 description 5
- 238000005859 coupling reaction Methods 0.000 description 5
- 235000012239 silicon dioxide Nutrition 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000006117 anti-reflective coating Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- VDRSDNINOSAWIV-UHFFFAOYSA-N [F].[Si] Chemical compound [F].[Si] VDRSDNINOSAWIV-UHFFFAOYSA-N 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 230000002301 combined effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66719—With a step of forming an insulating sidewall spacer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Definitions
- This application is directed, in general, to a semiconductor device and, more specifically, to an electronic device employing a vertical drift region.
- Trench field plate MOSFET transistors provide a vertical drift region architecture to reduce the area of the transistor.
- a general objective of MOSFET design is to minimize the specific on-resistance, R sp , of the transistor, e.g., the product of the device area A and its on-state resistance R on .
- R sp specific on-resistance
- a lower specific on-resistance results in lower area consumption and/or power dissipation during operation of the MOSFET.
- One aspect provides an electronic device that has a plurality of trenches formed in a semiconducting layer.
- a vertical drift region is located between and adjacent the trenches.
- An electrode is located within each trench, the trench having a gate electrode section and a field plate section.
- a graded field plate dielectric is located between the field plate section and the vertical drift region.
- the method includes providing a substrate that has a trench formed in a semiconductor layer.
- a gate dielectric is formed on a sidewall of the trench at a top portion thereof.
- a field plate dielectric is formed on the sidewall below the gate dielectric.
- the trench is filled with a field plate material.
- the field plate dielectric has a portion with a first thickness at a first depth of the trench, and a portion with a greater second thickness at a greater second depth of the trench.
- the MOSFET includes an epitaxial layer having a first conductivity type.
- a drain region is located in the epitaxial layer and has a second different conductivity type.
- a plurality of trenches is formed in the drain region.
- a polysilicon field plate is located within each of the trenches.
- An oxide field plate dielectric is located between each of the field plates and the drain region.
- a thickness of the oxide field plate liner is greater adjacent a bottom of the field plates than adjacent a top of the field plates.
- FIG. 1 is a prior art field plate trench MOSFET transistor
- FIG. 2 shows an embodiment of the disclosed MOSFET transistor
- FIGS. 3A-3C illustrate electric potential and electric field profiles
- FIGS. 4A-4J , 5 A, 5 B and 6 A- 6 F illustrate methods of forming embodiments of the disclosure.
- a trench field plate MOSFET includes a number of field plates formed within a drain extension region.
- the disclosure benefits from the recognition that operating characteristics of a trench field plate MOSFET may be improved by providing a dielectric between the field plates and the drain extension region that has a variable thickness therebetween.
- the variable thickness is expected to provide a flatter potential distribution in the direction of carrier flow during operation, resulting in increased blocking voltage, e.g.
- FIG. 1 illustrates a portion of a prior art trench field plate power MOSFET 100 (hereinafter referred to as the MOSFET 100 ). Coordinate axes are shown for reference.
- the illustrated portion includes a substrate 105 with a drain 110 and a drain extension 115 located thereover.
- a body 120 (sometimes referred to as a backgate) is located over the extension 115 , with a source 125 formed over the body 120 .
- the drain 110 , the extension 115 and the source 125 may be of a first conductivity type, e.g., n-doped, while the substrate 105 and the body 120 may be of a second conductivity type, e.g., p-doped.
- the drain 110 is doped with a higher dopant concentration, e.g., about 1E19 cm ⁇ 3 , than the extension 115 , e.g., about 1E16 cm 3 .
- the substrate 105 may be highly doped, e.g., n++ or p++ depending on the polarity of the MOSFET 100 .
- Each electrode 135 includes a gate electrode 140 and a field plate 145 .
- the plate 145 is that section of the electrode 135 below a neck region 150 in which the thickness of the electrode 135 decreases to the thickness T 1 of the plate 145 .
- a gate dielectric 155 is located between the electrode 140 and the body 120 , while a field plate dielectric 160 is located between the plate 145 and the extension 115 .
- the dielectric 160 has a relatively uniform thickness T 2 between the plate 145 and extension 115 .
- a unit cell 165 includes one-half of two adjacent electrodes 135 .
- the MOSFET 100 typically includes N unit cells extending in the ⁇ z direction and arranged, e.g., in a linear array.
- the extension 115 may be characterized as including a drain drift region 170 located between the plates 145 , the body 120 and the drain 110 .
- the region 170 is a region with a lower doping compared to the drain 110 , e.g., in which a drain-source voltage drop occurs during operation.
- the electrode 140 produces an inversion channel along the sidewalls of the trench 130 adjacent the body 120 , connecting the source 125 to the extension 115 .
- Charge carriers may flow in the region 170 in a generally vertical ( ⁇ y) direction.
- the region 170 may be regarded as a vertical drift region.
- the plate 145 may be used to modulate the carrier concentration in the region 170 .
- the region 170 is effectively depleted vertically by the body 120 and horizontally by the plate 145 .
- This horizontal depletion of the region 170 allows, for a given maximum drain-source voltage, a designer to increase the doping of the region 170 , or to reduce the thickness thereof. Either case reduces the device specific on-resistance compared to a vertical MOSFET that does not employ a trench field plate architecture.
- a maximum gate-drain voltage is reached at the bottom of the trench 130 , so that lateral depletion is maximum at this position.
- depletion is also important because of the combined effect of the body 120 and the plate 145 . As a result of these two affects, the potential drops faster at the top of the region 170 and the bottom of the trench 130 than in the vertical space therebetween.
- FIG. 3A a computed electric potential distribution within the unit cell 165 is shown.
- the spacing between electric equipotential lines along a path 310 is associated with the strength of an electric potential distribution there-along.
- the equipotential lines are initially relatively closely spaced, indicating a relatively high potential gradient, and are less closely spaced about midway along the path 310 , indicating a relatively low gradient.
- the gradient is again more relatively greater.
- FIG. 3C illustrates an electric field profile 320 associated with the potential distribution of FIG. 3A along the path 310 .
- the profile 320 is characterized by two local maxima associated with the beginning and end of the path 310 , and a local minimum about midway along the path 310 .
- the electric field at this minimum is only about half of the value at the maxima.
- a power MOSFET may be characterized by its blocking voltage, e.g., the voltage above which source-drain breakdown occurs.
- a higher blocking voltage is associated with a flatter electric field profile.
- the profile 320 is expected to be associated with a relatively low blocking voltage.
- MOSFET 200 trench field plate power MOSFET 200
- the MOSFET 200 includes a substrate 205 , drain 210 , drain extension 215 , a gate dielectric 220 , a body 225 and a source 230 , each of which may be conventional.
- Electrodes 235 are located in trenches 240 formed within the extension 215 .
- a unit cell 245 includes one-half of two adjacent electrodes 235 .
- Each electrode 235 includes a gate electrode 250 defined as that section of the electrode 235 above a neck region 255 below which the electrode 235 narrows.
- a section of the electrode 235 below the region 255 is defined as a field plate 260 .
- a drift region 265 is that region of the extension 215 between adjacent plates 260 .
- a field plate dielectric 270 is located between each plate 260 and the region 265 .
- the electrode 235 may comprise any conductive material.
- the electrode 235 is doped polysilicon.
- the electrode 235 is a metallic material, such as tungsten or copper.
- the electrode 235 may include a liner, such as, e.g., titanium, tantalum and/or a nitride of titanium or tantalum.
- the dielectric 270 has a nonuniform thickness over its vertical extent L.
- the field plate dielectric has a nonuniform thickness when its thickness varies by about 20% or more over its vertical extent adjacent the plate 260 .
- an upper section 275 has a thickness T 3
- a lower section 280 has a thickness T 4 that is greater than T 3 .
- Other embodiments may include, e.g., more than two portions of uniform width, or one or more portions having a nonuniform width, such as a taper from a lesser thickness to a greater thickness with increasing trench depth.
- a taper may be linear or nonlinear.
- the width is monotonic with increasing depth, e.g., the width does not decrease with depth at any location of the dielectric 270 .
- the dielectric 270 is thick enough at the bottom of the trench 240 to sustain the maximum drain-gate voltage expected at that location during device operation.
- the plate 260 has a nonuniform thickness that mirrors the nonuniform thickness of the dielectric 270 , e.g., becomes narrower with increasing depth of the trench 240 .
- the thickness of the field plate may have different profiles, e.g., a constant or increasing thickness, with increasing trench depth.
- FIG. 3B illustrates a computed electric potential distribution within the unit cell 245 for the nonlimiting case that the dielectric 270 includes two portions each having a different uniform thickness, e.g., such as illustrated in FIG. 2 .
- the electric field associated with the equipotential distribution along a path 330 is plotted in FIG. 3C as an electric field profile 340 .
- the profile 340 is characterized by two local maxima near the beginning and end point of the path 330 .
- the profile 340 is significantly more uniform than the profile 320 .
- the local minimum of the profile 320 is replaced in the profile 340 by two local minima and a local maximum, with the electric field at the minima being at least about 70% of the maximum value near the end points.
- the different thicknesses of the dielectric 270 provide a means to engineer a more uniform potential distribution in the region 265 by increasing the capacitive coupling of the plate 260 to the region 265 through thinner portions of the dielectric 270 than in the prior art case represented by FIG. 1 .
- the plate 260 Under high drain-source voltage, the plate 260 is expected to more efficiently deplete the region 265 than in the prior art MOSFET 100 . It is believed that by employing some of the embodiments of the disclosure, a nonuniformity of the electric field between the end points of path 330 , e.g., between the top and the bottom of the region 265 , may be limited to no greater than about 20%. In other cases, with careful design the nonuniformity of the electric field may be limited to no greater than about 10%. Use of numerical simulation techniques may guide the design of a field plate profile having desired nonuniformity characteristics.
- the dielectric 160 of the prior art MOSFET 100 has a single, uniform thickness.
- the thickness of the oxide below the region 150 is typically designed to resist breakdown in a region 350 (see FIG. 3A ) at the bottom of the trench where the electric field is high.
- the drain-source breakdown voltage Vb, and thus the blocking voltage of the MOSFET 100 is limited by the lack of depletion in the region 170 .
- the dielectric 270 has is a graded dielectric having at least two different thicknesses, such that the thickness of the dielectric 270 between the plate 260 and the region 265 increases in a stepwise or continuous manner toward the drain 210 .
- the term “graded field plate dielectric” includes both an abrupt and a gradual increase of thickness of the dielectric 270 by at least about 20% with increasing depth of the trench 240 .
- process conditions may result in a flare of the plate 260 near the bottom of the trench 240 . This flare may cause a portion of the dielectric 270 to thin with depth adjacent such a flared section of the plate 260 .
- the definition of “graded field plate dielectric” excludes the thinned portion.
- the novel configuration resulting from the graded field plate dielectric thickness is expected to result in an increased drain depletion effect and improved (e.g., more uniform) electric field distribution along the region 265 at a drain-source voltage close to a device maximum operating voltage and breakdown voltage.
- This configuration allows the thickness of the extension 215 to be reduced, or for the doping level of the extension 215 to be increased. In both cases, the device R sp may be reduced, and the constraints on R sp for a given V b may be relaxed.
- the device 400 may be any current or future-conceived electronic device using an architecture that includes a vertical plate electrode adjacent a drift region of a semiconductor substrate. Embodiments presented herein are illustrated without limitation using a power MOSFET as an example electronic device.
- a substrate 402 is provided with a semiconductor layer 404 thereover.
- “provided” means that a device, substrate, structural element, etc., may be manufactured by the individual or business entity performing the disclosed methods, or obtained thereby from a source other than the individual or entity, including another individual or business entity.
- the substrate may be as described previously, including, e.g., a highly doped buried semiconductor layer in contact with the layer 404 that functions as a drain.
- the layer 404 may be a crystalline semiconductor, and in some cases may be an epitaxial layer formed on a semiconductor substrate.
- the layer 404 is an epitaxial layer of a first conductivity type, e.g., n-type, and the substrate 402 is of an opposite second conductivity type, e.g., p-type, with a buried layer (not shown) of the first conductivity type located therebetween.
- the substrate 402 may include a buried oxide layer, such as semiconductor-on-insulator (SOI) or materials other than the primary elemental constituents of the layer 404 .
- SOI semiconductor-on-insulator
- the opening 408 may be formed conventionally.
- a hardmask 416 may be used to aid the definition of the opening 408 .
- a portion of the hardmask 416 may remain over the layer 404 , as illustrated.
- the hardmask 416 may be removed prior to the step illustrated by FIG. 4A .
- the opening 408 is formed using a Deep Reactive Ion Etch (DRIE) process alternating anisotropic etch and sidewall passivation, for example using silicon fluorine or chlorine based etchants and oxygen-based passivation.
- DRIE Deep Reactive Ion Etch
- a dielectric liner 420 is formed on the sidewall 412 .
- the liner 420 may be, e.g., a thermal oxide of the layer 404 , or other dielectric formed by, e.g., a chemical vapor deposition (CVD) process.
- the liner 420 may be deposited with any thickness consistent with a desired electrical potential distribution in the region 265 , e.g., and allowed by the width of the opening 408 , and the ability to fill the opening 408 with a field plate material at a later step.
- the opening 408 may be about 1.5 ⁇ m wide and 4 ⁇ m deep
- the liner 420 may be a thermal oxide with a thickness of about 600 nm.
- FIG. 4C illustrates the device 400 after forming a filler 424 in the opening 408 .
- the filler 424 may be any material that may be removed at a greater rate than the liner 420 , or at a lesser rate that the liner 420 , depending on conditions of the removal process. Nonlimiting examples include photoresist, an anti-reflective coating (ARC), silicon nitride and polysilicon.
- the filler 424 is completely removed in subsequent processing steps.
- the filler 424 is regarded as sacrificial.
- a portion of the filler 424 may be removed and a remaining portion left in the opening 408 . In such cases, it is preferred that the filler 424 be a conductive or semiconductive material such as, e.g., polysilicon.
- FIG. 4D illustrates the device 400 after a first portion of the filler 424 is removed by an etch process 428 .
- an etch process may be any process that is used to controllably remove a portion or an entirety of a material layer. Conventional processes are known to those skilled in the pertinent art to remove these example materials with selectivity to the liner 420 .
- An etch process may include dry (plasma) removal, wet removal, or a combination. It is understood by those skilled in the pertinent art that certain removal processes may include a subsequent clean step that may or may not result in additional removal of the target layer.
- the removing leaves a remaining portion 430 .
- a portion 432 of the liner 420 is uncovered by the process 428 .
- the process 428 may remove the first portion of the filler 424 at a greater rate than the liner 420 , and may also remove the first portion at a greater rate than the hardmask 416 when present.
- FIG. 4E illustrates the device 400 after removing the portion 432 , by, e.g., an isotropic etch process 436 .
- the process 436 may be configured to remove the portion 432 at a greater rate than the portion 430 .
- the process 436 may also be configured to result in a profile 440 of the surface of the liner 420 that is higher where the liner 420 meets the sidewall 412 than where the liner 420 meets the portion 430 , to produce a gradual dielectric thickness increase from top to bottom.
- a second portion of the filler 424 is removed by an etch process 444 .
- the removing leaves a remaining portion 450 .
- the process 444 may be a same process as the process 428 , e.g., the same tool, chemistry and clean, but need not be.
- the process 444 may be configured to remove the filler 424 at a greater rate than the liner 420 .
- the process 444 is configured to preserve the general characteristics of the profile 440 .
- the removing of the portion of the filler 424 results in an uncovered portion 448 of the liner 420 .
- FIG. 4G illustrates the device 400 after removing a portion of the liner 420 by an etch process 452 .
- the process 452 is an isotropic etch process.
- the process 452 may be configured to thin the portion 448 of the liner 420 while retaining the general characteristics of the profile 440 .
- the process 452 may optionally be configured to remove any remaining portions of the hardmask 416 , as illustrated in FIG. 4G .
- the portion 450 of the filler 424 is removed by an etch process 456 .
- the process 456 may be configured to be selective to the liner 420 , thus generally preserving the profile 440 .
- the profile of the liner 420 is configured to function as a field plate dielectric to cooperate with a field plate formed in a later process step to reduce nonuniformity of electric fields in a vertical drift region of the operational device 400 .
- the thickness of the liner 420 is graded such that it includes at least an upper portion 460 with a thickness 464 that is thinner than a lower portion 468 with a thickness 472 .
- the capacitive coupling between the later-formed field plate and the layer 404 is increased at the level of the portion 460 and the lateral drain extension depletion effect is increased relative to the ungraded case of the prior art MOSFET 100 .
- the thickness 472 of the liner 420 is at least about 20% greater than the thickness 464 of the portion 460 .
- a gate oxide layer 476 has been formed by, e.g., thermal oxidation.
- An electrode 478 is formed in the opening 408 .
- Conventional implant and anneal processes may be used to form a body 480 , a source 484 , and a body contact (not shown).
- the electrode 478 may be, e.g., a conventional conductive or semiconductive material such as described previously with respect to the electrode 235 .
- the electrode 478 may be formed by a conventional process that is designed to fill narrow or high aspect-ratio trenches. Such processes are known to those skilled in the pertinent arts, and may include several deposition and etch steps.
- the electrode 478 may include gaps and/or seams, generally it is preferred that such imperfections are minimized. When gaps do occur, such may optionally be filled by a dielectric such as a CVD oxide if the gap width is large enough.
- the electrode 478 may include a neck region 486 below which is located a field plate 488 having an upper region 492 and a lower region 494 .
- the layer 404 includes a drift region 496 .
- the regions 492 , 494 of the plate 488 have a width reduced by twice the thickness of the liner 420 adjacent each respective region 492 , 496 .
- the region 492 and the region 496 may each have different thickness that is substantially uniform.
- the width of the region 492 may be at least 20% greater than the width of the region 494 .
- the thickness profile of the liner 420 provides the aforementioned advantageous potential and electric field distribution in the region 496 .
- the plate 478 is expected to have a greater capacitive coupling to the region 496 where the liner 420 is thinner, e.g., the portion 460 , and a lower capacitive coupling where the liner 420 is thicker, e.g., the portion 468 .
- the process described by, e.g., FIGS. 4D though 4 H may be optionally repeated to form more than two dielectric liner portions of substantially uniform thickness.
- FIG. 4J illustrates an alternate embodiment of the device 400 having a field plate dielectric 497 , a gate electrode 498 and a field plate 499 .
- the dielectric 497 has a thickness that increases from top to bottom of the region 496 , but in a more continuous manner than for the liner 420 . In some cases, the dielectric 497 has a thickness that increases about linearly with depth adjacent the region 496 . Parameters such as chemistry, pressure, power and temperature of an etch process may be determined by those skilled in the etching arts to provide a more isotropic etch than the process 456 to result in the more linear profile of the dielectric 497 . The more linear profile of the dielectric 497 may provide a nearly uniform electric field over the region 496 in the direction of carrier flow.
- FIG. 5A illustrates, with continuing reference to FIG. 4G , a device 500 in which a dielectric layer 510 is formed over the portion 450 of the filler 424 .
- the layer 510 is formed on exposed portions of the liner 420 , the portion 450 and the layer 404 .
- the layer 510 may include a compound formed with the underlying composition, e.g., silicon dioxide over silicon or germanium dioxide over germanium.
- the layer 510 may be formed, e.g., by thermal oxidation or a CVD process.
- an upper electrode 520 has been formed over the layer 510 , and may be formed by the methods described with respect to the plate 488 .
- the electrode 520 and the portion 450 may act together as an electrode 570 .
- the combination of the electrode 520 below a neck region 530 , the portion 450 and the layer 510 therebetween constitutes a field plate 540 .
- the portion 450 may be referred to herein as the deep region of the plate 540
- the electrode 520 below the region 530 may be referred to as the shallow region of the plate 540 .
- Sources 550 and a body 560 may be formed in a conventional manner.
- the portion 450 is left electrically floating. In such cases, the portion 450 is capacitively coupled to the electrode 520 of the plate 540 by the layer 510 . In other embodiments a conductive path may be made between the electrode 520 and the portion 450 in later process steps that may be conventional. In one embodiment, a portion of the filler 424 is masked to remain unetched at one or more locations of the device 400 thereby providing a connection between the electrode 520 and the portion 450 .
- the portion 450 of the field plate is connected to a node different from the gate.
- the portion 450 may be connected to the power supply ground.
- capacitive loading on the channel is expected to be reduced.
- the parasitic capacitance between the layer 404 and the plate 540 may reduce the parasitic capacitance between the layer 404 and the plate 540 , relative to the configuration of FIG. 4I . Such a reduction of capacitance may allow a greater switching speed of the device 500 relative to the device 400 .
- FIGS. 6A-6H an alternate embodiment of forming an electronic device 600 is illustrated.
- a substrate 605 is provided with a semiconductor layer 610 thereover.
- the substrate 605 may be, e.g., a silicon handle wafer of a first conductivity type, and the layer 610 may be, e.g., an epitaxial layer having of a second conductivity type.
- the characteristics of the layer 610 may be as described for the layer 404 .
- a buried layer, not shown, of the second conductivity type, may be located between the layer 610 and the substrate 605 .
- the opening 615 may be one of a periodic array of such openings, such as, e.g., a linear array of trenches.
- the opening may be formed conventionally using, e.g., photoresist and plasma etch.
- a hard mask and/or antireflective coating (ARC), not shown, may optionally be used during formation of the opening 615 at an earlier process step.
- First mask layers 620 are located on the sidewalls of the opening 615 .
- the layers 620 are formed of a material that may be selectively removed at a later processing step without significantly eroding a later-formed field plate dielectric.
- the layers 620 may be silicon nitride or silicon oxynitride.
- the layers 620 may be formed by depositing a conformal layer of a spacer material by a CVD process. After deposition of the spacer material, the layer 610 may be exposed by removing the spacer material at the bottom of the opening 615 . Such removal may be done by an anisotropic etch such as, e.g., DRIE.
- etch process conditions appropriate for the pitch, density and depth of the opening 615 and neighboring openings (not shown).
- the device 600 has been further processed with an etch process 625 to remove an additional portion of the layer 610 .
- the removing may be done by a conventional DRIE process configured to selectively remove the layer 610 at a greater rate than other exposed material layers such as, e.g., photo resist or a hard mask.
- the additional removal of the layer 610 deepens the opening 615 to a depth D 2 .
- second mask layers 630 have been formed over the layer 620 and the sidewalls of the opening 615 exposed by the process 625 .
- the layers 630 may be conventionally formed as for the first mask layers, e.g., a conformal silicon nitride or silicon oxynitride layer followed by a DRIE etch.
- the layers 620 , 630 are formed of the same material, while in other cases they are formed of different materials.
- FIG. 6D illustrates the device 600 after an additional portion of the layer 610 has been removed at the bottom of the opening 615 by an etch process 635 .
- the removing results in a depth D 3 of the opening 615 .
- the process 635 process may be a DRIE process or other suitable anisotropic etch process.
- a first dielectric portion 640 has been formed on the sidewall of the opening 615 exposed by the process 635 .
- the formation process may be a conventional thermal oxidation, e.g.
- the forming process is configured to result in a thickness T 1 .
- the layers 630 are removed using a conventional process selective to the portion 640 .
- Those skilled in the pertinent art may configure an isotropic etch process, e.g., to remove the layers 630 at a greater rate than the portion 640 .
- a conventional etch process with high selectivity to silicon dioxide may remove the silicon nitride layers 630 . The removing exposes that portion of the sidewall of the opening 615 that was in contact with the layers 630 .
- the device 600 is illustrated in FIG. 6F after a second dielectric portion 645 has been formed on the sidewall of the opening 615 exposed by the removal of the layers 630 .
- the combined portions 640 , 645 are referred to as field plate dielectric 650 .
- the portion 645 may again be formed by a conventional thermal oxidation process.
- the forming process is configured to result in a thickness T 2 of the portion 645 .
- the portion 640 also typically becomes thicker during this thermal oxidation step, with a thickness T 3 .
- the thickness T 2 is about 300 nm
- the thickness T 3 is about 600 nm.
- One skilled in the pertinent art can determine appropriate process conditions to produce such thicknesses.
- a corner 655 at the step from the smaller to the larger width of the opening 615 can be rounded by the second substrate etch process.
- the oxide at the transition from the portion 640 to the portion 645 is expected to relatively smooth and defect-free.
- an electric field produced at the corner during operation of the completed device 600 will be reduced relative to the case of a sharper corner, and the dielectric adjacent the corner is expected to have a high breakdown strength.
- the dielectric 650 may be formed with more than one dielectric material layer.
- the dielectric 650 may include a layer of silicon dioxide and a layer of silicon nitride.
- a layer of CVD silicon nitride is formed over a layer of thermally grown oxide. Such a configuration may be advantageous when a greater capacitive coupling is desired between the plate 260 and the extension 215 (see FIG. 2 ).
- the layer 620 have been removed by an isotropic etch process that may, but need not be, the same process as that used to remove the layers 630 .
- the removing exposes the sidewall of the opening 615 in contact with the layer 620 .
- the device 600 is again exposed to a conventional thermal oxidation process.
- the oxidation process grows a gate oxide layer 660 that is a continuous extension of the dielectric 650 .
- a field plate 665 has been formed in the opening 615 .
- the plate 665 may have the same general characteristics of the plate 488 .
- the profile of the dielectric 650 is expected to result in a more uniform electric field distribution in a drift region 670 adjacent the dielectric 650 .
- the process sequence described by FIGS. 6B through 6F may be optionally repeated to form a greater number of liner thickness when desired. In some cases, such a configuration may result in greater uniformity of the electric field in the region 670 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
An electronic device has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.
Description
- This application is directed, in general, to a semiconductor device and, more specifically, to an electronic device employing a vertical drift region.
- Trench field plate MOSFET transistors provide a vertical drift region architecture to reduce the area of the transistor. A general objective of MOSFET design is to minimize the specific on-resistance, Rsp, of the transistor, e.g., the product of the device area A and its on-state resistance Ron. A lower specific on-resistance results in lower area consumption and/or power dissipation during operation of the MOSFET.
- One aspect provides an electronic device that has a plurality of trenches formed in a semiconducting layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the trench having a gate electrode section and a field plate section. A graded field plate dielectric is located between the field plate section and the vertical drift region.
- Another aspect provides a method of forming a vertical MOSFET. The method includes providing a substrate that has a trench formed in a semiconductor layer. A gate dielectric is formed on a sidewall of the trench at a top portion thereof. A field plate dielectric is formed on the sidewall below the gate dielectric. The trench is filled with a field plate material. The field plate dielectric has a portion with a first thickness at a first depth of the trench, and a portion with a greater second thickness at a greater second depth of the trench.
- Another aspect provides a vertical field plate trench MOSFET. The MOSFET includes an epitaxial layer having a first conductivity type. A drain region is located in the epitaxial layer and has a second different conductivity type. A plurality of trenches is formed in the drain region. A polysilicon field plate is located within each of the trenches. An oxide field plate dielectric is located between each of the field plates and the drain region. A thickness of the oxide field plate liner is greater adjacent a bottom of the field plates than adjacent a top of the field plates.
- In accordance with the standard practice in the semiconductor industry, various features of the accompanying drawings may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Furthermore, in certain embodiments, reference may be made to vertical or horizontal directions. No limitations regarding actual device orientation are implied by use of these directions. Such references take the horizontal direction to be generally parallel to an underlying substrate, and vertical to be generally normal to the horizontal direction. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
-
FIG. 1 is a prior art field plate trench MOSFET transistor; -
FIG. 2 shows an embodiment of the disclosed MOSFET transistor; -
FIGS. 3A-3C illustrate electric potential and electric field profiles; and -
FIGS. 4A-4J , 5A, 5B and 6A-6F illustrate methods of forming embodiments of the disclosure. - A trench field plate MOSFET includes a number of field plates formed within a drain extension region. The disclosure benefits from the recognition that operating characteristics of a trench field plate MOSFET may be improved by providing a dielectric between the field plates and the drain extension region that has a variable thickness therebetween. The variable thickness is expected to provide a flatter potential distribution in the direction of carrier flow during operation, resulting in increased blocking voltage, e.g.
-
FIG. 1 illustrates a portion of a prior art trench field plate power MOSFET 100 (hereinafter referred to as the MOSFET 100). Coordinate axes are shown for reference. The illustrated portion includes asubstrate 105 with adrain 110 and adrain extension 115 located thereover. A body 120 (sometimes referred to as a backgate) is located over theextension 115, with asource 125 formed over thebody 120. Thedrain 110, theextension 115 and thesource 125 may be of a first conductivity type, e.g., n-doped, while thesubstrate 105 and thebody 120 may be of a second conductivity type, e.g., p-doped. Typically, thedrain 110 is doped with a higher dopant concentration, e.g., about 1E19 cm−3, than theextension 115, e.g., about 1E16 cm3. Thesubstrate 105 may be highly doped, e.g., n++ or p++ depending on the polarity of theMOSFET 100. - Located within the
extension 115 aretrenches 130 withelectrodes 135 located therein. Eachelectrode 135 includes agate electrode 140 and afield plate 145. Theplate 145 is that section of theelectrode 135 below aneck region 150 in which the thickness of theelectrode 135 decreases to the thickness T1 of theplate 145. - A gate dielectric 155 is located between the
electrode 140 and thebody 120, while a field plate dielectric 160 is located between theplate 145 and theextension 115. The dielectric 160 has a relatively uniform thickness T2 between theplate 145 andextension 115. Aunit cell 165 includes one-half of twoadjacent electrodes 135. TheMOSFET 100 typically includes N unit cells extending in the ±z direction and arranged, e.g., in a linear array. - The
extension 115 may be characterized as including adrain drift region 170 located between theplates 145, thebody 120 and thedrain 110. Theregion 170 is a region with a lower doping compared to thedrain 110, e.g., in which a drain-source voltage drop occurs during operation. Under appropriate bias conditions, theelectrode 140 produces an inversion channel along the sidewalls of thetrench 130 adjacent thebody 120, connecting thesource 125 to theextension 115. Charge carriers may flow in theregion 170 in a generally vertical (±y) direction. Thus, theregion 170 may be regarded as a vertical drift region. - The
plate 145 may be used to modulate the carrier concentration in theregion 170. Under high drain voltage, theregion 170 is effectively depleted vertically by thebody 120 and horizontally by theplate 145. This horizontal depletion of theregion 170 allows, for a given maximum drain-source voltage, a designer to increase the doping of theregion 170, or to reduce the thickness thereof. Either case reduces the device specific on-resistance compared to a vertical MOSFET that does not employ a trench field plate architecture. - Under some operating conditions, e.g., a sufficiently large drain voltage, a maximum gate-drain voltage is reached at the bottom of the
trench 130, so that lateral depletion is maximum at this position. At the top of theregion 170, depletion is also important because of the combined effect of thebody 120 and theplate 145. As a result of these two affects, the potential drops faster at the top of theregion 170 and the bottom of thetrench 130 than in the vertical space therebetween. - These effects are illustrated in
FIG. 3A , in which a computed electric potential distribution within theunit cell 165 is shown. The spacing between electric equipotential lines along apath 310 is associated with the strength of an electric potential distribution there-along. The equipotential lines are initially relatively closely spaced, indicating a relatively high potential gradient, and are less closely spaced about midway along thepath 310, indicating a relatively low gradient. Towards the end of thepath 310, the gradient is again more relatively greater. -
FIG. 3C illustrates anelectric field profile 320 associated with the potential distribution ofFIG. 3A along thepath 310. Theprofile 320 is characterized by two local maxima associated with the beginning and end of thepath 310, and a local minimum about midway along thepath 310. The electric field at this minimum is only about half of the value at the maxima. - A power MOSFET may be characterized by its blocking voltage, e.g., the voltage above which source-drain breakdown occurs. A higher blocking voltage is associated with a flatter electric field profile. Thus, the
profile 320 is expected to be associated with a relatively low blocking voltage. - Turning to
FIG. 2 , illustrated is a trench field plate power MOSFET 200 (hereinafter MOSFET 200) according to the disclosure. TheMOSFET 200 includes asubstrate 205, drain 210,drain extension 215, agate dielectric 220, abody 225 and asource 230, each of which may be conventional.Electrodes 235 are located intrenches 240 formed within theextension 215. Aunit cell 245 includes one-half of twoadjacent electrodes 235. Eachelectrode 235 includes agate electrode 250 defined as that section of theelectrode 235 above aneck region 255 below which theelectrode 235 narrows. A section of theelectrode 235 below theregion 255 is defined as afield plate 260. Adrift region 265 is that region of theextension 215 betweenadjacent plates 260. Afield plate dielectric 270 is located between eachplate 260 and theregion 265. - The
electrode 235 may comprise any conductive material. In one embodiment, theelectrode 235 is doped polysilicon. In another embodiment, theelectrode 235 is a metallic material, such as tungsten or copper. In some embodiments, theelectrode 235 may include a liner, such as, e.g., titanium, tantalum and/or a nitride of titanium or tantalum. - The dielectric 270 has a nonuniform thickness over its vertical extent L. As used herein, the field plate dielectric has a nonuniform thickness when its thickness varies by about 20% or more over its vertical extent adjacent the
plate 260. In the illustrated embodiment, anupper section 275 has a thickness T3, and alower section 280 has a thickness T4 that is greater than T3. Other embodiments may include, e.g., more than two portions of uniform width, or one or more portions having a nonuniform width, such as a taper from a lesser thickness to a greater thickness with increasing trench depth. A taper may be linear or nonlinear. In some embodiments, the width is monotonic with increasing depth, e.g., the width does not decrease with depth at any location of the dielectric 270. In some preferred embodiments, the dielectric 270 is thick enough at the bottom of thetrench 240 to sustain the maximum drain-gate voltage expected at that location during device operation. - In the illustrated embodiment, the
plate 260 has a nonuniform thickness that mirrors the nonuniform thickness of the dielectric 270, e.g., becomes narrower with increasing depth of thetrench 240. In other embodiments, the thickness of the field plate may have different profiles, e.g., a constant or increasing thickness, with increasing trench depth. -
FIG. 3B illustrates a computed electric potential distribution within theunit cell 245 for the nonlimiting case that the dielectric 270 includes two portions each having a different uniform thickness, e.g., such as illustrated inFIG. 2 . The electric field associated with the equipotential distribution along apath 330 is plotted inFIG. 3C as anelectric field profile 340. As was described for theprofile 320, theprofile 340 is characterized by two local maxima near the beginning and end point of thepath 330. However, theprofile 340 is significantly more uniform than theprofile 320. The local minimum of theprofile 320 is replaced in theprofile 340 by two local minima and a local maximum, with the electric field at the minima being at least about 70% of the maximum value near the end points. The different thicknesses of the dielectric 270 provide a means to engineer a more uniform potential distribution in theregion 265 by increasing the capacitive coupling of theplate 260 to theregion 265 through thinner portions of the dielectric 270 than in the prior art case represented byFIG. 1 . Under high drain-source voltage, theplate 260 is expected to more efficiently deplete theregion 265 than in theprior art MOSFET 100. It is believed that by employing some of the embodiments of the disclosure, a nonuniformity of the electric field between the end points ofpath 330, e.g., between the top and the bottom of theregion 265, may be limited to no greater than about 20%. In other cases, with careful design the nonuniformity of the electric field may be limited to no greater than about 10%. Use of numerical simulation techniques may guide the design of a field plate profile having desired nonuniformity characteristics. - The dielectric 160 of the
prior art MOSFET 100 has a single, uniform thickness. The thickness of the oxide below theregion 150 is typically designed to resist breakdown in a region 350 (seeFIG. 3A ) at the bottom of the trench where the electric field is high. The drain-source breakdown voltage Vb, and thus the blocking voltage of theMOSFET 100 is limited by the lack of depletion in theregion 170. - In contrast to the
prior art MOSFET 100, in a device of the disclosure, e.g., theMOSFET 200, the dielectric 270 has is a graded dielectric having at least two different thicknesses, such that the thickness of the dielectric 270 between theplate 260 and theregion 265 increases in a stepwise or continuous manner toward thedrain 210. As used herein, the term “graded field plate dielectric” includes both an abrupt and a gradual increase of thickness of the dielectric 270 by at least about 20% with increasing depth of thetrench 240. In some cases, process conditions may result in a flare of theplate 260 near the bottom of thetrench 240. This flare may cause a portion of the dielectric 270 to thin with depth adjacent such a flared section of theplate 260. In such cases, the definition of “graded field plate dielectric” excludes the thinned portion. - The novel configuration resulting from the graded field plate dielectric thickness is expected to result in an increased drain depletion effect and improved (e.g., more uniform) electric field distribution along the
region 265 at a drain-source voltage close to a device maximum operating voltage and breakdown voltage. This configuration allows the thickness of theextension 215 to be reduced, or for the doping level of theextension 215 to be increased. In both cases, the device Rsp may be reduced, and the constraints on Rsp for a given Vb may be relaxed. - Turning to
FIG. 4A , one embodiment of a method of forming anelectronic device 400 is illustrated. Thedevice 400 may be any current or future-conceived electronic device using an architecture that includes a vertical plate electrode adjacent a drift region of a semiconductor substrate. Embodiments presented herein are illustrated without limitation using a power MOSFET as an example electronic device. InFIG. 4A , asubstrate 402 is provided with asemiconductor layer 404 thereover. Herein, “provided” means that a device, substrate, structural element, etc., may be manufactured by the individual or business entity performing the disclosed methods, or obtained thereby from a source other than the individual or entity, including another individual or business entity. - An
opening 408 with a sidewall 412 is formed within thelayer 404. The substrate may be as described previously, including, e.g., a highly doped buried semiconductor layer in contact with thelayer 404 that functions as a drain. Thelayer 404 may be a crystalline semiconductor, and in some cases may be an epitaxial layer formed on a semiconductor substrate. In one embodiment, thelayer 404 is an epitaxial layer of a first conductivity type, e.g., n-type, and thesubstrate 402 is of an opposite second conductivity type, e.g., p-type, with a buried layer (not shown) of the first conductivity type located therebetween. Thesubstrate 402 may include a buried oxide layer, such as semiconductor-on-insulator (SOI) or materials other than the primary elemental constituents of thelayer 404. - The
opening 408 may be formed conventionally. In some embodiments, ahardmask 416 may be used to aid the definition of theopening 408. In some cases, a portion of thehardmask 416 may remain over thelayer 404, as illustrated. In other embodiments, thehardmask 416 may be removed prior to the step illustrated byFIG. 4A . In some embodiments, theopening 408 is formed using a Deep Reactive Ion Etch (DRIE) process alternating anisotropic etch and sidewall passivation, for example using silicon fluorine or chlorine based etchants and oxygen-based passivation. Those skilled in the pertinent art are knowledgeable about forming openings such as theopening 408. - In
FIG. 4B , adielectric liner 420 is formed on the sidewall 412. Theliner 420 may be, e.g., a thermal oxide of thelayer 404, or other dielectric formed by, e.g., a chemical vapor deposition (CVD) process. Theliner 420 may be deposited with any thickness consistent with a desired electrical potential distribution in theregion 265, e.g., and allowed by the width of theopening 408, and the ability to fill theopening 408 with a field plate material at a later step. In an example embodiment, theopening 408 may be about 1.5 μm wide and 4 μm deep, and theliner 420 may be a thermal oxide with a thickness of about 600 nm. -
FIG. 4C illustrates thedevice 400 after forming afiller 424 in theopening 408. Thefiller 424 may be any material that may be removed at a greater rate than theliner 420, or at a lesser rate that theliner 420, depending on conditions of the removal process. Nonlimiting examples include photoresist, an anti-reflective coating (ARC), silicon nitride and polysilicon. In some embodiments, thefiller 424 is completely removed in subsequent processing steps. In this context, thefiller 424 is regarded as sacrificial. In some embodiments, as described below, a portion of thefiller 424 may be removed and a remaining portion left in theopening 408. In such cases, it is preferred that thefiller 424 be a conductive or semiconductive material such as, e.g., polysilicon. -
FIG. 4D illustrates thedevice 400 after a first portion of thefiller 424 is removed by anetch process 428. As used herein, an etch process may be any process that is used to controllably remove a portion or an entirety of a material layer. Conventional processes are known to those skilled in the pertinent art to remove these example materials with selectivity to theliner 420. An etch process may include dry (plasma) removal, wet removal, or a combination. It is understood by those skilled in the pertinent art that certain removal processes may include a subsequent clean step that may or may not result in additional removal of the target layer. InFIG. 4D , the removing leaves a remainingportion 430. Aportion 432 of theliner 420 is uncovered by theprocess 428. Theprocess 428 may remove the first portion of thefiller 424 at a greater rate than theliner 420, and may also remove the first portion at a greater rate than thehardmask 416 when present. -
FIG. 4E illustrates thedevice 400 after removing theportion 432, by, e.g., anisotropic etch process 436. Theprocess 436 may be configured to remove theportion 432 at a greater rate than theportion 430. Theprocess 436 may also be configured to result in aprofile 440 of the surface of theliner 420 that is higher where theliner 420 meets the sidewall 412 than where theliner 420 meets theportion 430, to produce a gradual dielectric thickness increase from top to bottom. - In
FIG. 4F , a second portion of thefiller 424 is removed by anetch process 444. The removing leaves a remainingportion 450. Theprocess 444 may be a same process as theprocess 428, e.g., the same tool, chemistry and clean, but need not be. Theprocess 444 may be configured to remove thefiller 424 at a greater rate than theliner 420. In some embodiments, theprocess 444 is configured to preserve the general characteristics of theprofile 440. The removing of the portion of thefiller 424 results in an uncoveredportion 448 of theliner 420. -
FIG. 4G illustrates thedevice 400 after removing a portion of theliner 420 by anetch process 452. In some embodiments, theprocess 452 is an isotropic etch process. Theprocess 452 may be configured to thin theportion 448 of theliner 420 while retaining the general characteristics of theprofile 440. Theprocess 452 may optionally be configured to remove any remaining portions of thehardmask 416, as illustrated inFIG. 4G . - In
FIG. 4H , theportion 450 of thefiller 424 is removed by anetch process 456. Theprocess 456 may be configured to be selective to theliner 420, thus generally preserving theprofile 440. - The profile of the
liner 420 is configured to function as a field plate dielectric to cooperate with a field plate formed in a later process step to reduce nonuniformity of electric fields in a vertical drift region of theoperational device 400. In particular, the thickness of theliner 420 is graded such that it includes at least anupper portion 460 with athickness 464 that is thinner than alower portion 468 with athickness 472. As a result, the capacitive coupling between the later-formed field plate and thelayer 404 is increased at the level of theportion 460 and the lateral drain extension depletion effect is increased relative to the ungraded case of theprior art MOSFET 100. In some embodiments, thethickness 472 of theliner 420 is at least about 20% greater than thethickness 464 of theportion 460. - In
FIG. 4I , agate oxide layer 476 has been formed by, e.g., thermal oxidation. Anelectrode 478 is formed in theopening 408. Conventional implant and anneal processes may be used to form abody 480, asource 484, and a body contact (not shown). Theelectrode 478 may be, e.g., a conventional conductive or semiconductive material such as described previously with respect to theelectrode 235. Theelectrode 478 may be formed by a conventional process that is designed to fill narrow or high aspect-ratio trenches. Such processes are known to those skilled in the pertinent arts, and may include several deposition and etch steps. While embodiments of theelectrode 478 may include gaps and/or seams, generally it is preferred that such imperfections are minimized. When gaps do occur, such may optionally be filled by a dielectric such as a CVD oxide if the gap width is large enough. Theelectrode 478 may include aneck region 486 below which is located afield plate 488 having anupper region 492 and alower region 494. - The
layer 404 includes adrift region 496. Theregions plate 488 have a width reduced by twice the thickness of theliner 420 adjacent eachrespective region region 492 and theregion 496 may each have different thickness that is substantially uniform. The width of theregion 492 may be at least 20% greater than the width of theregion 494. - The thickness profile of the
liner 420 provides the aforementioned advantageous potential and electric field distribution in theregion 496. In particular, theplate 478 is expected to have a greater capacitive coupling to theregion 496 where theliner 420 is thinner, e.g., theportion 460, and a lower capacitive coupling where theliner 420 is thicker, e.g., theportion 468. In some embodiments, the process described by, e.g.,FIGS. 4D though 4H may be optionally repeated to form more than two dielectric liner portions of substantially uniform thickness. -
FIG. 4J illustrates an alternate embodiment of thedevice 400 having afield plate dielectric 497, agate electrode 498 and afield plate 499. The dielectric 497 has a thickness that increases from top to bottom of theregion 496, but in a more continuous manner than for theliner 420. In some cases, the dielectric 497 has a thickness that increases about linearly with depth adjacent theregion 496. Parameters such as chemistry, pressure, power and temperature of an etch process may be determined by those skilled in the etching arts to provide a more isotropic etch than theprocess 456 to result in the more linear profile of the dielectric 497. The more linear profile of the dielectric 497 may provide a nearly uniform electric field over theregion 496 in the direction of carrier flow. -
FIG. 5A illustrates, with continuing reference toFIG. 4G , adevice 500 in which adielectric layer 510 is formed over theportion 450 of thefiller 424. Starting from thedevice 400 processed throughFIG. 4G , thelayer 510 is formed on exposed portions of theliner 420, theportion 450 and thelayer 404. Thelayer 510 may include a compound formed with the underlying composition, e.g., silicon dioxide over silicon or germanium dioxide over germanium. Thelayer 510 may be formed, e.g., by thermal oxidation or a CVD process. - In
FIG. 5B , anupper electrode 520 has been formed over thelayer 510, and may be formed by the methods described with respect to theplate 488. Theelectrode 520 and theportion 450 may act together as anelectrode 570. The combination of theelectrode 520 below aneck region 530, theportion 450 and thelayer 510 therebetween constitutes afield plate 540. In this context, theportion 450 may be referred to herein as the deep region of theplate 540, and theelectrode 520 below theregion 530 may be referred to as the shallow region of theplate 540.Sources 550 and abody 560 may be formed in a conventional manner. - In some embodiments, the
portion 450 is left electrically floating. In such cases, theportion 450 is capacitively coupled to theelectrode 520 of theplate 540 by thelayer 510. In other embodiments a conductive path may be made between theelectrode 520 and theportion 450 in later process steps that may be conventional. In one embodiment, a portion of thefiller 424 is masked to remain unetched at one or more locations of thedevice 400 thereby providing a connection between theelectrode 520 and theportion 450. - In some embodiments, the
portion 450 of the field plate is connected to a node different from the gate. For example, to reduce gate-to-drain capacitance it may be advantageous to connect theportion 450 to a voltage node other than the gate. For example, theportion 450 may be connected to the power supply ground. In this case, capacitive loading on the channel is expected to be reduced. Thus, when the drain or the gate is switched from one voltage state to another, charging effects that may slow channel operation are expected to be reduced relative to the case in which theportion 450 is not grounded. It is expected that these and similar embodiments may reduce the parasitic capacitance between thelayer 404 and theplate 540, relative to the configuration ofFIG. 4I . Such a reduction of capacitance may allow a greater switching speed of thedevice 500 relative to thedevice 400. - Turning to
FIGS. 6A-6H , an alternate embodiment of forming anelectronic device 600 is illustrated. InFIG. 6A , asubstrate 605 is provided with asemiconductor layer 610 thereover. Thesubstrate 605 may be, e.g., a silicon handle wafer of a first conductivity type, and thelayer 610 may be, e.g., an epitaxial layer having of a second conductivity type. The characteristics of thelayer 610 may be as described for thelayer 404. A buried layer, not shown, of the second conductivity type, may be located between thelayer 610 and thesubstrate 605. - An
opening 615 with a depth D1 is formed in thelayer 610. Theopening 615 may be one of a periodic array of such openings, such as, e.g., a linear array of trenches. The opening may be formed conventionally using, e.g., photoresist and plasma etch. A hard mask and/or antireflective coating (ARC), not shown, may optionally be used during formation of theopening 615 at an earlier process step. - First mask layers 620 are located on the sidewalls of the
opening 615. Thelayers 620 are formed of a material that may be selectively removed at a later processing step without significantly eroding a later-formed field plate dielectric. In a nonlimiting example, when the field plate dielectric is silicon dioxide, thelayers 620 may be silicon nitride or silicon oxynitride. Thelayers 620 may be formed by depositing a conformal layer of a spacer material by a CVD process. After deposition of the spacer material, thelayer 610 may be exposed by removing the spacer material at the bottom of theopening 615. Such removal may be done by an anisotropic etch such as, e.g., DRIE. Those skilled in the pertinent art may determine etch process conditions appropriate for the pitch, density and depth of theopening 615 and neighboring openings (not shown). - In
FIG. 6B , thedevice 600 has been further processed with anetch process 625 to remove an additional portion of thelayer 610. The removing may be done by a conventional DRIE process configured to selectively remove thelayer 610 at a greater rate than other exposed material layers such as, e.g., photo resist or a hard mask. The additional removal of thelayer 610 deepens theopening 615 to a depth D2. - In
FIG. 6C , second mask layers 630 have been formed over thelayer 620 and the sidewalls of theopening 615 exposed by theprocess 625. Thelayers 630 may be conventionally formed as for the first mask layers, e.g., a conformal silicon nitride or silicon oxynitride layer followed by a DRIE etch. In some cases, thelayers -
FIG. 6D illustrates thedevice 600 after an additional portion of thelayer 610 has been removed at the bottom of theopening 615 by anetch process 635. The removing results in a depth D3 of theopening 615. Theprocess 635 process may be a DRIE process or other suitable anisotropic etch process. - In
FIG. 6E , a firstdielectric portion 640 has been formed on the sidewall of theopening 615 exposed by theprocess 635. The formation process may be a conventional thermal oxidation, e.g. The forming process is configured to result in a thickness T1. After forming theportion 640, thelayers 630 are removed using a conventional process selective to theportion 640. Those skilled in the pertinent art may configure an isotropic etch process, e.g., to remove thelayers 630 at a greater rate than theportion 640. For example, when thelayers 630 are formed of silicon nitride and theportion 640 is formed of silicon dioxide, a conventional etch process with high selectivity to silicon dioxide may remove the silicon nitride layers 630. The removing exposes that portion of the sidewall of theopening 615 that was in contact with thelayers 630. - The
device 600 is illustrated inFIG. 6F after a seconddielectric portion 645 has been formed on the sidewall of theopening 615 exposed by the removal of thelayers 630. The combinedportions field plate dielectric 650. Theportion 645 may again be formed by a conventional thermal oxidation process. The forming process is configured to result in a thickness T2 of theportion 645. Theportion 640 also typically becomes thicker during this thermal oxidation step, with a thickness T3. In an example embodiment, the thickness T2 is about 300 nm, and the thickness T3 is about 600 nm. One skilled in the pertinent art can determine appropriate process conditions to produce such thicknesses. - A
corner 655 at the step from the smaller to the larger width of theopening 615 can be rounded by the second substrate etch process. With appropriate choice of the spacer and spacer thickness, the oxide at the transition from theportion 640 to theportion 645 is expected to relatively smooth and defect-free. Thus, an electric field produced at the corner during operation of the completeddevice 600 will be reduced relative to the case of a sharper corner, and the dielectric adjacent the corner is expected to have a high breakdown strength. - In some embodiments, the dielectric 650 may be formed with more than one dielectric material layer. For example, the dielectric 650 may include a layer of silicon dioxide and a layer of silicon nitride. In one embodiment, a layer of CVD silicon nitride is formed over a layer of thermally grown oxide. Such a configuration may be advantageous when a greater capacitive coupling is desired between the
plate 260 and the extension 215 (seeFIG. 2 ). - Turning to
FIG. 6G , thelayer 620 have been removed by an isotropic etch process that may, but need not be, the same process as that used to remove thelayers 630. The removing exposes the sidewall of theopening 615 in contact with thelayer 620. Thedevice 600 is again exposed to a conventional thermal oxidation process. The oxidation process grows agate oxide layer 660 that is a continuous extension of the dielectric 650. - In
FIG. 6H , afield plate 665 has been formed in theopening 615. Theplate 665 may have the same general characteristics of theplate 488. As was described with respect to theelectronic device 400, the profile of the dielectric 650 is expected to result in a more uniform electric field distribution in adrift region 670 adjacent the dielectric 650. The process sequence described byFIGS. 6B through 6F may be optionally repeated to form a greater number of liner thickness when desired. In some cases, such a configuration may result in greater uniformity of the electric field in theregion 670. - Those skilled in the art to which this application relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments.
Claims (28)
1. An electronic device, comprising:
a plurality of trenches located within a semiconducting layer;
a vertical drift region between and adjacent said trenches;
an electrode located within each trench, said electrode having a gate electrode section and a field plate section; and
a graded field plate dielectric located between said field plate section and said vertical drift section.
2. The electronic device recited in claim 1 , wherein said second thickness is at least about 20% greater than said first thickness.
3. The electronic device recited in claim 1 , wherein a thickness of said field plate dielectric increases about linearly with increasing depth of said trench.
4. The electronic device recited in claim 1 , wherein a thickness of said field plate dielectric increases in a stepwise fashion from said top of said field plate to said bottom of said field plate.
5. The electronic device recited in claim 1 , wherein said field plate includes two or more regions, each region having a substantially uniform thickness.
6. The electronic device recited in claim 1 , wherein an electric field in said drift region in varies by less than about 30% of a maximum value in a direction parallel to said field plate.
7. The electronic device recited in claim 1 , further comprising an insulating layer located between a deep section of said field plate and a shallow section of said field plate.
8. The electronic device recited in claim 1 , wherein said field plate comprises polycrystalline silicon.
9. A method of forming a vertical MOSFET, comprising:
providing a semiconductor layer over a substrate, said semiconductor layer having a trench formed therein;
forming a gate dielectric on a top portion of a sidewall of said trench;
forming a field plate dielectric on a bottom portion of said sidewall, said field plate dielectric having a first portion with a first thickness at a first depth of said trench, and a second portion with a greater second thickness at a greater second depth of said trench, and
filling said trench with a field plate material.
10. The method recited in claim 9 , wherein forming said field plate dielectric comprises removing a portion of a dielectric layer formed over said sidewall.
11. The method recited in claim 10 , wherein forming said field plate dielectric further comprises removing a portion of a filler material thereby exposing said removed portion of said dielectric layer.
12. The method recited in claim 9 , wherein forming said field plate dielectric includes forming a mask layer over a portion of said sidewall that blocks formation of a dielectric layer on said sidewall.
13. The method recited in claim 9 , wherein forming said field plate dielectric comprises:
forming a dielectric layer on said sidewall;
filling said trench with a sacrificial filler material;
removing a first portion of said sacrificial filler material, thereby exposing an upper portion of said dielectric layer; and
at least partially removing said exposed upper portion of said dielectric layer.
14. The method recited in claim 13 , further comprising:
removing a second portion of said sacrificial filler material, thereby exposing a lower portion of said dielectric layer and leaving a remaining portion of said sacrificial filler material;
partially removing said exposed lower portion of said dielectric layer, leaving a remaining portion of said dielectric layer on said sidewalls; and
removing said remaining portion of said sacrificial filler material.
15. The method recited in claim 12 , further comprising deepening said trench after forming said mask layer.
16. The method recited in claim 11 , further comprising removing said mask layer after at least partially forming said second portion.
17. The method recited in claim 10 , further comprising removing a portion of said field plate dielectric after forming said portions with different thicknesses, thereby increasing a linearity of a change of thickness of said field plate dielectric with increasing depth of said trench.
18. The method recited in claim 9 , further comprising forming a gate oxide on said sidewall after forming said portions of said field plate dielectric.
19. The method recited in claim 13 , further comprising forming an insulating layer on an exposed surface of a remaining portion of said filler material; and
filling said trench with a field plate material.
20. The method recited in claim 19 , further comprising forming a conductive path between said remaining portion and said field plate material.
21. The method recited in claim 9 , further comprising forming a first mask layer over sidewalls of said trench
22. The method of claim 21 , further comprising a first deepening of said trench after forming said first mask layer.
23. The method of claim 22 , further comprising forming a second mask layer over sidewalls of trench exposed by first deepening.
24. The method of claim 23 , further comprising a second deepening of said trench after forming said second mask layer.
25. The method of claim 24 , further comprising:
forming a first oxide layer over a surface of said semiconductor layer exposed by said second deepening;
removing said second mask layer;
forming a second oxide liner over a surface of said semiconductor layer exposed by said first deepening; and
removing said first mask layer
26. A vertical MOSFET comprising:
an epitaxial layer located over a substrate, including:
a body region adjacent an upper surface of said epitaxial layer and doped to have a first conductivity type;
a drain region located between said body region and said substrate and being doped to have a second conductivity type;
a buried region located between said drain region and said substrate and being doped to have said second conductivity type; and
a source region located within said body region and being doped to have said second conductivity type;
two trenches formed in said epitaxial layer;
polysilicon field plates, one field plate located within each of said trenches;
a drift region located within said drain region and between said field plates;
oxide liners located between each of said field plates and said drift region, a lower portion of each of said oxide liners having a thickness greater than a thickness of an upper portion of said oxide liners.
27. The vertical MOSFET recited in claim 26 , wherein said thickness of said lower portion is at least about 20% greater than said thickness of said upper portion.
28. The vertical MOSFET recited in claim 26 , wherein said thickness of said lower portion is substantially uniform over a vertical extent of said lower portion, and said thickness of said upper portion is substantially uniform over a vertical extent of said upper portion.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/426,717 US20100264486A1 (en) | 2009-04-20 | 2009-04-20 | Field plate trench mosfet transistor with graded dielectric liner thickness |
US13/188,162 US8853029B2 (en) | 2009-04-20 | 2011-07-21 | Method of making vertical transistor with graded field plate dielectric |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/426,717 US20100264486A1 (en) | 2009-04-20 | 2009-04-20 | Field plate trench mosfet transistor with graded dielectric liner thickness |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/188,162 Division US8853029B2 (en) | 2009-04-20 | 2011-07-21 | Method of making vertical transistor with graded field plate dielectric |
Publications (1)
Publication Number | Publication Date |
---|---|
US20100264486A1 true US20100264486A1 (en) | 2010-10-21 |
Family
ID=42980358
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/426,717 Abandoned US20100264486A1 (en) | 2009-04-20 | 2009-04-20 | Field plate trench mosfet transistor with graded dielectric liner thickness |
US13/188,162 Active 2030-06-21 US8853029B2 (en) | 2009-04-20 | 2011-07-21 | Method of making vertical transistor with graded field plate dielectric |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/188,162 Active 2030-06-21 US8853029B2 (en) | 2009-04-20 | 2011-07-21 | Method of making vertical transistor with graded field plate dielectric |
Country Status (1)
Country | Link |
---|---|
US (2) | US20100264486A1 (en) |
Cited By (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110104880A1 (en) * | 2009-10-30 | 2011-05-05 | Jens Heinrich | Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition |
US20110115015A1 (en) * | 2009-11-17 | 2011-05-19 | Chiao-Shun Chuang | Trench devices having improved breakdown voltages and method for manufacturing same |
US20110165747A1 (en) * | 2010-01-07 | 2011-07-07 | Hynix Semiconductor Inc. | Semiconductor apparatus and fabrication method thereof |
US20110233660A1 (en) * | 2010-03-24 | 2011-09-29 | Panasonic Corporation | Semiconductor device and manufacture thereof |
US8288230B2 (en) * | 2010-09-30 | 2012-10-16 | Infineon Technologies Austria Ag | Method for producing a gate electrode structure |
US20120319199A1 (en) * | 2011-06-20 | 2012-12-20 | Maxpower Semiconductor, Inc. | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process |
US20120326227A1 (en) * | 2011-06-27 | 2012-12-27 | Burke Peter A | Method of making an insulated gate semiconductor device and structure |
US20140054682A1 (en) * | 2012-08-21 | 2014-02-27 | Balaji Padmanabhan | Bidirectional field effect transistor and method |
US8765609B2 (en) * | 2012-07-25 | 2014-07-01 | Power Integrations, Inc. | Deposit/etch for tapered oxide |
WO2014106127A1 (en) * | 2012-12-31 | 2014-07-03 | Vishay-Siliconix | Adaptive charge balanced mosfet techniques |
CN104037229A (en) * | 2013-03-05 | 2014-09-10 | 美格纳半导体有限公司 | Semiconductor Device And Method For Fabricating The Same |
US20140252461A1 (en) * | 2013-03-05 | 2014-09-11 | Magnachip Semiconductor, Ltd. | Semiconductor device and method for fabricating the same |
US20140339651A1 (en) * | 2013-05-16 | 2014-11-20 | International Rectifier Corporation | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric |
CN104488084A (en) * | 2012-07-25 | 2015-04-01 | 电力集成公司 | Method of forming a tapered oxide |
US20150325685A1 (en) * | 2014-05-07 | 2015-11-12 | International Rectifier Corporation | Power Semiconductor Device with Low RDSON and High Breakdown Voltage |
CN105931969A (en) * | 2016-05-31 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing terminal structure |
US20160293754A1 (en) * | 2012-12-13 | 2016-10-06 | Infineon Technologies Americas Corp. | Method of Manufacturing a Trench FET Having a Merged Gate Dielectric |
US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
US9673314B2 (en) * | 2015-07-08 | 2017-06-06 | Vishay-Siliconix | Semiconductor device with non-uniform trench oxide layer |
US9786753B2 (en) * | 2015-07-13 | 2017-10-10 | Diodes Incorporated | Self-aligned dual trench device |
CN109216172A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the division grid structure of semiconductor devices |
CN109216438A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the stacking polysilicon grating structure of semiconductor devices |
CN109216439A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Manufacturing method with the semiconductor devices of the field plate structure of progressive thickness in groove |
US20190081173A1 (en) * | 2017-09-14 | 2019-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
US10325988B2 (en) * | 2013-12-13 | 2019-06-18 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped field plates |
US10395970B2 (en) | 2013-12-05 | 2019-08-27 | Vishay-Siliconix | Dual trench structure |
US20190296115A1 (en) * | 2018-03-21 | 2019-09-26 | Texas Instruments Incorporated | Semiconductor device having polysilicon field plate for power mosfets |
CN112382658A (en) * | 2020-08-28 | 2021-02-19 | 电子科技大学 | Low gate charge device with stepped discrete shield trenches and method of making the same |
US11069782B2 (en) * | 2015-07-29 | 2021-07-20 | Infineon Technologies Ag | Semiconductor device comprising a gradually increasing field dielectric layer and method of manufacturing a semiconductor device |
US11121224B2 (en) | 2019-02-08 | 2021-09-14 | Texas Instruments Incorporated | Transistor with field plate over tapered trench isolation |
US11322594B2 (en) * | 2020-08-13 | 2022-05-03 | Texas Instruments Incorporated | Semiconductor device including a lateral insulator |
EP4064364A1 (en) * | 2021-03-23 | 2022-09-28 | Infineon Technologies Austria AG | Semiconductor device including a trench strucure |
US20230101610A1 (en) * | 2021-09-30 | 2023-03-30 | Texas Instruments Incorporated | Field-effect transistor having fractionally enhanced body structure |
CN116864381A (en) * | 2023-07-17 | 2023-10-10 | 上海功成半导体科技有限公司 | Preparation method of shielded gate power device and shielded gate power device |
EP4235753A3 (en) * | 2021-02-17 | 2023-11-08 | Infineon Technologies Austria AG | Semiconductor power device and method of manufacturing the same |
US11824111B2 (en) | 2020-10-08 | 2023-11-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
US11862691B2 (en) | 2019-11-01 | 2024-01-02 | Raytheon Company | Field effect transistor having field plate |
US20240047387A1 (en) * | 2021-05-12 | 2024-02-08 | Texas Instruments Incorporated | Semiconductor doped region with biased isolated members |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8193081B2 (en) * | 2009-10-20 | 2012-06-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for metal gate formation with wider metal gate fill margin |
KR101996244B1 (en) * | 2013-06-27 | 2019-07-05 | 삼성전자 주식회사 | Method for fabricating semiconductor device |
US9818828B2 (en) | 2016-03-09 | 2017-11-14 | Polar Semiconductor, Llc | Termination trench structures for high-voltage split-gate MOS devices |
JP6416142B2 (en) * | 2016-03-11 | 2018-10-31 | 株式会社東芝 | Semiconductor device |
US10804263B2 (en) | 2016-09-23 | 2020-10-13 | Texas Instruments Incorporated | Switching field plate power MOSFET |
CN107068758A (en) * | 2017-01-19 | 2017-08-18 | 电子科技大学 | VDMOS device with internal field plate structure |
CN109326595B (en) * | 2017-07-31 | 2021-03-09 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
CN107706101A (en) * | 2017-09-29 | 2018-02-16 | 上海华虹宏力半导体制造有限公司 | The manufacture method of trench gate |
KR102119483B1 (en) * | 2018-12-06 | 2020-06-05 | 현대오트론 주식회사 | Power semiconductor device and method of fabricating the same |
Citations (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605841B2 (en) * | 2000-12-20 | 2003-08-12 | Infineon Technologies Ag | Method for producing an electrode by means of a field effect controllable semiconductor component and field-effect-controllable semiconductor component |
US20030173618A1 (en) * | 2002-02-21 | 2003-09-18 | Markus Zundel | MOS transistor device |
US20030209757A1 (en) * | 2002-03-28 | 2003-11-13 | Ralf Henninger | Semiconductor component with an increased breakdown voltage in the edge area |
US20060118864A1 (en) * | 2004-10-29 | 2006-06-08 | Infineon Technologies Ag | Power trench transistor |
US20060278922A1 (en) * | 2005-03-31 | 2006-12-14 | Markus Zundel | Trench transistor with increased avalanche strength |
US20070114600A1 (en) * | 2005-08-31 | 2007-05-24 | Franz Hirler | Trench transistor and method for fabricating a trench transistor |
US7372103B2 (en) * | 2005-03-31 | 2008-05-13 | Infineon Technologies Austria Ag | MOS field plate trench transistor device |
US20080135930A1 (en) * | 2006-11-14 | 2008-06-12 | Kabushiki Kaisha Toshiba | Power semiconductor device |
US20080197442A1 (en) * | 2007-02-20 | 2008-08-21 | Infineon Technologies Austria Ag | Semiconductor component with cell structure and method for producing the same |
US20080230833A1 (en) * | 2007-03-23 | 2008-09-25 | Infineon Technologies Austria Ag | Semiconductor component and method for producing a semiconductor component |
US20090039419A1 (en) * | 2007-08-10 | 2009-02-12 | Infineon Technologies Ag | Semiconductor component with dynamic behavior |
US20090114986A1 (en) * | 2005-08-31 | 2009-05-07 | Infineon Technologies Austria Ag | Field plate trench transistor and method for producing it |
US20090206395A1 (en) * | 2008-02-20 | 2009-08-20 | Force-Mos Technology Corporation | Trench mosfet with double epitaxial structure |
US20090218618A1 (en) * | 2008-03-03 | 2009-09-03 | Infineon Technologies Austria Ag | Semiconductor device and method for forming same |
US20100087039A1 (en) * | 2007-10-31 | 2010-04-08 | Force-Mos Technology Corp. | Methods for manufacturing trench MOSFET with implanted drift region |
US20100117144A1 (en) * | 2008-11-10 | 2010-05-13 | Infineon Technologies Austria Ag | Semiconductor device and method for the production of a semiconductor device |
US20100140697A1 (en) * | 2008-12-08 | 2010-06-10 | Yedinak Joseph A | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics |
US7750397B2 (en) * | 2007-04-19 | 2010-07-06 | Infineon Technologies Austria Ag | Semiconductor component including compensation zones and discharge structures for the compensation zones |
US20100207206A1 (en) * | 2004-05-19 | 2010-08-19 | Infineon Technologies Ag | Transistor |
-
2009
- 2009-04-20 US US12/426,717 patent/US20100264486A1/en not_active Abandoned
-
2011
- 2011-07-21 US US13/188,162 patent/US8853029B2/en active Active
Patent Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6605841B2 (en) * | 2000-12-20 | 2003-08-12 | Infineon Technologies Ag | Method for producing an electrode by means of a field effect controllable semiconductor component and field-effect-controllable semiconductor component |
US20030173618A1 (en) * | 2002-02-21 | 2003-09-18 | Markus Zundel | MOS transistor device |
US20030209757A1 (en) * | 2002-03-28 | 2003-11-13 | Ralf Henninger | Semiconductor component with an increased breakdown voltage in the edge area |
US6806533B2 (en) * | 2002-03-28 | 2004-10-19 | Infineon Technologies Ag | Semiconductor component with an increased breakdown voltage in the edge area |
US20100207206A1 (en) * | 2004-05-19 | 2010-08-19 | Infineon Technologies Ag | Transistor |
US20060118864A1 (en) * | 2004-10-29 | 2006-06-08 | Infineon Technologies Ag | Power trench transistor |
US20060278922A1 (en) * | 2005-03-31 | 2006-12-14 | Markus Zundel | Trench transistor with increased avalanche strength |
US7372103B2 (en) * | 2005-03-31 | 2008-05-13 | Infineon Technologies Austria Ag | MOS field plate trench transistor device |
US20070114600A1 (en) * | 2005-08-31 | 2007-05-24 | Franz Hirler | Trench transistor and method for fabricating a trench transistor |
US20090114986A1 (en) * | 2005-08-31 | 2009-05-07 | Infineon Technologies Austria Ag | Field plate trench transistor and method for producing it |
US20080135930A1 (en) * | 2006-11-14 | 2008-06-12 | Kabushiki Kaisha Toshiba | Power semiconductor device |
US7642597B2 (en) * | 2006-11-14 | 2010-01-05 | Kabushiki Kaisha Toshiba | Power semiconductor device |
US20080197442A1 (en) * | 2007-02-20 | 2008-08-21 | Infineon Technologies Austria Ag | Semiconductor component with cell structure and method for producing the same |
US20080230833A1 (en) * | 2007-03-23 | 2008-09-25 | Infineon Technologies Austria Ag | Semiconductor component and method for producing a semiconductor component |
US7615847B2 (en) * | 2007-03-23 | 2009-11-10 | Infineon Technologies Austria Ag | Method for producing a semiconductor component |
US7750397B2 (en) * | 2007-04-19 | 2010-07-06 | Infineon Technologies Austria Ag | Semiconductor component including compensation zones and discharge structures for the compensation zones |
US20090039419A1 (en) * | 2007-08-10 | 2009-02-12 | Infineon Technologies Ag | Semiconductor component with dynamic behavior |
US20100087039A1 (en) * | 2007-10-31 | 2010-04-08 | Force-Mos Technology Corp. | Methods for manufacturing trench MOSFET with implanted drift region |
US20090206395A1 (en) * | 2008-02-20 | 2009-08-20 | Force-Mos Technology Corporation | Trench mosfet with double epitaxial structure |
US20090218618A1 (en) * | 2008-03-03 | 2009-09-03 | Infineon Technologies Austria Ag | Semiconductor device and method for forming same |
US20100117144A1 (en) * | 2008-11-10 | 2010-05-13 | Infineon Technologies Austria Ag | Semiconductor device and method for the production of a semiconductor device |
US20100140697A1 (en) * | 2008-12-08 | 2010-06-10 | Yedinak Joseph A | Trench-Based Power Semiconductor Devices with Increased Breakdown Voltage Characteristics |
Cited By (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110104880A1 (en) * | 2009-10-30 | 2011-05-05 | Jens Heinrich | Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition |
US7951677B2 (en) * | 2009-10-30 | 2011-05-31 | Globalfoundries Inc. | Corner rounding in a replacement gate approach based on a sacrificial fill material applied prior to work function metal deposition |
US20110115015A1 (en) * | 2009-11-17 | 2011-05-19 | Chiao-Shun Chuang | Trench devices having improved breakdown voltages and method for manufacturing same |
US8314471B2 (en) * | 2009-11-17 | 2012-11-20 | Diodes Incorporated | Trench devices having improved breakdown voltages and method for manufacturing same |
US20110165747A1 (en) * | 2010-01-07 | 2011-07-07 | Hynix Semiconductor Inc. | Semiconductor apparatus and fabrication method thereof |
US20110233660A1 (en) * | 2010-03-24 | 2011-09-29 | Panasonic Corporation | Semiconductor device and manufacture thereof |
US8288230B2 (en) * | 2010-09-30 | 2012-10-16 | Infineon Technologies Austria Ag | Method for producing a gate electrode structure |
US8680607B2 (en) * | 2011-06-20 | 2014-03-25 | Maxpower Semiconductor, Inc. | Trench gated power device with multiple trench width and its fabrication process |
US20120319199A1 (en) * | 2011-06-20 | 2012-12-20 | Maxpower Semiconductor, Inc. | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process |
US9245963B2 (en) | 2011-06-27 | 2016-01-26 | Semiconductor Components Industries, Llc | Insulated gate semiconductor device structure |
US20120326227A1 (en) * | 2011-06-27 | 2012-12-27 | Burke Peter A | Method of making an insulated gate semiconductor device and structure |
US8889532B2 (en) * | 2011-06-27 | 2014-11-18 | Semiconductor Components Industries, Llc | Method of making an insulated gate semiconductor device and structure |
CN104488084A (en) * | 2012-07-25 | 2015-04-01 | 电力集成公司 | Method of forming a tapered oxide |
US8765609B2 (en) * | 2012-07-25 | 2014-07-01 | Power Integrations, Inc. | Deposit/etch for tapered oxide |
US9472630B2 (en) | 2012-07-25 | 2016-10-18 | Power Integrations, Inc. | Deposit/etch for tapered oxide |
US20140054682A1 (en) * | 2012-08-21 | 2014-02-27 | Balaji Padmanabhan | Bidirectional field effect transistor and method |
US9048214B2 (en) * | 2012-08-21 | 2015-06-02 | Semiconductor Components Industries, Llc | Bidirectional field effect transistor and method |
US9853142B2 (en) * | 2012-12-13 | 2017-12-26 | Infineon Technologies Americas Corp. | Method of manufacturing a trench FET having a merged gate dielectric |
US20160293754A1 (en) * | 2012-12-13 | 2016-10-06 | Infineon Technologies Americas Corp. | Method of Manufacturing a Trench FET Having a Merged Gate Dielectric |
US9853140B2 (en) | 2012-12-31 | 2017-12-26 | Vishay-Siliconix | Adaptive charge balanced MOSFET techniques |
WO2014106127A1 (en) * | 2012-12-31 | 2014-07-03 | Vishay-Siliconix | Adaptive charge balanced mosfet techniques |
US20140252462A1 (en) * | 2013-03-05 | 2014-09-11 | Magnachip Semiconductor, Ltd. | Semiconductor device and method for fabricating the same |
US9099554B2 (en) * | 2013-03-05 | 2015-08-04 | Magnachip Semiconductor, Ltd. | Semiconductor device with low on resistance and method for fabricating the same |
US9379187B2 (en) | 2013-03-05 | 2016-06-28 | Magnachip Semiconductor, Ltd. | Vertically-conducting trench MOSFET |
US9012985B2 (en) * | 2013-03-05 | 2015-04-21 | Magnachip Semiconductor, Ltd. | Semiconductor device having a trench whose upper width is wider than a lower width thereof, and a method for fabricating the same |
US20140252461A1 (en) * | 2013-03-05 | 2014-09-11 | Magnachip Semiconductor, Ltd. | Semiconductor device and method for fabricating the same |
CN104037229A (en) * | 2013-03-05 | 2014-09-10 | 美格纳半导体有限公司 | Semiconductor Device And Method For Fabricating The Same |
US10483359B2 (en) | 2013-05-16 | 2019-11-19 | Infineon Technologies Americas Corp. | Method of fabricating a power semiconductor device |
US9299793B2 (en) | 2013-05-16 | 2016-03-29 | Infineon Technologies Americas Corp. | Semiconductor device with a field plate trench having a thick bottom dielectric |
US20140339651A1 (en) * | 2013-05-16 | 2014-11-20 | International Rectifier Corporation | Semiconductor Device with a Field Plate Double Trench Having a Thick Bottom Dielectric |
US9735241B2 (en) * | 2013-05-16 | 2017-08-15 | Infineon Technologies Americas Corp. | Semiconductor device with a field plate double trench having a thick bottom dielectric |
US10395970B2 (en) | 2013-12-05 | 2019-08-27 | Vishay-Siliconix | Dual trench structure |
US10325988B2 (en) * | 2013-12-13 | 2019-06-18 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped field plates |
US20150325685A1 (en) * | 2014-05-07 | 2015-11-12 | International Rectifier Corporation | Power Semiconductor Device with Low RDSON and High Breakdown Voltage |
US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
CN107851665B (en) * | 2015-07-08 | 2022-06-28 | 维西埃-硅化物公司 | Semiconductor device having non-uniform trench oxide layer |
US9978859B2 (en) | 2015-07-08 | 2018-05-22 | Vishay-Siliconix | Semiconductor device with non-uniform trench oxide layer |
KR102631737B1 (en) | 2015-07-08 | 2024-02-01 | 비쉐이-실리코닉스 | Semiconductor device with non-uniform trench oxide layer |
KR20180042847A (en) * | 2015-07-08 | 2018-04-26 | 비쉐이-실리코닉스 | Semiconductor device having heterogeneous trench oxide layer |
CN107851665A (en) * | 2015-07-08 | 2018-03-27 | 维西埃-硅化物公司 | Semiconductor devices with uneven trench oxide layer |
US9673314B2 (en) * | 2015-07-08 | 2017-06-06 | Vishay-Siliconix | Semiconductor device with non-uniform trench oxide layer |
US9786753B2 (en) * | 2015-07-13 | 2017-10-10 | Diodes Incorporated | Self-aligned dual trench device |
US11069782B2 (en) * | 2015-07-29 | 2021-07-20 | Infineon Technologies Ag | Semiconductor device comprising a gradually increasing field dielectric layer and method of manufacturing a semiconductor device |
CN105931969A (en) * | 2016-05-31 | 2016-09-07 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing terminal structure |
CN109216172B (en) * | 2017-07-03 | 2021-01-05 | 无锡华润上华科技有限公司 | Manufacturing method of split gate structure of semiconductor device |
CN109216172A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the division grid structure of semiconductor devices |
CN109216438A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the stacking polysilicon grating structure of semiconductor devices |
CN109216439A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | Manufacturing method with the semiconductor devices of the field plate structure of progressive thickness in groove |
CN109509785A (en) * | 2017-09-14 | 2019-03-22 | 株式会社东芝 | Semiconductor device |
US20190081173A1 (en) * | 2017-09-14 | 2019-03-14 | Kabushiki Kaisha Toshiba | Semiconductor device |
US10720499B2 (en) * | 2018-03-21 | 2020-07-21 | Texas Instruments Incorporated | Semiconductor device having polysilicon field plate for power MOSFETs |
US20190296115A1 (en) * | 2018-03-21 | 2019-09-26 | Texas Instruments Incorporated | Semiconductor device having polysilicon field plate for power mosfets |
US11121224B2 (en) | 2019-02-08 | 2021-09-14 | Texas Instruments Incorporated | Transistor with field plate over tapered trench isolation |
US11862691B2 (en) | 2019-11-01 | 2024-01-02 | Raytheon Company | Field effect transistor having field plate |
US11322594B2 (en) * | 2020-08-13 | 2022-05-03 | Texas Instruments Incorporated | Semiconductor device including a lateral insulator |
CN112382658A (en) * | 2020-08-28 | 2021-02-19 | 电子科技大学 | Low gate charge device with stepped discrete shield trenches and method of making the same |
US11824111B2 (en) | 2020-10-08 | 2023-11-21 | Kabushiki Kaisha Toshiba | Semiconductor device |
EP4235753A3 (en) * | 2021-02-17 | 2023-11-08 | Infineon Technologies Austria AG | Semiconductor power device and method of manufacturing the same |
EP4064364A1 (en) * | 2021-03-23 | 2022-09-28 | Infineon Technologies Austria AG | Semiconductor device including a trench strucure |
US20240047387A1 (en) * | 2021-05-12 | 2024-02-08 | Texas Instruments Incorporated | Semiconductor doped region with biased isolated members |
US20230101610A1 (en) * | 2021-09-30 | 2023-03-30 | Texas Instruments Incorporated | Field-effect transistor having fractionally enhanced body structure |
CN116864381A (en) * | 2023-07-17 | 2023-10-10 | 上海功成半导体科技有限公司 | Preparation method of shielded gate power device and shielded gate power device |
Also Published As
Publication number | Publication date |
---|---|
US8853029B2 (en) | 2014-10-07 |
US20110275210A1 (en) | 2011-11-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8853029B2 (en) | Method of making vertical transistor with graded field plate dielectric | |
US10741698B2 (en) | Semi-floating gate FET | |
US9799762B2 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
US9431530B2 (en) | Super-high density trench MOSFET | |
US9673289B2 (en) | Dual oxide trench gate power MOSFET using oxide filled trench | |
US10355087B2 (en) | Semiconductor device including a transistor with a gate dielectric having a variable thickness | |
CN103915499B (en) | The method of semiconductor devices and manufacture semiconductor devices | |
US20170033212A1 (en) | Semiconductor Device and Transistor Cell Having a Diode Region | |
US20130153995A1 (en) | Semiconductor device and method for manufacturing the same | |
US8860136B2 (en) | Semiconductor device and method of manufacturing a semiconductor device | |
US20150108568A1 (en) | Semiconductor structure with high energy dopant implantation | |
TWI471942B (en) | Trench-gate mosfet with capacitively depleted drift region | |
US8159024B2 (en) | High voltage (>100V) lateral trench power MOSFET with low specific-on-resistance | |
JP2008091924A (en) | Gate etching method of high voltage fet | |
TW201318170A (en) | Replacement source/drain finFET fabrication | |
US9449968B2 (en) | Method for manufacturing a semiconductor device and a semiconductor device | |
KR20120106578A (en) | Mosfet device with thick trench bottom oxide | |
US10026835B2 (en) | Field boosted metal-oxide-semiconductor field effect transistor | |
CN105470140B (en) | The method and semiconductor devices of manufacturing semiconductor devices | |
US6977203B2 (en) | Method of forming narrow trenches in semiconductor substrates | |
CN115241283A (en) | Integrated planar-trench gate power MOSFET | |
CN115050823A (en) | Semiconductor device including trench structures separated from each other | |
US20150325685A1 (en) | Power Semiconductor Device with Low RDSON and High Breakdown Voltage | |
CN104979197B (en) | Fin formula field effect transistor and forming method thereof | |
CN111029257A (en) | Transistor device and method for forming recess for trench gate electrode |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DENISON, MARIE;PENDHARKAR, SAMEER;HOWER, PHILIP L.;AND OTHERS;SIGNING DATES FROM 20090329 TO 20090413;REEL/FRAME:022570/0515 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |