CN111029257A - Transistor device and method for forming recess for trench gate electrode - Google Patents

Transistor device and method for forming recess for trench gate electrode Download PDF

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Publication number
CN111029257A
CN111029257A CN201910953696.2A CN201910953696A CN111029257A CN 111029257 A CN111029257 A CN 111029257A CN 201910953696 A CN201910953696 A CN 201910953696A CN 111029257 A CN111029257 A CN 111029257A
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China
Prior art keywords
trench
insulating layer
depth
gate electrode
recess
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Inventor
T.法伊尔
J.班达里
C.格鲁贝尔
H.霍费尔
R.K.约希
O.屈恩
J.斯坦布伦纳
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

Transistor devices and methods for forming recesses for trench gate electrodes are disclosed. In an embodiment, a method includes forming a recess for a trench gate electrode, the method including: forming a trench in the first major surface of the semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first major surface; forming a first insulating layer on the bottom and sidewalls of the trench; inserting a first conductive material into the trench, the first conductive material at least partially covering the first insulating layer to form a field plate in a lower portion of the trench; applying a second insulating layer to the first major surface and the trench such that the second insulating layer fills the trench and covers the conductive material; removing the second insulating layer from the first main surface and partially removing the second insulating layer from the trench by wet chemical etching; and forming a recess for the gate electrode in the second insulating layer in the trench.

Description

Transistor device and method for forming recess for trench gate electrode
Background
Many functions of modern devices in automotive, consumer and industrial applications, such as controlling electric motors or motors, are based on semiconductor transistor devices, such as field effect transistors, such as MOSFETs (metal oxide semiconductor field effect transistors) and IGBTs (insulated gate bipolar transistors).
The capacitance between the gate electrode and the supply electrodes, which are the source and drain electrodes for MOSFETs and the emitter and collector electrodes for IGBTs, and the blocking voltage of the transistor are operating parameters that can be optimized to improve the performance of the transistor device. Buried field plates can be used to increase the on-resistance R for a particular applicationonThe blocking voltage of (2). A field plate and a gate electrode may be disposed in the trench, with the field plate disposed toward a lower side of the trench and the gate electrode disposed toward an upper side of the trench. The gate electrode is electrically isolated from the field plate and the semiconductor body, and the field plate is electrically isolated from the semiconductor body, typically by an insulating material such as oxide. Although a buried field plate may be usedFor reducing the gate drain capacitance (Qgd), but a capacitance is generated between the gate electrode and the field plate, which forms part of the gate-source capacitance (Qgs), since the field plate is typically coupled to the source potential.
The gate-source capacitance can be affected by adjusting the dielectric constant and thickness of the spacer layer between the gate electrode and the field plate. However, to further improve the performance of transistor devices, further improvements are desirable.
Disclosure of Invention
In an embodiment, a transistor device includes a semiconductor substrate having a first major surface and a plurality of transistor cells. Each transistor cell includes: a trench extending into the semiconductor substrate from the first main surface and having a bottom and sidewalls extending from the bottom to the first main surface; a field plate in the trench; a gate electrode in the trench, disposed over and electrically insulated from the field plate; and a mesa including a drift region, a body region on the drift region, and a source region on the body region. The lower surface of the gate electrode is arranged at a depth d from the first main surfacegTo (3). The body region has a depth d from the first main surfacepnForming a pn-junction with the semiconductor material of the semiconductor substrate. Depth dpnAnd depth dgThe variation in the difference between is less than dg8% of the total.
In an embodiment, a method of forming a recess for a trench gate electrode includes: forming a trench in the first major surface of the semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first major surface; forming a first insulating layer on the bottom and sidewalls of the trench; inserting a first conductive material into the trench, the first conductive material at least partially covering the first insulating layer to form a field plate in a lower portion of the trench; applying a second insulating layer to the first major surface and the trench such that the second insulating layer fills the trench and covers the conductive material of the field plate; removing the second insulating layer from the first main surface and partially removing the second insulating layer from the trench by wet chemical etching; and forming a recess for the gate electrode in the second insulating layer in the trench.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
Drawings
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the drawings and are detailed in the following description.
Fig. 1A to 1G illustrate a method for forming a recess for a trench electrode.
Fig. 2 illustrates a flow chart of a method for forming a recess for a trench gate electrode.
Fig. 3 illustrates a transistor device including a trench gate electrode.
Detailed Description
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "above," "below," "front," "rear," "leading," "trailing," etc., is used with reference to the orientation of the figure(s) being described. Because components of various embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description of the invention is not to be taken in a limiting sense, and the scope of the invention is defined by the appended claims.
A number of exemplary embodiments will be explained below. In this case, identical structural features are identified in the figures by identical or similar reference symbols. In the context of the present description, "lateral" or "lateral direction" should be understood to mean a direction or range running generally parallel to the lateral extent of the semiconductor material or semiconductor carrier. The transverse direction thus extends generally parallel to these surfaces or sides. In contrast, the terms "vertical" or "vertical direction" are understood to mean a direction running generally perpendicular to these surfaces or sides and therefore to the transverse direction. The vertical direction thus runs in the thickness direction of the semiconductor material or semiconductor carrier.
As used in this specification, when an element such as a layer, region or substrate is referred to as being "on" or "extending" onto another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present.
As used in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.
In power MOSFET devices, the gate-drain capacitance (Qgd) has a strong influence on the switching behavior of the device. The ratio between Qgd and Qgs (gate-source capacitance) determines the sensitivity to inductive turn-on (during turn-off, the rapidly rising drain voltage opens the device via capacitive coupling). The value of the gate-drain capacitance adds to the switching losses and it affects the drift behavior of the channel resistance when the device is subjected to stress conditions. To control these problems, precise control of the process is required in order to achieve precise target values of gate-drain capacitance and to achieve small variations across each wafer, which can be challenging for vertical gate structures.
The geometric equivalent for the Qgd value is the overlap of the lower end of the gate electrode over the end of the body of the transistor. For a transistor structure having a trench including a gate electrode positioned on a field plate, also referred to as a dual polysilicon MOSFET, this geometry typically depends at least on the growth of the IPD (interpoly dielectric) and the underlying polysilicon electrode, i.e. the recess of the field plate, because both the field plate and the gate electrode are commonly formed of polysilicon. Using conventional processing for gate recess etch and subsequent deposition/growth, production limitations are expected to vary on the order of > - +/-40 nm.
The embodiments described herein are based on the recognition that: for vertical gate structures, the Qgd value may depend on the history of the trench processing prior to gate oxide growth, since the vertical position of the gate electrode in the trench is defined by the initial recess into the trench, while the body implant is defined with respect to the mesa surface; and on the following recognition: this difference can lead to alignment variations between the gate electrode and the MOSFET channel across the wafer and from batch to batch.
As described herein, a process is provided in which the gate electrode positioning in such vertical dual polysilicon MOSFETs is independent of the trench processing history. Thus, better control over the target Qgd value is provided. The gate overlap on the ends of the body of the transistor is defined using the following method. In a first step, after forming a lower polysilicon electrode (i.e., field plate) in a lower portion of the trench and removing oxide on the sidewalls of an upper portion of the trench above the field plate, the entire trench is refilled with oxide. In a second step, the oxide overfill is planarized using a chemical-mechanical polishing (CMP) process, and the CMP is designed to stop with very high selectivity on top of the transistor mesa. In some embodiments, the silicon removal from the mesa is only on the order of a few (2 to 3) nm. The method defines a new surface from which to define both the gate electrode and all implants. The upper portion of the transistor thus becomes independent of all processing involved in forming the lower polysilicon electrode. Since the entirety of the upper portion of the trench is filled with oxide, the lower end portion of the gate electrode may be defined only by a wet chemical etching process for forming a recess for the gate electrode in the upper portion of the trench. In this way the geometrical variation between the overlap of the gate electrode and the body region can be reduced to about +/-15 nm. This in turn results in a reduction in the variation by a factor of about 2.5 to 3 compared to the current standard method.
Fig. 1A to 1G illustrate a method for forming a recess for a trench gate electrode and for forming a trench gate electrode in the recess. The trench gate electrode may be used in a transistor device such as a MOSFET device.
Fig. 1A illustrates a semiconductor substrate 10, which may be a silicon substrate. The silicon substrate may be a single crystal silicon wafer or may comprise an epitaxially deposited single crystal silicon layer, commonly known as an epitaxial layer, disposed on a support substrate, which may be a single crystal silicon wafer. The semiconductor substrate 10 comprises a first main surface 11.
A trench 12 is formed in the first main surface 11 of the semiconductor substrate 10 and has a bottom 13 and sidewalls 14 extending from the bottom 13 to the first main surface 11. The trenches may extend substantially perpendicular to the first main surface 11. The first main surface 11 may be described as a lateral or horizontal surface and the grooves 12 may be considered as vertical grooves.
The grooves 12 may have an elongated strip shape, wherein the length of the grooves 12 extends into the plane of the drawing. Typically, a MOSFET device includes a plurality of trenches 12, the plurality of trenches 12 extending substantially parallel to one another such that adjacent trenches 12 define a mesa 30. In other embodiments, the grooves 12 may have a columnar shape or a needle shape and may be substantially circular, square, hexagonal in plan view. In these embodiments, the regions between the columnar trenches form mesas.
The sidewalls 14 continuously adjoin the bottom 13 to form the trench 12. In embodiments in which the trench 12 has an elongated strip-like shape, the side wall 14 may have two substantially parallel long portions connected by two substantially parallel short portions extending substantially perpendicular to the long portions to form a rectangular shape in plan view.
The method will be described with respect to a single trench 12. However, the preparation of the recess and trench gate electrodes is typically performed essentially simultaneously for a plurality of trenches. The trench 12 may form part of the active switching region of the transistor device and be positioned in what is commonly referred to as the active region 15 or cell field of the transistor device. Some of the trenches 12' may also be positioned in the edge termination region 16 and form part of the edge termination structure of the transistor device. The trenches 12' in the edge termination region may have one or more dimensions, such as a width, that are different than the dimensions of the trenches 12 in the active region 15.
After forming the trench 12 in the first main surface, a first insulating layer 17 is formed on the bottom 13 and the sidewalls 14 of the trench 12, and the first insulating layer 17 may completely cover the semiconductor material forming the bottom 13 and the sidewalls 14 of the trench 12. The first insulating material 17 has a thickness such that it lines the bottom 13 and sidewalls 14 and defines a gap or unfilled region at the center of the width of the trench 12. A first conductive material 18 is inserted into the trench, and in particular into the gap defined by the first insulating layer 17, to form a field plate 19 in the lower portion of the trench 12.
In some embodiments, such as illustrated in fig. 1A, in the upper portion of the trench 12, the first insulating layer 17 is completely removed from the sidewalls 14 of the trench 12 in the upper portion of the trench 12, thereby exposing the semiconductor material of the substrate 10. The uppermost portion of the field plate 19 may protrude above the upper surface of the remainder of the first insulating layer 17. In some embodiments, there may be a very thin insulating layer with a thickness of a few nanometers on the sidewalls 14 of the upper portion of the trench 12.
The first conductive material 18 may be inserted into the trench 12 by completely filling the trench 12 with the first conductive material 18 and applying the first conductive material 18 over the first main surface 11 of the semiconductor substrate 10. The first conductive material 18 is then removed from the first major surface 11, for example by chemical mechanical polishing, and the first conductive material 18 is removed from the upper portion of the trench 12, for example by etching, to form a field plate 19 in the lower portion of the trench 12. The upper portion of the trench 12 is not filled or is empty and may be laterally defined by the semiconductor material of the semiconductor substrate 10 forming the sidewalls 14 of the trench 12 and at the bottom by the field plate 19 and the first insulating layer 17 laterally arranged between the field plate 19 and the sidewalls 14. The first insulating layer 17 may be formed of silicon oxide (e.g. silicon dioxide) and the first conductive material 18 and the field plate 19 may be formed of polysilicon.
Fig. 1B illustrates the semiconductor substrate 10 after a second insulating layer 20 has been applied to the first major surface 11 of the semiconductor substrate 10 such that the second insulating layer 20 fills the trenches 12 and covers the conductive material 18 and the field plate 19. The second insulating layer 20 covers the portion of the field plate 19 protruding from the first insulating layer 17 and contacts the portion of the upper surface and side faces of the field plate 19 not covered by the first insulating layer 17. The second insulating layer 20 also contacts the first insulating layer 17 and the sidewalls 14 of the upper portion of the trench 12, or contacts the thin oxide layer (if present) remaining on the upper portion of the sidewalls 14 of the trench 12.
The second insulating layer 20 may be conformally deposited such that it has peaks over the mesas 30 and valleys over the trenches 12. The bottom of the valleys is located above the first main surface 11 so that the trenches 12 are completely filled with the second insulating layer 20. The second insulating layer 20 may be deposited using high density plasma deposition (HDP), and the second insulating layer 20 may be formed of silicon dioxide.
Fig. 1C illustrates the semiconductor substrate after the second insulating layer 20 has been removed from the first major surface 11 of the semiconductor substrate 10 such that the semiconductor material of the mesas 30 is exposed and forms the uppermost surface of the semiconductor substrate 10 and such that the second insulating material 20 located in the trenches 12 is substantially coplanar with the upper surface of the mesas 30 to provide a planar first major surface 11.
This planar first major surface 11 may then be used to determine the depth of the gate in the trench 12 and the location of the implanted region within the mesa 30, as described in relation to fig. 1D to 1G.
The second insulating layer 20 is partially removed from the trench 12, and a recess 21 for a gate electrode is formed in the second insulating layer 20 in the trench 12, as illustrated in fig. 1D. The recess 21 has a bottom 24 formed by the second insulating material 20 such that it is spaced from the field plate 19 by a region of the second insulating layer 20. A second insulating layer 20 provides electrical insulation on top of the field plate 19. The side wall 22 of the recess 21 is formed by the semiconductor of the semiconductor substrate 10The material is formed. The recess 21 has a depth drSuch that the bottom 24 of the recess 21 is located at a depth or distance d from the first main surface 11rTo (3).
The second insulating layer 20 is removed from the trench 12 by wet chemical etching to form a recess 21. By removing the second insulating material 20 from the trench 12 and forming the recess 21 using wet chemical etching, the depth d of the recess 21 can be controlled using the first main surface 11rSince the first main surface 11 may act as an etch stop. Since the top portion of the trench 12 is filled with a single insulating material, i.e. the material of the second insulating layer 20, the wet etch enables a more precise control of the depth d of the recess 21r。
In some embodiments, the second insulating layer 20 is removed selectively with respect to the material of the semiconductor substrate 10. For example, the first main surface 11 of the semiconductor substrate 10 may function as an etch stop. The second insulating layer 20 may be selectively removed by Chemical Mechanical Polishing (CMP). The chemical mechanical polishing may include using a slurry having a polishing selectivity of about 100 to 1 of the material of the second insulating layer 20 compared to the material of the semiconductor substrate.
Fig. 1E illustrates the semiconductor substrate 10 after forming a third insulating layer 23 on the exposed sidewalls 22 of the recess 21. The third insulating layer 23 forms a gate oxide and is thinner than the first insulating layer 17. In some embodiments, the third insulating layer 23 is conformally deposited and covers the first main surface 11, the sidewalls 22 and the bottom 24 of the recess 21.
As illustrated in fig. 1F, a second conductive material 25 is inserted into the recess 21 now comprising a third insulating layer 23 as gate oxide at least on the sidewalls 22 to form a gate electrode 26 in the upper portion of the trench 12. The gate electrode 26 is separated from the semiconductor material of the mesa 30 by the third insulating material 23 and from the field plate 19 by the second insulating layer 20. For embodiments in which the gate oxide is deposited on the second insulating layer 20, the gate electrode 26 is separated from the field plate by the gate oxide and the second insulating layer 20.
The first, second, and third insulating layers 17, 20, and 23 may include silicon oxide. The semiconductor substrate 10 may include silicon. The first conductive material 18 forming the field plate 19 and the second conductive material 25 forming the gate electrode 26 may comprise polysilicon.
Depth d of the formed recess 21rMay be matched to the depth d of the gate electrode in the final device structuregAlso, for example, if the third insulating layer 23 forming the gate oxide is deposited only on the silicon forming the sidewalls 22. In some embodiments, the depth d of the recessrCan be reacted with dgThere is an offset. For example, if a third insulating layer 23 forming a gate oxide is deposited onto the bottom 24 of the recess 21, the depth d of the recessrPossibly with dgThere is an offset. If the third insulating layer 23 forming the gate oxide is formed by thermal annealing, the depth d of the recess isrMay be related to d due to consumption of the top portion of the mesa or due to the effects of other processing parameters, e.g., affecting the upper surface of the mesa, such as thermal oxide, e.g., masking oxidegThere is an offset.
As schematically illustrated by the arrows in fig. 1G, a body region 27 of the second conductivity type may be formed by implantation into the first main surface 11 of the semiconductor substrate 10. The body region 27 forms a pn-junction 28 with the underlying semiconductor material of the semiconductor substrate 10, which comprises a first conductivity type opposite to a second conductivity type. For example, the semiconductor substrate may be n-type and the body region 27 may be p-type. The pn-junction 28 is formed at a depth d from the first main surface 11pnTo (3). A source region 29 comprising the first conductivity type is formed on the body region 27.
The lower surface of the gate electrode 26 is located at a depth d from the first main surface 11gTo (3). The pn-junction 28 between the body region 27 and the underlying semiconductor substrate 10 is arranged at a depth d from the first main surface 11pnTo (3). Since both the implantation to form the body region 27 and the wet etching process to form the recess 21 are determined by processes measured from the position of the first main surface 11, the position of the bottom of the recess 21 and hence of the lowermost portion of the gate electrode 26 and the position of the body region 27 and hence of the pn junctionThe relationship between the junctions 28 can be more closely controlled. Therefore, the overlap between the gate electrode 26 and the body region 27 can be more closely controlled, and the gate-drain capacitance Qgd is reduced.
In some embodiments, the depth dpnAnd depth dgThe difference therebetween varies less than dg8% of the total. This difference in depth is a difference in absolute depth. The difference in depth may have a distribution defined in a sigma manner. In some embodiments, the depth dpnAnd depth dgThe difference therebetween varies less than dg8% of (c), has ± 4.5 σ. By way of example, the depth d of the recessrMay be 200. + -.20 nm with a distribution of. + -. 4.5. sigma. If the depth dpnA variation of ± 10nm with a standard deviation of 4.5 σ, the total variation is √ (20)2+102) = √ (500) = ± 22.4nm, having ± 6.4 σ, because √ (4.5)2+4.52) = 6.4 σ, and each process is independent.
Depth dpnAnd depth dgThe variation in the difference between is not only lower for cells within the cell field of a single transistor device, but it is also lower for the edge termination region and from wafer to wafer and from batch to batch.
The lower surface of the gate electrode 26 has a depth d in the final productg. Depth d of the recess directly after its formationrPossibly to a depth d in the final productgIn contrast, because the growth of the gate oxide consumes some of the silicon of the mesa. If a gate oxide is deposited onto the bottom of the recess 21, such as the third insulating layer 23 illustrated in FIG. 1E, then the initial recess depth drThe thickness of the deposited layer is modified. For the deposited gate oxide layer, at the initial recess depth drTaking this thickness into account. Since the thickness of the gate oxide layer is very precisely controlled, it should not adversely affect QgdThe achieved accuracy of.
In some embodiments, the depth d of the recess 21 may be further controlled byr: determining the depth d of the recess 21r1The determined depth dr1Compared with a predetermined depth and if the determined depth dr1Less than the predetermined depth, the second insulating layer 21 is further removed, for example by wet chemical etching, and the depth of the recess 21 is increased. The method may be repeated until the determined depth equals the depth dr. Responsive to the determined depth d of the recess 21r1To adjust the composition of the wet chemical etch and/or one or more etch conditions.
Fig. 2 illustrates a flow chart 40 of a method of forming a recess for a trench gate electrode. In block 41, a trench is formed in a first major surface of a semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first major surface.
In block 42, a first insulating layer is formed on the bottom and sidewalls of the trench. In block 43, a first conductive material is inserted into the trench so that it at least partially covers the first insulating layer to form a field plate in a lower portion of the trench. In block 44, a second insulating layer is applied to the first major surface and the trench such that the second insulating layer fills the trench and covers the conductive material. In block 45, the second insulating layer is removed from the first major surface. In block 46, the second insulating layer is partially removed from the trench by wet chemical etching, and a recess for the gate electrode is formed in the second insulating layer in the trench. The use of wet chemical etching enables the depth of the recess to be controlled compared to the first major surface of the substrate.
In some embodiments, the second insulating layer is selectively removed, and the first main surface of the semiconductor substrate serves as an etch stop. The control of depth may be further aided by the use of: chemical mechanical polishing to remove the second insulating layer from the first major surface; and a paste selective to the material of the second insulating layer, e.g., silicon oxide, compared to the material of the semiconductor substrate, e.g., silicon. The chemical mechanical polishing may be performed using a slurry having a polishing selectivity of the second insulating layer to the semiconductor substrate of about 100 to 1.
The second insulating layer may be deposited onto the first major surface using High Density Plasma (HDP) deposition. HDP deposition may be used to ensure that the upper portion of the trench is completely filled with a single body of material comprising the second insulating layer. Filling the trench with one type of oxide only enables control of the depth of the recess and thus the position of the gate electrode in the device and its spacing from or depth from the first main surface, since different oxides have different etch rates. Filling the upper portion of the trench with a single material further assists in providing a predictable and controllable removal of the second insulating layer from the trench by wet etching and thus a well-defined depth to the recess and a well-defined position of the gate electrode relative to the first main surface of the semiconductor substrate.
In some embodiments, removing the second insulating layer from the trench by wet chemical etching includes exposing the semiconductor material at sidewalls of the trench over the first conductive material. The first conductive material of the field plate remains covered by the second insulating material.
Prior to refilling the trench, the first insulating layer may be removed from the sidewalls (if present on the sidewalls in the upper portion of the trench) by wet chemical etching to expose the semiconductor material of the semiconductor substrate.
In some embodiments, the recess for the gate electrode may be formed using multiple steps. For example, in an embodiment, the method further comprises: determining a depth of the recess; comparing the determined depth to a predetermined depth; and further removing the second insulating layer and increasing the depth of the recess using wet chemical etching. The method may be repeated until the recess has a predetermined depth. The composition of the wet chemical etch and/or the etch conditions may be adjusted in response to the determined depth.
In some embodiments, the composition of the wet chemical etch and/or the etch conditions may be adjusted in response to the determined depth of the recess for use in fabricating subsequent wafers or wafer lots.
In some embodiments, the method further comprises: forming a third insulating layer on the exposed sidewall to form a gate oxide; and inserting a second conductive material into the recess to form a gate electrode in an upper portion of the trench. The third insulating layer may be formed by depositing an insulating material into the trench or by oxidizing the semiconductor material of the exposed sidewalls of the trench.
In some embodiments, the first conductive material may be inserted into the trench by: the trench is filled with a first conductive material and the first conductive material is applied over the first major surface, and then the first conductive material is removed from the first major surface and from an upper portion of the trench to form a field plate in a lower portion of the trench.
The method may further comprise: forming a body region of the second conductivity type by implantation into the first main surface of the semiconductor substrate, the body region being at a depth d from the first main surfacepnForming a pn junction with the semiconductor material of the semiconductor substrate and forming a source region on the body region. The semiconductor material of the semiconductor substrate in contact with the body region forms a drift region of the transistor structure. A drain region may be formed in the semiconductor substrate below the drift region to form a vertical transistor structure, such as a vertical MOSFET structure. The drain region may be provided by a semiconductor support substrate which is highly doped, for example with the first conductivity type, wherein the drift region, the body region and the source region of the mesa and the trench are formed in an epitaxial semiconductor layer which is formed on the support substrate.
The location of the recess and the gate electrode formed in the recess is independent of previous methods and processes for forming the field plate in the bottom of the trench. Therefore, any variation in the position of the field plate is not transferred to the position of the gate electrode. Additionally, since the body region is formed by implantation into the semiconductor substrate from the first main surface, the position of the body region with respect to the first main surface and the depth of the pn-junction between the body region and the underlying portion of the semiconductor substrate forming the drift region are controlled with respect to the same surface, i.e. the first main surface as used for controlling the depth of the gate electrode. Thus, the difference between the depth of the recess and its gate electrode and the depth of the pn-junction of the body region and the drift region can be more precisely defined not only within the cells of a single transistor device but also wafer-wise and batch-wise. Thus, the gate-drain capacitance can be reduced not only for single transistor devices but also for multiple wafers and batches of wafers.
In some embodiments, the improved Qgd control process may be implemented as follows: the starting point is a vertical double polysilicon transistor with a completed lower polysilicon electrode, i.e., a field plate. The insulating layer or field oxide FOX at the sidewalls at the upper portion of the trench above the field plate has been removed in order to optimize the aspect ratio of the top opening for oxide filling of the trench. This removal of field oxide may be omitted depending on the aspect ratio of the trench.
In a next step, the trench is filled with an oxide including an overfill. The height of the overfill can depend on the nature of the slurry used in the subsequent CMP process. Depending on the subsequent planarization paste requirements, the filling may transfer or planarize the topography. If High Density Plasma (HDP) is used to deposit the oxide, a thin protective layer may be grown or deposited prior to oxide fill to protect the exposed silicon from plasma damage.
In the next step, the surface is planarized in a CMP process. The process needs to have a very high selectivity to oxide compared to silicon so as not to significantly affect the trench depth and trench depth variation. The planarization is followed by the necessary cleaning steps that may have resulted in a small initial constant recess of the oxide into the trench.
Finally, the oxide is recessed as required into the trench to create a recess for the gate electrode. Due to the previous planarization, the recess becomes independent of the processing history of the trench. Both the gate electrode and the implant are defined from the same surface, resulting in an optimal alignment between the channel and the gate electrode. This allows the resulting gate overlap over the channel to be minimized and helps to reduce/control Qgd. The wet recess etch may be divided into sections to fine tune the final depth after the first initial etch/measurement. A constant offset may also be added by a possible wet clean before the subsequent gate oxide growth. An offset may also be used for the deposited gate oxide that reduces the initial size of the recess by the width of the deposited and annealed gate oxide layer.
Fig. 3 illustrates a transistor device 50, such as a MOSFET device, that includes a gate structure 51 that is fabricated using the methods described herein. Transistor device 50 includes a semiconductor substrate 52 having a first major surface 53 and a plurality of transistor cells 54. Each transistor cell 54 includes: a trench 55 extending substantially vertically into the semiconductor substrate 52 from the first main surface 53 and having a bottom 56 and sidewalls 57 extending from the bottom 56 to the first main surface 53; a field plate 58 in the trench 55; a gate electrode 59 in trench 55, which is disposed over field plate 58 and electrically insulated from field plate 58. Gate electrode 59 is recessed into a top portion of trench 55 so that its upper surface is below first major surface 53. The transistor cell 54 further comprises a mesa 60 defined by a contiguous trench in the trench 55, the trench 55 comprising a drift region 61, a body region 62 on the drift region 61 and a source region 63 on the body region 62. The lower surface 64 of the gate electrode 59 is arranged at a depth d from the first main surface 53gAnd the body region 62 is at a depth d from the first main surfacepnForming a pn junction 65 with the semiconductor material of the semiconductor substrate 52. Depth dpnAnd depth dgThe variation in the difference between is less than dg8% of the total.
The transistor device 50 further comprises a drain region 66, and a drift region 61 is formed on the drain region 66. The drain region 66 may be formed in a support substrate such as a highly doped silicon single crystal substrate, and the drift region 61, the body region 62 and the source region 63 may be formed in an epitaxial silicon layer grown on the support substrate. The drain region may form a back surface of the transistor device 60. The semiconductor substrate 52, the drift region 61, the source region 63 and the drain region 66 have a first conductivity type, for example n-type, and the body region 62 has a second conductivity type, for example p-type.
The trench 55 includes a first insulating layer 67, the first insulating layer 67 forming a field oxide lining the bottom 56 and a lower portion 68 of the sidewall 57 and laterally positioned between the field plate 58 and the sidewall 57. A second insulating layer 69 is positioned on the field plate 58 and extends between the field plate 58 and the gate electrode 59. The top portion of the field plate 58 is covered by a second insulating layer 69. A third insulating layer 70 providing a gate insulation or gate oxide is arranged on the portion 71 of the sidewall 57 at the top of the trench 55 and extends from the second insulating layer 69 to the first main surface 53 of the semiconductor substrate 52.
Since the overlap at the gate electrode 59 below between the gate electrode 59 and the body region 62 can be more accurately controlled by manufacturing the transistor device 50 using the methods described herein, the gate-drain capacitance can be easily and more accurately controlled and the performance of the transistor device 50 improved.
Spatially relative terms, such as "lower," "below," "lower," "above," and "upper," are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as "first," "second," and the like, are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms "having," "including," "containing," and "containing" are open-ended terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It is to be understood that features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims (15)

1. A method of forming a recess for a trench gate electrode, comprising:
forming a trench in the first major surface of the semiconductor substrate, the trench having a bottom and sidewalls extending from the bottom to the first major surface;
forming a first insulating layer on the bottom and sidewalls of the trench;
inserting a first conductive material into the trench, the first conductive material at least partially covering the first insulating layer to form a field plate in a lower portion of the trench;
applying a second insulating layer to the first major surface and the trench such that the second insulating layer fills the trench and covers the conductive material;
removing the second insulating layer from the first major surface;
the second insulating layer is partially removed from the trench by wet chemical etching, and a recess for a gate electrode is formed in the second insulating layer in the trench.
2. The method of claim 1, wherein the second insulating layer is selectively removed and the first major surface of the semiconductor substrate acts as an etch stop.
3. The method of claim 2, wherein the second insulating layer is selectively removed by chemical mechanical polishing.
4. The method according to claim 2 or claim 3, wherein performing chemical mechanical polishing comprises using a slurry having a polishing selectivity of 100 to 1 of the second insulating layer over the semiconductor substrate.
5. The method of any of claims 1 to 4, wherein the second insulating layer is applied using high density plasma deposition.
6. The method of any of claims 1 to 5, wherein removing the second insulating layer from the trench by wet chemical etching comprises: the semiconductor material at the sidewalls of the trench over the first conductive material is exposed, the first conductive material being covered by a second insulating material.
7. The method of claim 6, further comprising:
forming a third insulating layer on the exposed sidewall, and
a second conductive material is inserted into the recess to form a gate electrode in an upper portion of the trench.
8. The method of any of claims 1-7, wherein inserting a first conductive material comprises:
filling the trench with a first conductive material and applying the first conductive material over the first main surface, an
The first conductive material is removed from the first major surface and from an upper portion of the trench to form a field plate in a lower portion of the trench.
9. The method of claim 8, wherein after forming the field plate, the first insulating layer is removed from sidewalls at an upper portion of the trench to expose semiconductor material of the semiconductor substrate.
10. The method of any of claims 1 to 9, wherein the first and second insulating layers comprise silicon oxide, the semiconductor substrate comprises silicon, and the first conductive material comprises polysilicon.
11. The method of any of claims 1 to 10, further comprising:
forming a body region of the second conductivity type by implantation into the first main surface of the semiconductor substrate, the body region being at a depth d from the first main surfacepnOf semiconductor substrateThe semiconductor material forms a pn-junction, and
a source region is formed over the body region.
12. The method of claim 11, wherein the gate electrode has a depth dgAnd the depth d of the recesspnAnd depth dgThe variation in the difference between is less than dg8% of the total.
13. The method of any of claims 1 to 12, further comprising:
determining the depth d of the recessr1；
The determined depth dr1To a predetermined depth drMaking a comparison, and
the second insulating layer is further removed and the depth of the recess is increased using wet chemical etching.
14. The method of claim 13, further comprising adjusting a composition of the wet chemical etch and/or an etch condition in response to the determined depth.
15. A transistor device, comprising:
a semiconductor substrate having a first major surface and a plurality of transistor cells, each transistor cell comprising:
a trench extending into the semiconductor substrate from the first main surface and having a bottom and sidewalls extending from the bottom to the first main surface;
a field plate in the trench;
a gate electrode in the trench, disposed over and electrically insulated from the field plate; and
a mesa including a drift region, a body region on the drift region, and a source region on the body region,
wherein the content of the first and second substances,
the lower surface of the gate electrode is arranged at a depth d from the first main surfacegAt the position of the air compressor, the air compressor is started,
the body region has a depth d from the first main surfacepnTo form a pn-junction with the semiconductor material of the semiconductor substrate, and
depth dpnAnd depth dgThe variation in the difference between is less than dg8% of the total.
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